JPH05136360A - Electrostatic breakdown protective circuit and semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To present a technique that has advantages in frequency characteristics and protects a JFET adequately from an electrostatic breakdown. CONSTITUTION:JFET's Q2 and Q3 are provided as variable impedance device. The JFET's Q2 and Q3 are in a low impedance state only if the voltage at a signal input terminal exceeds the power supply voltage in a JFET Q1. Consequently, a current caused by an applied voltage is bypassed to the power supply, so that a junction-type gate in the JFET Q1 can be protected from static electricity.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a technique for preventing element destruction due to static electricity, and further to an electrostatic breakdown protection technology for a junction type field effect transistor.
The present invention relates to a technique effectively applied to a semiconductor integrated circuit represented by.

[0002]

2. Description of the Related Art A junction field effect transistor (hereinafter abbreviated as "JFET") having a semiconductor pn junction or a junction between a metal and a semiconductor as a gate is an element which is easily damaged by static electricity applied to the gate. Therefore, a means for preventing it is needed. For example, JFE
In a semiconductor integrated circuit in which T is the first input stage, the J
To prevent FET damage, as shown in Fig. 3, JF
A resistor is inserted between the gate terminal of ET and the power supply line. That is, the gate terminal of the n-channel depletion type JFET Q1 is connected to the resistance R1 for electrostatic breakdown protection.
The resistor R1 is connected to the ground power supply GND via the resistor R1 as a current path to release high-voltage static electricity applied to the signal input terminal.

As another example of the electrostatic breakdown protection circuit, as shown in FIG. 4, an input signal from the outside of the semiconductor integrated circuit is input to the gate terminal of an n-channel depletion type JFET Q1 via a resistor R2. There is a circuit that I tried to input. In this circuit, the resistance R2 reduces the current flowing when a high-voltage static electricity is applied to the signal input terminal, thereby preventing an excessive current from flowing to the gate of the JFET Q1.

As an example of the literature describing the electrostatic breakdown prevention technique, GaAs ICS Sy in 1984 is used.
"Capacitor Dio at mposium
deFET Logic (CDFL) Circuit
ApproachforGaAs D-MESFET
There is IC'S.

[0005]

However, in the circuit configuration shown in FIG. 3, the order of the diodes existing between the gate and the source and between the gate and the drain of the JFET Q1 is higher than the impedance of the resistance R1 for electrostatic breakdown protection. Since the directional impedance is lower, most of the current does not flow in the electrostatic breakdown protection resistor R1 but flows in the diode as a gate current. Even if the voltage applied to the signal input terminal is at a low level of about several tens of volts due to the low forward impedance of this diode, the JF
It has been found by the present inventor that the resistor R1 does not function sufficiently as a protection circuit because an excessive current flows in the gate of the ETQ1 and thereby destroys the junction gate.

In the circuit configuration shown in FIG. 4, an input signal from the outside of the semiconductor integrated circuit is input to the gate terminal of the n-channel depletion type JFET Q1 via the resistor R2 to reduce the current flowing through the gate. J
Although the junction type gate of the FET Q1 can be protected, it has been revealed by the present inventor that it is difficult to operate at a high frequency because the frequency characteristic of the signal input section is deteriorated due to the increase of the input impedance. ..

An object of the present invention is to provide a technique which is excellent in frequency characteristics and which can appropriately perform electrostatic breakdown protection of JFET.

The above and other objects and novel features of the present invention will be apparent from the description of this specification and the accompanying drawings.

[0009]

The outline of a typical one of the inventions disclosed in the present application will be briefly described as follows.

That is, a variable impedance element, which is arranged between the gate of the junction field effect transistor and a power source and is brought into a low impedance state by applying a voltage higher than the power source voltage of the junction field effect transistor, is provided. This is to form an electrostatic breakdown protection circuit. In a more specific aspect, the variable impedance element can be an enhancement junction field effect transistor. At this time, the source terminal or the drain terminal and the gate terminal of the enhancement type junction field effect transistor can be short-circuited,
A resistance for limiting the gate current of the enhancement junction field effect transistor can be provided between the source terminal or the drain terminal and the gate terminal.

Further, the electrostatic breakdown protection circuit is provided in a semiconductor integrated circuit in which a junction field effect transistor is the first input stage.

[0012]

According to the above-mentioned means, the variable impedance element is brought into a high impedance state when the voltage of the signal input terminal of the JFET is lower than the power source voltage, but conversely when it is higher than the power source voltage. The low impedance state causes the power supply to bypass the current resulting from the applied voltage. This is JFET
Prevent the electrostatic damage of. At this time, if the input voltage is within the power supply voltage range, there is no factor that deteriorates the frequency characteristic between the signal input terminal and the gate terminal of the JFET.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIG. 1 shows a circuit of an embodiment of the present invention.

Although not particularly limited, the circuit shown in FIG. 1 is formed on one semiconductor substrate such as single crystal silicon by a known semiconductor integrated circuit manufacturing technique.

In FIG. 1, Q1 is a Schottky type depletion type n-channel JFET having a Schottky junction between a metal and a semiconductor as a gate, although not particularly limited. The JFET Q1 is not particularly limited, but gallium arsenide A GaAs Schottky field effect transistor (GaAs MES FET) of (GaAs) is applied. The basic structure of a GaAs MES FET is that an n-channel GaAs layer is formed on a semi-insulating GaAs layer by a selective ion implantation method, and on this, an alloy type ohmic electrode as a source and a drain, and an n-channel GaAs and a Schottky junction as a gate. The metal to be formed is provided. Therefore, there is a Schottky diode between the gate and the source and between the gate and the drain of the GaAs MES FET, and as described above, there is a risk that the Schottky junction will be destroyed due to an excessive current flowing through the Schottky diode. is there.

In the circuit shown in FIG. 1, a JF as a variable impedance element is used as a protection circuit against electrostatic breakdown.
ETQ2 and Q3 are provided. Although not particularly limited, enhancement type n-channel type GaAs MES FETs are applied to these JFETs Q2 and Q3.
JFET Q2 is a ground power supply (ground level) GND
And the gate terminal of JFETQ1
The ETQ3 is arranged between the negative power supply Vss and the gate terminal of the JFET Q1. The gate terminal of JFETQ2 is coupled to the gate of JFETQ1 and the gate terminal of JFETQ3 is coupled to the negative power supply Vss. In the circuit shown in FIG. 1, the drain terminal of JFET Q2 is the ground power supply GN.
The source terminal of JFET Q3, which is coupled to D, is a negative power source Vs.
Alternatively, the source terminal terminal of JFET Q2 may be coupled to the ground power supply GND and the drain terminal of JFET Q3 may be coupled to the negative power supply Vss.

Here, the operation principle of the electrostatic breakdown protection circuit according to the present invention will be described.

The JFETs Q2 and Q3 are shown in FIG.
It can be thought of as a switch as shown in. J
The gate terminal of the FET Q1 is grounded via the switch S1 and further coupled to the negative power supply Vss via the switch S2. A current path is formed by such a switch.
The impedances of the switches S1 and S2 in the ON state are extremely lower than the forward impedances of the diodes existing between the gate and the source and between the gate and the drain of the JFET Q1. When the switch S1 or S2 is turned on when a voltage within the power supply voltage range is input to the signal input terminal from the outside of the semiconductor integrated circuit, the input signal level from the outside is not correctly transmitted to the JFET Q1 and prevents normal operation. Therefore, the switches S1 and S2 must not turn on when an input voltage within the power supply voltage range is applied to the signal input terminal. Therefore, the switches S1 and S2 are selectively turned on only when a high voltage outside the power supply voltage range is applied to the input terminal due to static electricity or the like, and when an input voltage within the power supply voltage range is applied,
When the switches S1 and S2 are turned off to enter the high impedance state, the input signal at that time is accurately transmitted to the gate terminal of the JFET Q1.

Further, when a signal of a level higher than the ground power supply GND is applied to the input terminal, the switch S1 is turned on, so that it is extremely lower than the forward impedance of the diode existing between the gate and drain of the JFET Q1. An impedance current path is formed, and static electricity or the like flows to the ground power supply GND. And negative power supply Vss
When a lower level signal is applied to the signal input terminal from outside the semiconductor integrated circuit, the switch S2 is turned on,
A current path having an impedance extremely lower than the forward impedance of the diode existing between the gate and the source of the JFET Q1 is formed, and high-voltage static electricity or the like flows to the negative power source Vss via the switch S2. By such an operation, it is possible to prevent the junction type gate from being destroyed due to an excessive current flowing through the gate of the JFET Q1.

In the circuit shown in FIG. 1, since the JFETs Q2 and Q3 are enhancement type FETs, when an input voltage within the power supply voltage range is applied to the signal input terminal from the outside of the semiconductor integrated circuit, the JFETs Q2 and Q3. Reverse bias is applied between the gate and drain, and JFETs Q2 and Q3 are turned off. Therefore, JFETs Q2 and Q3
Is in a high impedance state, and at this time JFETQ1
An input voltage level from outside the semiconductor integrated circuit is directly transmitted to the gate terminal of the.

However, when a level higher than the sum of the level of the ground power supply GND and the threshold voltage VTH of the JFET Q2 is applied to the input terminal, the gate and the drain of the JFET Q2 are forward biased, which causes JFE.
Since TQ2 is turned on, a current path having an impedance extremely lower than the forward impedance of the diode existing between the gate and drain of JFETQ1 is formed, and high voltage static electricity or the like is generated through the path to the ground power supply GN.
She is washed away by D. Also, from the outside of the semiconductor integrated circuit, a negative power source V
The difference between the ss level and the threshold voltage VTH of JFET Q3 (V
When a level lower than (ss-VTH) is applied to the input terminal, the gate-drain of JFETQ3 becomes forward biased and JFETQ3 is turned on. Therefore, the forward impedance of the diode existing between the gate-source of JFETQ1 A current path having an impedance extremely lower than that of the above is configured, and high-voltage static electricity or the like is caused to flow to the negative power source Vss via the path. This prevents the gate of JFET Q1 from being destroyed.

According to the above embodiment, the following operational effects are obtained.

(1) J as a variable impedance element
The FETs Q2 and Q3 are in a high impedance state when the voltage of the signal input terminal of the JFET Q1 is lower than the power supply voltage, but on the contrary, when they are higher than the power supply voltage, they are in a low impedance state. Since the current resulting from the applied voltage can be bypassed to the power supply, the junction gate of the JFET Q1 can be protected from static electricity.

(2) If the input voltage is within the power supply voltage range, there is no impedance such as a resistor that deteriorates frequency characteristics between the signal input terminal and the gate terminal of the JFET for inputting a signal from outside the semiconductor integrated circuit. The frequency characteristics are not deteriorated.

(3) By using JFETs Q2 and Q3 as enhancement type junction field effect transistors, the variable impedance means having the above-mentioned function can be easily realized.

FIG. 2 shows another embodiment of the present invention.

In the circuit shown in FIG. 1, when a high voltage outside the power supply voltage range due to static electricity or the like is applied to the signal input terminal from the outside of the semiconductor integrated circuit, JFETQ2 which is a variable impedance element provided as a protection element. Alternatively, a large potential difference also occurs between the gate and drain (or source) of Q3, causing an excessive gate current to flow and causing JFE
There is a risk of destroying the junction gate of TQ2 or Q3. However, unlike the JFET Q1, the JFETs Q2 and Q3 are not intended to operate at high speed by a signal input to the signal input terminal from outside the semiconductor integrated circuit. Therefore, as shown in FIG. 2, resistors R3 and R4 are added. There is no problem even if the impedance is increased. Therefore, in the embodiment shown in FIG. 2, the gate terminal and the source terminal (or the drain terminal) are connected via a resistor to form a JFET.
By reducing the gate current flowing through Q2 and Q3, the junction type gates of JFETs Q2 and Q3 are protected.

Although the invention made by the present inventor has been specifically described based on the embodiments, the present invention is not limited to the embodiments and various modifications can be made without departing from the scope of the invention. Yes.

For example, in the above embodiment, GaAs MES
Although the case where the FET is applied has been described, other types of JFET can be used. In addition, depending on the configuration of the input circuit in which a signal from the outside of the semiconductor integrated circuit is input to the JFET, J
Either one of the FETs Q2 and Q3 may be used.

In the above description, the case where the invention made by the present inventor is mainly applied to the semiconductor integrated circuit which is the field of application of the background has been described, but the present invention is not limited to this, and for example, a single unit. It can also be applied to a JFET that is commercialized as a component.

The present invention can be applied on condition that at least the JFET is present.

[0032]

The effects obtained by the typical ones of the inventions disclosed in the present application will be briefly described as follows.

That is, the variable impedance element is J
When the voltage of the signal input terminal of the FET is lower than the power supply voltage, it is in a high impedance state, and conversely, when it is higher than the power supply voltage, it is in a low impedance state, which results from the applied voltage. By bypassing the current to the power supply, electrostatic breakdown of the JFET is accurately prevented. Further, if the input voltage is within the power supply voltage range, there is no factor that deteriorates the frequency characteristics between the signal input terminal and the gate terminal of the JFET, so that the frequency characteristics during normal operation are not deteriorated.

[Brief description of drawings]

FIG. 1 is an electrical connection diagram of a circuit according to an embodiment of the present invention.

FIG. 2 is an electrical connection diagram of a circuit of another embodiment of the present invention.

FIG. 3 is an electrical connection diagram of a conventional circuit.

FIG. 4 is an electrical connection diagram of a conventional circuit.

FIG. 5 is an operation ionization diagram of the electrostatic breakdown protection circuit according to the present invention.

[Explanation of symbols]

 GND Ground power supply Vss Negative power supply Q1 Depletion type JFET Q2, Q3 Enhancement type JFET D Drain terminal S Source terminal G Gate terminal R1, R2 Resistor R3, R4 Resistor S1, S2 switch

Claims (5)

[Claims] 1. An electrostatic breakdown protection circuit for a junction field effect transistor, wherein a voltage higher than a power supply voltage of the junction field effect transistor is applied between the gate of the junction field effect transistor and a power supply. An electrostatic breakdown protection circuit including a variable impedance element that is brought into a low impedance state by being subjected to the electrostatic discharge protection circuit. 2. The electrostatic breakdown protection circuit according to claim 1, wherein the variable impedance element is an enhancement type junction field effect transistor. 3. The electrostatic breakdown protection circuit according to claim 2, wherein the source terminal or the drain terminal of the enhancement type junction field effect transistor and the gate terminal are short-circuited. 4. The electrostatic breakdown protection circuit according to claim 2, wherein a resistor is provided between the source terminal or the drain terminal and the gate terminal of the enhancement type junction field effect transistor. 5. A semiconductor integrated circuit having a junction field effect transistor as an input first stage, the semiconductor integrated circuit including the electrostatic breakdown protection circuit according to claim 1, 2, 3 or 4.