JPH0548021A - Semiconductor protective circuit - Google Patents

Semiconductor protective circuit

Info

Publication number
JPH0548021A
JPH0548021A JP3200196A JP20019691A JPH0548021A JP H0548021 A JPH0548021 A JP H0548021A JP 3200196 A JP3200196 A JP 3200196A JP 20019691 A JP20019691 A JP 20019691A JP H0548021 A JPH0548021 A JP H0548021A
Authority
JP
Japan
Prior art keywords
diode
channel transistor
internal circuit
resistor
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3200196A
Other languages
Japanese (ja)
Inventor
Tsutomu Endo
勉 遠藤
Original Assignee
Sumitomo Metal Ind Ltd
住友金属工業株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Ind Ltd, 住友金属工業株式会社 filed Critical Sumitomo Metal Ind Ltd
Priority to JP3200196A priority Critical patent/JPH0548021A/en
Publication of JPH0548021A publication Critical patent/JPH0548021A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent induction of a latch-up by separating an input terminal from a circuit side within a substrate by allowing a specified voltage to be applied to a gate of a P-channel transistor or an N-channel transistor when a current exceeding a specified level flows to a diode or an N<+> diode for turning off the transistor. CONSTITUTION:When an input voltage is applied outside a threshold voltage range, a depletion-type N-channel transistor 14, a depletion-type P-channel transistor 13, and a P<+> diode 15 are in conduction state, a potential at a,junction point 22 is clamped, and then an internal circuit 27 is protected. At this time, when a current flowing to a polysilicon resistor 20 exceeds a specified value, the depletion-type P-channel transistor 13 is turned off and then an input terminal 11 and the internal circuit 27 are separated, thus preventing a latch-up from being induced.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor protection circuit, and more particularly to a semiconductor protection circuit interposed between an input terminal and a board internal circuit.

[0002]

2. Description of the Related Art The voltage-current characteristic of a diode has a characteristic that a current suddenly starts flowing when a voltage of a certain threshold is exceeded and a current does not flow in the opposite direction. Usually, the oxide film thickness of the gate portion of the transistor in the internal circuit is very thin, and thus a dielectric breakdown may easily occur at a low voltage of several tens of volts. In such a case, most of the products will be destroyed during the handling if they are left as they are. Therefore, a gate protection circuit is added to all the input terminals in some form.

FIG. 2 is a circuit diagram showing an example of a conventional input gate protection circuit and an internal circuit side (transistor technology SPEC).
IAL No.4 Special Feature C-MOS Standard Logic IC Application Manual
). Reference numeral 56 in the drawing denotes an input gate protection circuit, and the input terminal 41 is connected via a resistor 49 to an internal circuit 57 having the input protection terminal 42 built therein. A connection line branches between the resistor 49 and the input protection terminal 42, one of which is connected to the power supply voltage 55 via the P + diode 45 as a clamp element, and the other of which is an N + diode as a clamp element. It is connected to a ground terminal 47 via 46.

The internal circuit 57 branches from the input protection terminal 42, one of which is connected to the base of the P-channel transistor 53, the emitter of the P-channel transistor 53 is connected to the power supply voltage 55, and is connected to the output terminal 48 side. ..
The other is connected to the base of the N-channel transistor 54, the emitter of the N-channel transistor 54 is connected to the ground terminal 47, and the collector is connected to the output terminal 48 side.

The semiconductor protection circuit 56 thus configured
When a high voltage of + or-is applied to, since the P + diode 45 and the N + diode 46 are provided,
The high voltage is clamped by the current flowing to the side of the diodes 45 and 46, and the gate oxide films of the transistors 53 and 54 in the internal circuit 57 can be protected.

[0006]

However, in the above-described conventional input gate protection circuit 56, for example, the input voltage is the power supply voltage V DD + (V of the input protection diode 45).
If it is higher than F ), the input current will suddenly increase. If a voltage of V DD + 2V is applied to the input terminal 41, a diode 45 is connected between the input terminal 41 and the power supply voltage 55.
Then, a potential difference of 1.5 V is generated by subtracting V F (assumed to be 0.5 V), and an overcurrent flows from the input terminal 41 toward the power supply voltage 55. When this current exceeds the specified input current (± 20 mA), it becomes a trigger current, which causes a problem that latch-up is induced.

The present invention has been invented in view of the above problems. It is possible to prevent overcurrent from occurring even when a high voltage is applied to the input terminal and prevent latch-up. Another object of the present invention is to provide a semiconductor protection circuit capable of protecting the gate breakdown of the transistor of the internal circuit.

[0008]

[Means for Solving the Problems] To achieve the above object
The semiconductor protection circuit according to the present invention is
Between the internal input terminal of the transistor of the internal circuit on the circuit side
Via a resistor to the depletion type P-channel and
N-channel transistors are connected in series,
Between the transistor and the internal input terminal on the internal circuit side of the board.
Has a branch point, one of which is P + Diode and
Connected to the power supply voltage on the board side via a resistor
The other from the point is N + The substrate through a diode and a resistor
Connected to the ground terminal on the side of the
Gate electrode is P + Connect between the diode and the resistor.
And the gate electrode of the N-channel transistor is
Note N + Be connected between the diode and the resistor.
And are characterized.

[0009]

According to the above structure, the depletion type P channel and the N channel are connected via the resistor between the input terminal and the internal input terminal of the transistor of the internal circuit on the substrate internal circuit side.
Channel transistors are connected in series, and there is a branch point between these transistors and the internal input terminal on the substrate internal circuit side, and one of the branch points is connected to the power supply voltage on the substrate side via the P + diode and the resistor. The other end is connected to the ground terminal on the substrate side through an N + diode and a resistor, and the gate electrode of the P-channel transistor is connected between the P + diode and the resistor. Since the gate electrode of the channel transistor is connected between the N + diode and the resistor, the potential at the input terminal is clamped by the P + diode or the N + diode when a high voltage is applied to the input terminal. The internal circuit is protected.

Further, the P + diode or the N
When a current larger than a predetermined current flows through the + diode, a predetermined voltage is applied to the gate of the P-channel transistor or the N-channel transistor, and these transistors are turned off.

Therefore, the input terminal and the internal circuit side of the substrate are separated from each other, and the induction of latch-up is prevented.

[0012]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a semiconductor protection circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram showing a semiconductor protection circuit according to the present embodiment, and 26 in the figure shows a semiconductor protection circuit. The input terminal 11 is connected in series via a polysilicon resistor 19 to a depletion type N-channel transistor 14 and a depletion type P-channel transistor 13 in this order, and is further connected to an input protection terminal 12 in an internal circuit 27. A branch point N 1 is formed between the depletion type P-channel transistor 13 and the input protection terminal 12, and one connection line 29 branched from the branch point N 1 is connected via the P + diode 15 and the polysilicon resistor 20. It is connected to the power supply voltage 25, and the other connection line 30 is connected to the ground terminal 17 via the N + diode 16 and the resistor 21. Further, a branch point N 2 between the P + diode 15 and the polysilicon resistor 20
Is connected to the gate electrode of the depletion type N-channel transistor 13, and similarly, the branch point N 3 between the N + diode 16 and the resistor 21 is connected to the gate electrode of the depletion type N-channel transistor 14.

The internal circuit 27 branches from the input protection terminal 12, one of which is connected to the gate electrode of the P-channel transistor 23, the drain electrode of the P-channel transistor 23 is connected to the power supply voltage 25, and the source electrode is connected to the output terminal 18. Is connected to the side. The other is connected to the gate electrode of the N-channel transistor 24, the drain electrode of the N-channel transistor 24 is connected to the ground terminal 17, and the source electrode is connected to the output terminal 18 side.

In the semiconductor protection circuit 26 configured as described above, for example, the polysilicon resistor 19 is set to 300.
Ω, polysilicon resistance 20, 21 to 30Ω, power supply voltage 2
5, 5V, ground terminal 17 0V, depletion type P-channel transistor 13 threshold value 5.5V, depletion type N-channel transistor 14 threshold value -0.5V, P + diode 15 and N + diode 16 The voltage at which the clamp current starts to flow is 0.6V,
Set the specified input current to ± 20 mA. Input terminal 11
When the input voltage is applied to the input terminal in the range of -0.6V to 5.6V, the depletion type P-channel transistor 1
3 and depletion type N-channel transistor 14
Becomes conductive, while P + diode 15 and N +
The diode 16 becomes non-conductive. Therefore, the internal circuit 2
7 works normally.

When the input voltage is thus set within the threshold voltage range, the P + diode 15 and the N + diode 16 do not conduct, and the depletion type P-channel transistor 13 and the depletion type N are provided.
The channel transistor 14 becomes conductive, and the internal circuit 27 operates normally.

On the other hand, when the input voltage is applied outside the threshold voltage range, for example, when a voltage of 5.6 V or more is applied to the input terminal 11, the depletion type N-channel transistor 14 and the depletion type P-channel transistor are provided. 13 and P + diode 15 are rendered conductive, the potential at branch point 22 is clamped, and internal circuit 27 is protected. At this time, if the current flowing through the polysilicon resistor 20 exceeds 17 mA, the potential between the polysilicon resistor 20 and the P + diode 15 becomes 5.5.
When the voltage exceeds V, the depletion type P-channel transistor 13 is turned off, and the input terminal 11 and the internal circuit 27 are disconnected. As a result, a current of about 20 mA or more is prevented from flowing in the internal circuit 27, and the induction of latch-up is prevented.

On the contrary, when an input voltage of -0.6 V or less is applied to the input terminal 11, the depletion type N-channel transistor 14, the depletion type P-channel transistor 13 and the N + diode 16 become conductive, and the branch point 22. The potential at is clamped to protect internal circuit 27. At this time, when the current flowing through the resistor 21 becomes 17 mA, the potential between the resistor 21 and the N + diode 16 becomes −0.5 V or less, the depletion type N-channel transistor 14 turns off, and the input terminal 11 and the internal circuit 27. And are separated. As a result, a current of about 20 mA or more is prevented from flowing in the internal circuit 27, and the induction of latch-up is prevented.

In the semiconductor protection circuit according to the embodiment described above, the gates of the transistors 23 and 24 in the internal circuit 27 can be protected even when a high voltage is applied to the input terminal 11. It is also possible to prevent the induction of latch-up due to overcurrent. Therefore, even when the breakdown voltage of the gate oxide film of the transistors 23 and 24 in the internal circuit 27 is close to the power supply voltage, the internal circuit 27 can be sufficiently protected, and the depletion type P-channel transistor 13 and the depletion type N-channel can be protected. Turning off the transistor 14 makes it possible to provide a semiconductor protection circuit having a long life.

[0019]

As described above in detail, in the semiconductor protection circuit according to the present invention, the depletion type is provided through the resistor between the input terminal and the internal input terminal of the transistor of the internal circuit on the substrate internal circuit side. P-channel and N-channel transistors are connected in series, and there is a branch point between these transistors and the internal input terminal on the substrate internal circuit side, and one of the branch points is connected to the substrate via a P + diode and a resistor. Is connected to the power supply voltage on the side, the other end is connected to the ground terminal on the side of the substrate through the N + diode and the resistor, and the gate electrode of the P-channel transistor is between the P + diode and the resistor. connected, the gate electrode of the N-channel transistor is connected between the resistor and the N + diode, when a high voltage is applied, the + Diode or the N +
While the diode is conducting to protect the internal circuit,
When the depletion type P-channel transistor or the depletion type N-channel transistor is turned off, the induction of latch-up can be prevented. Therefore, even when the breakdown voltage of the gate oxide film is close to the power supply voltage, the internal circuit can be sufficiently protected from a high voltage, and further, the induction of latch-up caused by an overcurrent can be prevented and a long-life semiconductor protection circuit can be provided. Can be provided.

[Brief description of drawings]

FIG. 1 is a schematic block diagram showing an embodiment of a semiconductor protection circuit according to the present invention.

FIG. 2 is a schematic block diagram showing a conventional semiconductor protection circuit.

[Explanation of symbols]

11 Input Terminal 12 Input Protection Terminal 13 Depletion Type P-Channel Transistor 14 Depletion Type N-Channel Transistor 15 P + Diode 16 N + Diode 17 Earth Terminal 20 Polysilicon Resistor 21 Polysilicon Resistor 25 Power Supply Voltage 26 Semiconductor Protection Circuit 27 Internal Circuit

Claims (1)

[Claims]
1. A depletion-type P-channel and N-channel transistor is connected in series via a resistor between an input terminal and an internal input terminal of a transistor of an internal circuit on the substrate internal circuit side, and these transistors and the substrate are connected. A branch point is formed between the internal input terminal on the internal circuit side and one of the branch points is connected to the power supply voltage on the substrate side through the P + diode and the resistor, and the other branch point is connected to the N + diode and It is connected to the ground terminal on the substrate side through a resistor, and the gate electrode of the P-channel transistor is P
+ Diode connected between said resistor, semiconductor protection circuit gate electrode of said N-channel transistor is characterized in that it is connected between the resistor and the N + diode.
JP3200196A 1991-08-09 1991-08-09 Semiconductor protective circuit Pending JPH0548021A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3200196A JPH0548021A (en) 1991-08-09 1991-08-09 Semiconductor protective circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3200196A JPH0548021A (en) 1991-08-09 1991-08-09 Semiconductor protective circuit

Publications (1)

Publication Number Publication Date
JPH0548021A true JPH0548021A (en) 1993-02-26

Family

ID=16420403

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3200196A Pending JPH0548021A (en) 1991-08-09 1991-08-09 Semiconductor protective circuit

Country Status (1)

Country Link
JP (1) JPH0548021A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227976A (en) * 1994-10-19 1996-09-03 Siliconix Inc Static discharge protective device for integrated circuit
JPH09116023A (en) * 1995-10-16 1997-05-02 Nec Corp Input protecting circuit for semiconductor integrated circuit device
JPH09186247A (en) * 1995-11-28 1997-07-15 Lg Semicon Co Ltd Static discharge and latch-up preventive circuit
JP2006156563A (en) * 2004-11-26 2006-06-15 Nec Electronics Corp Semiconductor device
JP2012199285A (en) * 2011-03-18 2012-10-18 Fujitsu Semiconductor Ltd Semiconductor element, method of manufacturing semiconductor element, and transistor circuit
JP2013211522A (en) * 2012-03-02 2013-10-10 Yokogawa Electric Corp Input protective circuit
US10426431B2 (en) 2014-11-19 2019-10-01 Canon Kabushiki Kaisha Protection circuit

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH08227976A (en) * 1994-10-19 1996-09-03 Siliconix Inc Static discharge protective device for integrated circuit
JPH09116023A (en) * 1995-10-16 1997-05-02 Nec Corp Input protecting circuit for semiconductor integrated circuit device
JPH09186247A (en) * 1995-11-28 1997-07-15 Lg Semicon Co Ltd Static discharge and latch-up preventive circuit
JP2006156563A (en) * 2004-11-26 2006-06-15 Nec Electronics Corp Semiconductor device
JP4647294B2 (en) * 2004-11-26 2011-03-09 ルネサスエレクトロニクス株式会社 Semiconductor device
JP2012199285A (en) * 2011-03-18 2012-10-18 Fujitsu Semiconductor Ltd Semiconductor element, method of manufacturing semiconductor element, and transistor circuit
JP2013211522A (en) * 2012-03-02 2013-10-10 Yokogawa Electric Corp Input protective circuit
KR101454766B1 (en) * 2012-03-02 2014-10-27 요코가와 덴키 가부시키가이샤 Input protection circuit
US10426431B2 (en) 2014-11-19 2019-10-01 Canon Kabushiki Kaisha Protection circuit

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