JPH09116023A - Input protecting circuit for semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To protect internal elements stably and to make it possible to input a high-voltage signal without damaging the reliability by providing specific n-channel type first and second MOS transistors, stabilizing the operation start voltage of an electrostatic protective circuit, and preventing the change of the electrostatic durability. SOLUTION: An n-channel type first MOS transistors M2 is provided with the gate electrode connected to a power terminal 3, with the drain electrode to an input terminal 1, with the source electrode to a free terminal, and with the foundation electrode to a grounding terminal 4. Besides, an n-channel type second MOS transistor M3 is provided with the gate and drain electrodes connected to the power terminal 3, with the source electrode to a free terminal, and the foundation electrode to the grounding electrode 4. That is, the operation start voltage of the electrostatic protective circuit in an input protecting circuit is determined by the breakdown withstand voltages between the drain electrodes of the n-channel MOS transistors M2, M3 and a P-type substrate. Consequently, it becomes possible to prevent the deterioration of the electrostatic durability.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit for a semiconductor integrated circuit device having a CMOS transistor structure,
In particular, the present invention relates to an input protection circuit for protecting an internal signal processing circuit from high voltage such as static electricity.

[0002]

2. Description of the Related Art In recent years, the progress of miniaturization in semiconductor integrated circuit devices has been remarkably advanced, and the gate oxide film thickness of MOS transistors tends to be further reduced. The standard power supply voltage has been lowered from 5V, which has been used for many years, to 3.3V and 2.5V in order to prevent the reliability from being lowered due to miniaturization and thinning. Therefore, when a system is constructed using various semiconductor integrated circuit devices, for example, 5
The output signal of the semiconductor integrated circuit device of V power supply is input to the semiconductor integrated circuit device of 3.3 V power supply. As an input protection circuit capable of inputting a signal having a voltage higher than the power supply voltage of its own, there is a 1992 symposium on brussels circus digest of technical paper (1992 Sy.
mpodium on VLSI Circuits
Digest of Technical Paper
r), paper published on pages 90-91, Highly Reliable Process Insensitive 3.3V-
5V Interface Circuits (Highly R
Eliable Process Intensity
ve 3.3V-5V Interface Circ
Uit). The input protection circuit described in the above paper will be described below.

In the conventional input protection circuit shown in FIG. 3, an n-channel MOS transistor M1 is connected between an input terminal 1 and an output terminal 2. Due to the n-channel MOS transistor M1, the potential of the output terminal 2 is
It rises only up to a value lower than the potential of by the threshold voltage of the n-channel MOS transistor M1. Therefore, a voltage higher than the power supply voltage is not applied to the internal circuit (not shown) connected to the output terminal 2, and the reliability of the internal circuit is not impaired. Further, since the gate electrode of the n-channel MOS transistor M1 itself is connected to the power supply terminal, even if a signal having a voltage higher than the power supply voltage is applied to the input terminal 1, the gate between the gate electrode and the input terminal 1 or the drain electrode is The voltage applied to the oxide film is only the value obtained by subtracting the power supply voltage from the maximum voltage of the input signal, and the reliability is likewise not impaired.

Parasitic npn bipolar transistor Q1,
Q2 is provided to prevent damage due to static electricity. A cross section of this transistor is shown in FIG. The static electricity protection circuit does not affect the normal circuit operation, and it is desired to discharge quickly only when a high voltage pulse such as static electricity is applied. The parasitic npn bipolar transistor shown in FIG. 4 has n-type diffusion layers 31 and 32, a p-type silicon substrate 33, and a silicon oxide which are simultaneously formed when forming a source / drain and an element isolation region of an n-channel MOS transistor. And the film 34. n-type diffusion layer 31
Alternatively, p formed by 32 and p-type silicon substrate 33
It will not work unless the n-junction is forward biased or reverse biased and breakdown occurs.

The operation when an electrostatic pulse is applied to the input terminal 1 will be described below. When a positive electrostatic pulse is applied to the input terminal 1 with respect to the ground terminal 4, the pn junction between the collector and the base of the parasitic npn bipolar transistor Q2 is in a reverse bias state, and a breakdown current becomes a base due to the high voltage. Flowing. The current to the base raises the base potential due to the parasitic resistance, and the parasitic np
The n-bipolar transistor Q2 is turned on and discharged to protect the internal elements.

When a negative-polarity electrostatic pulse is applied to the input terminal 1 with respect to the ground terminal 4, the pn junction between the collector and the base of the parasitic npn bipolar transistor Q2 becomes a forward bias state and discharge is performed, and the internal element is discharged. Be protected.

When a positive electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the pn junction between the emitter and the base of the parasitic npn bipolar transistor Q1 is in a reverse bias state and a breakdown current is generated due to the high voltage. It flows to the base. The current to the base raises the base potential due to the parasitic resistance, the parasitic npn bipolar transistor Q1 is turned on and discharged, and the internal element is protected.

When a negative electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the pn junction between the collector and the base of the parasitic npn bipolar transistor Q1 is in a reverse bias state and a breakdown current is generated due to the high voltage. It flows to the base. The current to the base raises the base potential due to the parasitic resistance, the transistor Q1 is turned on and discharging is performed, and the internal element is protected.

[0009]

As described above, the conventional high voltage signal input protection circuit has a parasitic npn for electrostatic protection.
A bipolar transistor is used, and the breakdown voltage between the collector and the base or the emitter and the base serves as a trigger for starting the operation except when a negative electrostatic pulse is applied between the input terminal and the ground terminal.
Therefore, when the element isolation method is changed, for example, when trench isolation is adopted for high integration, the breakdown voltage becomes high and the protection function cannot be fulfilled. Speaking of the conventional input protection circuit shown in FIG. 3, the minimum channel length is 0.5 μm.
In the conventional manufacturing process, the breakdown withstand voltage of about 11V in the case of the conventional LOCOS isolation is increased to about 16V by adopting the trench isolation, and the n-channel MOS transistor M1 is destroyed. is there. The change in breakdown voltage due to the difference in the isolation method is because the breakdown between the p-type substrate and the n-type diffusion layer is caused by the electric field concentration near the surface of the boundary with the element isolation region. In order to avoid these, it is necessary to newly build an electrostatic protection-like element that is not a simple parasitic element, which has a drawback that the number of manufacturing steps increases.

[0010]

An input protection circuit for a semiconductor integrated circuit device according to the present invention is provided on a chip of a semiconductor integrated circuit device having a CMOS transistor structure, a gate electrode connected to a power supply voltage supply terminal, and a drain. An n-channel first MOS transistor having an electrode connected to a signal input terminal, a substrate electrode connected to a ground terminal, and a source electrode opened; and a gate electrode and a drain electrode connected to the power supply voltage supply terminal, The n-channel second M in which the substrate electrode is connected to the ground terminal and the source electrode is released.
And an OS transistor.

In the input protection circuit of the semiconductor integrated circuit device, the collector electrode is connected to the power supply voltage supply terminal, the emitter electrode is connected to the signal input terminal, and the base electrode is connected to the ground terminal. An npn-type first bipolar transistor, and an npn-type second bipolar transistor having a collector electrode connected to the signal input terminal and an emitter electrode and a base electrode connected to the ground terminal. .

Further, in the input protection circuit of the semiconductor integrated circuit device, a current path is connected between the signal input terminal and a signal input point of a signal processing circuit for receiving a signal from the input protection circuit. Then, an n-channel MOS transistor of a transfer gate having a gate electrode connected to the power supply voltage supply terminal and a substrate electrode connected to the ground terminal is provided.

[0013]

BEST MODE FOR CARRYING OUT THE INVENTION Next, embodiments of the present invention will be described in detail with reference to the drawings. FIG. 1 is a circuit diagram showing a first embodiment of the present invention. An n-channel M in which the gate electrode is connected to the power supply terminal 3, the drain electrode is connected to the input terminal 1, the source electrode is connected to the open end, and the substrate electrode is connected to the ground terminal 4.
The OS transistor M2, an n-channel MOS transistor M in which the gate electrode and the drain electrode are connected to the power supply terminal 3, the source electrode is connected to the open end, and the substrate electrode is connected to the ground terminal 4.
3 is included. Similar to the conventional input protection circuit shown in FIG. 3, an n-channel MOS transistor M1 is connected between the input terminal 1 and the output terminal 2 so that the potential of the output terminal 2 does not rise above the potential of the power supply terminal 3. .

The operation when an electrostatic pulse is applied to the input terminal 1 will be described below. When a positive electrostatic pulse is applied to the input terminal 1 with respect to the ground terminal 4,
The drain electrode (n-type diffusion layer) of the channel MOS transistor M2 and the p-type substrate are in a reverse bias state to cause breakdown and discharge, thereby protecting the internal circuit.

When a negative electrostatic pulse is applied to the input terminal 1 with respect to the ground terminal 4, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2 and the p-type substrate are in a forward bias state. By doing so, the internal circuit is protected.

When a positive electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2 and the p-type substrate are in a reverse bias state and break down. Occurs and discharges via the forward-biased pn junction between the p-type substrate and the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M3, thereby protecting the internal circuit.

When a negative electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M3 and the p-type substrate are in a reverse bias state and break down. Occurs and discharges via the forward biased pn junction between the p-type substrate and the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2, thereby protecting the internal circuit.

As described above, the operation start voltage of the electrostatic protection circuit in the input protection circuit is determined by the breakdown withstand voltage between the drain electrodes (n-type diffusion layers) of the n-channel MOS transistors M2 and M3 and the p-type substrate. It
The n-channel MOS transistors (M2, M3) are not parasitic elements and are manufactured in the same manner as the n-channel MOS transistor M1. Therefore, the relative breakdown voltage does not change even if the manufacturing method is changed, and is particularly high. Even if the method of forming the element isolation region is changed for integration, the breakdown withstand voltage does not change. For example, even if the LOCOS isolation is changed to the trench isolation in the manufacturing process with the minimum channel length of 0.5 μm, the breakdown voltage is 1
There is no change at around 0V. Therefore, by changing the element isolation method as in the conventional case, the n-channel MOS transistor M1
No longer causes static electricity damage. That is,
It can be said that the input protection circuit is suitable for miniaturization because it has little dependency on the manufacturing process.

Next, a second embodiment of the present invention will be described with reference to FIG.
This will be described in detail with reference to FIG. Similar to the first embodiment, the gate electrode is the power supply terminal 3 and the drain electrode is the input terminal 1.
In addition, the n-channel MOS transistor M2 having the source electrode at the open end, the substrate electrode connected to the ground terminal 4, the gate electrode and the drain electrode at the power supply terminal 3, the source electrode at the open end, and the substrate electrode at the ground terminal 4 And an n-channel MOS transistor M3 connected to. Similar to the conventional input protection circuit shown in FIG. 3, the n-channel MOS transistor M1 is provided with an input terminal 1 and an output terminal 2 so that the potential of the output terminal 2 does not rise above the potential of the power supply terminal 3.
Connected between them. The parasitic npn bipolar transistors Q1 and Q2 are connected between the input terminal 1, the power supply terminal 3, and the ground terminal for electrostatic protection, as in the conventional input protection circuit shown in FIG.

The operation when an electrostatic pulse is applied to the input terminal 1 will be described below. Input terminal 1
When a positive electrostatic pulse is applied to the ground terminal 4, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2 and the p-type substrate are reverse-biased and breakdown occurs, and this breakdown current is generated. The base resistance of the parasitic npn bipolar transistor Q2 is raised by the parasitic resistance, and the parasitic npn bipolar transistor Q2
By turning on 2 and discharging, the internal circuit is protected.

When a negative electrostatic pulse is applied to the input terminal 1 with respect to the ground terminal 4, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2, the p-type substrate and the collector of the parasitic npn bipolar transistor Q2.・
The internal circuit is protected by the forward bias between the bases and discharge.

When a positive electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M2 and the p-type substrate are in a reverse bias state and break. The breakdown occurs, and this breakdown current raises the base potential of the parasitic npn bipolar transistor Q1 due to the parasitic resistance.
The internal circuit is protected by turning on and discharging the n-bipolar transistor Q1.

When a negative electrostatic pulse is applied to the input terminal 1 with respect to the power supply terminal 3, the drain electrode (n-type diffusion layer) of the n-channel MOS transistor M3 and the p-type substrate are in a reverse bias state and break down. This breakdown current raises the base potential of the parasitic npn bipolar transistor Q1 due to the parasitic resistance, and the parasitic npn
The internal circuit is protected by turning on and discharging the bipolar transistor Q1.

As described above, in the second embodiment, the parasitic npn bipolar transistors Q1 and Q2 are generated by the breakdown current between the drains (n type diffusion layers) of the n channel MOS transistors M2 and M3 and the p type substrate. Is turned on to discharge static electricity. Therefore, as in the first embodiment, since the n-channel MOS transistors M2 and M3 are manufactured in the same manner as the n-channel MOS transistor M1 instead of being a parasitic element, the manufacturing method is different for the relative breakdown breakdown voltage. Even if it does not change, it can be said that it is an input protection circuit suitable for miniaturization with little dependence on the manufacturing process.

Although the degree of integration of the input protection circuit is inferior to that of the first embodiment, the first embodiment has an n-channel M channel.
While the discharge is performed only by the breakdown current of the OS transistor, by utilizing the operation of the bipolar transistor, the resistance at the time of discharge can be reduced, and there is an effect that it is resistant to thermal destruction.

[0026]

As described above, the input protection circuit of the semiconductor integrated circuit device of the present invention can stabilize the operation start voltage of the electrostatic protection circuit without depending on the change of the element isolation method and the like. As a result, it is possible to prevent fluctuations in static electricity resistance and protect internal elements in a stable manner, and to input a signal of a voltage higher than its own power supply voltage without impairing reliability, which is very suitable for miniaturization. effective.

[Brief description of the drawings]

FIG. 1 is a circuit diagram according to a first embodiment of the present invention.

FIG. 2 is a circuit diagram according to a second embodiment of the present invention.

FIG. 3 is a circuit diagram showing an example of a conventional input protection circuit.

FIG. 4 is a cross-sectional view of a parasitic npn bipolar transistor.

[Explanation of symbols] 1 input terminal 2 output terminal 3 power supply terminal 4 ground terminal 31 n-type diffusion layer (collector) 32 n-type diffusion layer (emitter) 33 p-type silicon substrate 34 silicon oxide film

Claims (4)

[Claims] 1. A semiconductor integrated circuit device having a CMOS transistor structure, which is provided on a chip, has a gate electrode connected to a power supply voltage supply terminal, a drain electrode connected to a signal input terminal, and a substrate electrode connected to a ground terminal. An n-channel first MOS transistor having a source electrode released, a gate electrode and a drain electrode connected to the power supply voltage supply terminal, a substrate electrode connected to the ground terminal, and a source electrode released n An input protection circuit for a semiconductor integrated circuit device, comprising: a channel-type second MOS transistor. 2. The input protection circuit for a semiconductor integrated circuit device according to claim 1, wherein a collector electrode is connected to the power supply voltage supply terminal, an emitter electrode is connected to the signal input terminal, and a base electrode is the ground terminal. An npn-type first bipolar transistor connected to the npn transistor, a collector electrode connected to the signal input terminal, and an emitter electrode and a base electrode connected to the ground terminal.
Type second bipolar transistor, and an input protection circuit for a semiconductor integrated circuit device. 3. The input protection circuit for a semiconductor integrated circuit device according to claim 1, wherein a current flows between the signal input terminal and a signal input point of a signal processing circuit that receives a signal from the input protection circuit. A semiconductor integrated circuit, which is provided with an n-channel MOS transistor of a transfer gate, which is connected so as to form a path, a gate electrode is connected to the power supply voltage supply terminal, and a substrate electrode is connected to the ground terminal. Device input protection circuit. 4. The input protection circuit of the semiconductor integrated circuit device according to claim 2, wherein a p-type silicon crystal substrate is used as a substrate of the chip, and the first and second bipolar transistors are the p-type silicon crystal. A substrate serves as a base region, and two n-type regions formed in the p-type silicon crystal substrate and in contact with the element isolation region are defined as collector regions or emitter regions. An input protection circuit for a semiconductor integrated circuit device having a structure.