JP3334741B2 - Semiconductor input circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor input circuit used in a semiconductor integrated circuit.
The present invention relates to a semiconductor input circuit suitable for an integrated circuit formed on a substrate (ilocon On Insurator).

[0002]

2. Description of the Related Art FIG. 4 is a diagram showing a configuration of a conventional semiconductor input circuit SI4.

The conventional semiconductor input circuit SI4 includes a surge protection circuit 20 and a signal level lowering circuit 40.

The semiconductor input circuit SI4 inputs a signal from the pad 10, and an input signal line L1 is connected between the pad 10 and an input terminal of the surge protection circuit 20, and the input signal line L1 is connected to a signal level lowering circuit. It is connected to 40 input terminals. The output terminal of the signal level lowering circuit 40 is connected to the input terminal of the internal circuit 50 via the output signal line L2, and the power supply line VDD of the signal level lowering circuit 40 and the power supply line VDD of the internal circuit 50 are common.

The surge protection circuit 20 is an N-channel MOS
Transistor 21 and N-channel MOS transistor 22
It is composed of N channel MOS transistor 2
1 has a drain connected to the pad 10, a gate connected to a high-potential power supply line VDD in the LSI,
Its source is connected to the drain of N-channel MOS transistor 22. The gate and source of the N-channel MOS transistor 22 are connected to a low-potential power supply line GND in the LSI.

The signal level lowering circuit 40 has an N-channel M
It comprises an OS transistor 41, a P-channel MOS transistor 42, and an inverter 43. N channel MOS transistor 41 has its drain connected to the input terminal of signal level lowering circuit 40, its gate connected to high potential power supply line VDD, and its source connected to
The drain of the P-channel MOS transistor 42 and the input terminal of the inverter 43 are connected. P channel M
The OS transistor 42 has a gate connected to the inverter 4
3 and the source thereof is connected to the high-potential power supply line VDD. The output terminal of the inverter 43 is connected to the input terminal of the internal circuit 50.

In the conventional semiconductor input circuit SI4, if the voltage of the high potential power supply line VDD is set to, for example, 2.0 V, the high level is 3.3 V and the low level is 0 during the operation.
A V signal is input, that is, a high-level voltage is input at a value higher than the voltage of the high-potential power supply line VDD.

Here, a surge protection circuit 20 is constituted by two-stage N-channel MOS transistors 21 and 22 connected in cascade, and a breakdown occurs between the source and drain of each of the N-channel MOS transistors 21 and 22. Designed not to wake up. This point is disclosed in JP-A-7-160033.

Further, the signal level lowering circuit 40 lowers the high level 3.3V of the input signal to the voltage value of VDD of 2.0V and outputs the same. This point is described in JP-A-62-14.
No. 5918. MOS in internal circuit 50
The high level 3.3 of the input signal is applied to the gate of the transistor.
When V is applied, the reliability of the gate oxide film is reduced. To prevent this reduction in reliability, the level of the input signal is reduced. That is, in the signal level lowering circuit 40,
The 3.3 V high-level input input to the drain terminal of the N-channel MOS transistor 41 has its source
VDD-Vthn (Vthn is the threshold voltage of the N-channel MOS transistor).

Then, the P-channel MOS transistor 4
2 sets the potential of the input terminal of the inverter 43 (the source terminal of the N-channel MOS transistor 41) from VDD-Vthn to V
It has been raised to DD. That is, the potential of the input terminal of the inverter 43 is not raised to VDD, and VDD-Vthn
If left as it is, both the N-channel MOS transistor and the P-channel MOS transistor constituting the inverter 43 are turned on, and flow from the terminal VDD to GND as a leak current, but the potential of the input terminal of the inverter 43 is raised to VDD. For example, both the N-channel MOS transistor and the P-channel MOS transistor constituting inverter 43 do not turn on, and no leak current flows.

FIG. 5 is a diagram showing paths R2 and R3 through which a surge current flows to the high potential power supply line VDD when a surge current flows into the conventional semiconductor input circuit SI4.

Although there is a path through which the surge current passing through the pad 10 passes through the low-potential power line GND, FIG. 5 shows a case in which the surge current passes through the high-potential power line VDD (or the case that the surge current enters from the VDD). Is shown. In this case, the low potential power supply line GND is floating.

The path R2 is a path through which the surge current flows from the surge protection circuit 20 to the internal circuit 5 via the low potential power line GND.
This is a path that passes through 0 and reaches the high-potential power supply line VDD. The path R3 is a path that reaches the high-potential power supply line VDD through the N-channel MOS transistor 41 and the P-channel MOS transistor 42. Here, since the breakdown potential of the gate oxide film, which is the input terminal of the inverter 43 in the signal level lowering circuit 40, is high, the breakdown potential of the path R3 passing through the inverter 43 is high.

Here, the breakdown voltage V of the path R2
bd _R2 is as follows: Vbd _R2 = n · Vb + Vb ′ (1) Vb is the source / drain breakdown voltage of the MOS transistor 21 or 22, and n
Vb is a two-stage N-channel MOS transistor 21;
22 is the sum of the breakdown voltages, Vb ′
Is a breakdown voltage of the internal circuit 50.

The breakdown voltage Vb of the path R3
d _R3 is Vbd _R3 = Vb + Vb ″ (2). Vb is the breakdown voltage of the N-channel MOS transistor 41, and Vb ″ is the breakdown voltage of the P-channel MOS transistor.

Which path of the paths R2 and R3 the surge current passes depends on which path has a lower breakdown voltage. That is, of the breakdown voltages of the paths R2 and R3, The surge current passes through the path with the lower breakdown voltage. Then, when using a bulk Si wafer as generally considered,
Breakdown voltage Vbd _R2 route R2, becomes smaller than the breakdown voltage Vbd _R3 route R3, through the route R2 that includes a surge protection circuit 20 is the surge current.

By the way, the surge current is generated by the surge protection circuit 2
Since the surge destruction is prevented by flowing through the path R2 including 0, the problem of the surge destruction does not occur in the conventional semiconductor input circuit SI4.

Next, the reason why the surge current flows through the path R2 including the surge protection circuit 20 in the above conventional example will be described.

FIG. 6A is a diagram showing a current path R2 viewed from a cross section of a device when a bulk substrate is used in the above-mentioned conventional example.

In the N-channel MOS transistor 21 and the N-channel MOS transistor 22 forming the surge protection circuit 20, the N-channel MOS transistor 21
Current directly reaches the source of N-channel MOS transistor 22 from its drain. By this current, the breakdown voltage of the surge protection circuit 20 is reduced as shown in FIG.
As shown in (1), 1.1 Vb (Vb is N channel M
The breakdown voltage of the OS transistor, which is 1.1
Vb is 1.1 times Vb).

On the other hand, the breakdown voltage Vd 'of the internal circuit 50 is the forward voltage portion Vd (= 0.8 V) of the well diode in FIG. Therefore, for a bulk substrate, equation (1) becomes: Vbd _R2 (bulk) = 1.1 Vb + 0.8 (3) Vbd _R2 (bulk) is a breakdown voltage when a surge current passes through the path R2 when a bulk substrate is used.

Further, a P-channel MOS in the path R3
According to experiments, the breakdown voltage of the transistor 42 can be regarded as about 30% of the breakdown voltage Vb of the N-channel MOS transistor. Therefore, for a bulk substrate, equation (2) becomes: Vbd _R3 (bulk) = 1.3 Vb (4) Vbd _R3 (bulk) is a breakdown voltage when a surge current passes through the path R3 when a bulk substrate is used.

Here, Vb is about 8 V in the 0.5 μm MOS process, and Vb is expressed by the formulas (3) and (4).
By substituting b = 8, Vbd _R2 (bulk) = 9.6 V
(1.1 Vb + 0.8), and Vbd _R3 (bulk) =
10.3V (1.3Vb) and therefore the path R
2 breakdown voltage Vbd _R2 (bulk)
3 is smaller than the breakdown voltage Vbd _R3 (bulk) and the surge current flows through the path R2, so that the surge current does not cause breakdown.

[0024]

FIG. 6 (2) is a diagram showing a cross section of a device when an SOI substrate is used in the above conventional example.

A conventional semiconductor input circuit is an SOI (Silocon O
n Insurator) When formed on a substrate, the N-channel MOS transistor 2 forming the surge protection circuit 20 is viewed from the path R2 on the SOI substrate as shown in FIG.
There is no path through which current flows directly from the drain of the N. 1 to the source of the N-channel MOS transistor 22. For this reason, the breakdown voltage of the surge protection circuit 20 is set as shown in FIG.
As shown in (2), the value approaches the value obtained by multiplying the breakdown voltage Vb of one MOS transistor by the number of cascaded stages.
about b.

Further, in the SOI substrate, since the well diode shown in FIG. 6A does not exist, the surge current is reduced by the N-channel MOS transistor and the P-channel MOS transistor of the internal circuit 50 as shown in FIG. High potential power supply line VDD passing between the source and drain with the transistor
To reach.

Therefore, in the SOI substrate, Vbd
_R2 (SOI) is as follows, corresponding to equation (1). Vbd _R2 (SOI) = 2Vb + Vb (5) Vbd _R2 (SOI) is a breakdown voltage when a surge current passes through the path R2 when an SOI substrate is used. Also, here, N
The source-drain breakdown voltage of the channel MOS transistor and the P-channel MOS transistor is assumed to be Vb. That is, when a surge current is input, the gate potential of the internal circuit 50 temporarily becomes high or low, and the gate potential of the N-channel MOS transistor
Since one of the channel MOS transistors is turned on, the source-drain breakdown voltage of the N-channel MOS transistor and the P-channel MOS transistor of the internal circuit 50 is Vb.

On the other hand, the breakdown voltage of the path R3 is S
Since it does not change on the OI substrate, Vbd _R3 (SOI)
Is equal to the expression (4). Vbd _R3 (SOI) = 1.3 Vb (6) Vbd _R3 (SOI) is a breakdown voltage when a surge current passes through the path R3 when an SOI substrate is used.

In the above conventional example, when an SOI substrate is used, by comparing the expressions (5) and (6),
The breakdown voltage of the path R2 (= 3 Vb)
3 is higher than the breakdown voltage (= 1.3 Vb). Therefore, in the above conventional example, S
When an OI substrate is used, the surge current flows through a path R3 shown in FIG. Therefore, N-channel MOS transistor 41 forming signal level lowering circuit 40 and P
Since a large current flows into the channel MOS transistor 42 and both transistors 41 and 42 are minute, the N-channel MOS transistor 41 and the P-channel MOS transistor 42 are broken.

Therefore, the conventional semiconductor input circuit is
When formed on an I substrate, there is a problem that surge destruction cannot be prevented even if the surge protection circuit 20 is added.

According to the present invention, when a semiconductor input circuit is formed on an SOI substrate and a signal having a higher potential than a power supply voltage used for an internal circuit is input to the semiconductor input circuit, a semiconductor having a sufficient surge withstand voltage can be obtained. It is an object to provide an input circuit.

[0032]

SUMMARY OF THE INVENTION The present invention is directed to a signal input device.
It is arranged between the pad and the internal circuit of the semiconductor integrated circuit,
A surge protection circuit and a signal level lowering circuit,
Connect the input terminal of the surge protection circuit to the pad
Output terminal of the signal level reduction circuit
Connected to the output signal line connected to the input terminal of the internal circuit.
In the continuous semiconductor input circuit, the input signal line
And the input terminal of the signal level lowering circuit.
Breakdown voltage increasing circuit and n side
Connected to a high-potential power supply line common to the circuit,
Pn connection connected to a low-potential power line common to the external circuit
And the surge protection circuit has a first diode.
N channel MOS transistor and second N channel MO
And the first N-channel M
The drain of the OS transistor is connected to the input signal line.
The gate is connected to the high potential power line, and the source is
To the drain of the second N-channel MOS transistor
Connected to the second N-channel MOS transistor.
The gate and source are connected to the low-potential power line,
The breakdown voltage increasing circuit comprises at least one column M
OS transistors, and the above-mentioned cascade MOS transistors
All gate terminals of the star
Connected to the power supply line that turns on the S transistor,
The signal level lowering circuit includes a third N-channel MOS transistor.
Transistors, p-channel MOS transistors, and inverters
And the third N-channel MOS transistor.
The drain of the star is connected to the input terminal of the signal level lowering circuit.
And the gate is connected to the high potential power line
Is connected to the drain of the P-channel MOS transistor.
Connected to the input terminal of the inverter, the P-channel
The gate of the MOS transistor is the output terminal of the inverter
The source is connected to the high potential power line
The output terminal of the inverter is connected to the output signal line
Semiconductor input circuit.

[0033]

FIG. 1 is a diagram showing a semiconductor input circuit SI1 according to one embodiment of the present invention.

The semiconductor input circuit SI1 has a surge protection circuit 20, a breakdown voltage increasing circuit 30, a signal level lowering circuit 40, and a diode 60.

In the semiconductor input circuit SI1, the pad 1
0, the input signal line L1 connected to the pad 10 is connected to the input terminal of the surge protection circuit 20,
The output terminal of the breakdown voltage increasing circuit 30 is connected to the input terminal of the signal level lowering circuit 40. The output terminal of the signal level lowering circuit 40 is connected to the input terminal of the internal circuit 50. Power supply V of the internal circuit 50, the signal level lowering circuit 40, and the breakdown voltage increasing circuit 30
DD is common. The diode 60 is a pn junction diode whose n-side is connected to a high-potential power supply line VDD and whose p-side is connected to a low-potential power supply line GND.

The surge protection circuit 20 is an N-channel MOS
Transistor 21 and N-channel MOS transistor 22
It is composed of N channel MOS transistor 2
1 has a drain connected to the pad 10, a gate connected to a high-potential power supply line VDD in the LSI,
Its source is connected to the drain of N-channel MOS transistor 22. The gate and source of the N-channel MOS transistor 22 are connected to a low-potential power supply line GND in the LSI.

The breakdown voltage increasing circuit 30 includes an N-channel MOS transistor 31. The N-channel MOS transistor 31 has a gate connected to the high potential power supply line VDD, a drain connected to the pad 10, The source is connected to the input terminal of the signal level lowering circuit 40.

The signal level lowering circuit 40 has an N-channel M
It comprises an OS transistor 41, a P-channel MOS transistor 42, and an inverter 43. The N-channel MOS transistor 41 has a drain connected to the input terminal of the signal level lowering circuit 40, a gate connected to the high potential power supply line VDD, and a source connected to the high potential power supply line VDD.
The drain of the P-channel MOS transistor 42 and the input terminal of the inverter 43 are connected. The P-channel MOS transistor 42 has a gate connected to the output terminal of the inverter 43 and a source connected to the high-potential power supply line VDD. The output terminal of the inverter 43 is connected to the input terminal of the internal circuit 50.

Next, the operation of the above embodiment will be described.

In the semiconductor input circuit SI1, for example, when the high potential VDD is set to 2.0V, a signal of a high level of 3.3V and a low level of 0V are input during operation. That is, a high level is input at a voltage higher than the high potential VDD.

The surge protection circuit 20 is constituted by two stages of N-channel MOS transistors 21 and 22 connected in cascade.
No breakdown occurs between the source and the drain of each of the 22. Also, the breakdown voltage increasing circuit 30
And the signal level lowering circuit 40 lowers the high level 3.3 V of the input signal to 2.0 V, which is the voltage value of the high potential power supply line VDD, and outputs it. In this manner, the high level 3.3 V is not applied to the gate of the MOS transistor of the internal circuit 50, so that the reliability of the gate oxide film due to the high level 3.3 V can be prevented. .

When the 3.3 V high level input at the drain terminal of the N-channel MOS transistor 31 is applied to the source of the N-channel MOS transistor 31 in the breakdown voltage increasing circuit 30, VDD-Vth
n. Vthn is an N-channel MO.
This is the threshold voltage of the S transistor 31.

The input signal of the semiconductor input circuit SI1 is supplied to the N-channel MOS in the signal level lowering circuit 40.
Although passing through the transistor 41, since the N-channel MOS transistor 41 is on, its drain and source have substantially the same potential, and the source terminal of the N-channel MOS transistor 41 outputs a high level potential of VDD-Vthn. I do. Then, the P-channel MOS transistor 42 is used to prevent a leakage current of the inverter 43,
The potential of the input terminal of the inverter 43 (the source terminal of the N-channel MOS transistor 41) is raised from VDD-Vthn to VDD.

Next, the operation when a surge current enters the above embodiment will be described.

FIG. 2 is a diagram for explaining the operation when a surge current enters the semiconductor input circuit SI1.

The substrate is an SOI substrate. Although there is a path through which the surge current from the pad 10 escapes to GND, the case where the surge current enters the high-potential power supply line VDD (or, in other words, enters from VDD) will be described. At this time,
The low potential power line GND is floating.

The path through which the surge current flows to the high-potential power line VDD includes a path R1 and a path R2 shown in FIG.
The path R1 is a path that reaches the high-potential power supply line VDD through the N-channel MOS transistor 31, the N-channel MOS transistor 41, and the P-channel MOS transistor 42, and is the input potential (gate) of the inverter 43 of the signal level lowering circuit 40. The break potential of the oxide film) is high. Route R
Reference numeral 2 denotes a path from the surge protection circuit 20 to the high-potential power line VDD through the diode 60 via the low-potential power line GND.

When a surge current flows through the path R2 including the surge protection circuit 20, surge destruction is prevented.
Which path the surge current passes through depends on which path has a lower breakdown voltage, that is, the surge current passes through a path having a lower breakdown voltage.

When the SOI substrate is used, the breakdown voltage when the surge current passes through the path R1 is Vb
Assuming that d _R1 (SOI), Vbd _R1 (SOI) = 2Vb + Vb ″ (7) where Vb is the source / drain breakdown voltage of the MOS transistor, and 2Vb is the N-channel MOS transistor 31 This is the sum of the breakdown voltages of the N-channel MOS transistor 41 and V
b ″ is a breakdown voltage of the P-channel MOS transistor 42.

If the breakdown voltage when the surge current passes through the path R2 is Vbd _R2 (SOI) when an SOI substrate is used, Vbd _R2 (SOI) = 2Vb + 0.8 (8) . Here, 2Vb is a breakdown voltage in the two-stage N-channel MOS transistors 21 and 22, and 0.8 (V) is a forward voltage Vd of the diode 60.
It is.

The breakdown voltage Vb ″ of the P-channel MOS transistor 42 is approximately 30% of the breakdown voltage Vb as an experimental value.
Vb "= 1.3 Vb. Therefore, the breakdown voltage Vbd _R1 (SOI) = 2 Vb + Vb" of the path R1.
= 2Vb + 0.3Vb = 2.3Vb. On the other hand, the breakdown voltage Vbd _R2 (SOI) of the path R2 = 2Vb
+0.8. Therefore, if the breakdown voltage Vb of the MOS transistor is higher than about 3V, the breakdown voltage of the path R2 becomes lower than the breakdown voltage of the path R1. Therefore, since the surge current does not pass through the breakdown voltage increasing circuit 30 and the signal level lowering circuit 40 through the path R2, the breakdown voltage increasing circuit 30 and the signal level lowering circuit 4
At 0, surge destruction can be prevented.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 3A is a circuit diagram showing a semiconductor input circuit SI2 according to a second embodiment of the present invention.

The semiconductor input circuit SI2 is basically the same as the semiconductor input circuit SI1, except that
N-channel MO instead of diode 60 in I1
An S transistor 70 is provided.

The N-channel MOS transistor 70 has a source connected to the high-potential power supply line VDD, a drain connected to the low-potential power supply line GND, and a gate connected to the drain. Then, when a voltage is applied, the N-channel MOS transistor 70 is turned off. Therefore, the N-channel MOS transistor 70 is used in the same manner as the diode 60.

FIG. 3B is a circuit diagram showing a semiconductor input circuit SI3 according to a third embodiment of the present invention.

The semiconductor input circuit SI3 is basically the same as the semiconductor input circuit SI1, except that
P-channel MO instead of diode 60 in I1
An S transistor 71 is provided.

The P-channel MOS transistor 71 has a source connected to the high-potential power supply line VDD, a drain connected to the low-potential power supply line GND, and a gate connected to the source. And when applying voltage,
The P-channel MOS transistor 71 is turned off, so that the P-channel MOS transistor 71 is used in the same manner as the diode 60.

That is, the semiconductor input circuits SI2 and SI3
Comprises a surge protection circuit and a signal level lowering circuit,
In a semiconductor input circuit in which an input terminal of a surge protection circuit is connected to an input signal line and an output terminal of a signal level lowering circuit is connected to an output signal line, the input terminal is connected between the input signal line and the input terminal of the signal level lowering circuit. And a MOS transistor having a source connected to a high-potential power supply line and a drain connected to a low-potential power supply line, and a potential for turning off the MOS transistor when a voltage is applied. This is an example of a semiconductor input circuit in which the gate of a MOS transistor is connected to a high-potential power line or a low-potential power line having

In each of the above embodiments, one N-channel MOS transistor 31 is used as the breakdown voltage increasing circuit 30, but a plurality of N-channel MOS transistors are arranged in tandem as the breakdown voltage increasing circuit 30. In this case, the value of the breakdown voltage in the path 1 becomes large, and the difference between the value of the breakdown voltage in the path R1 and the value of the breakdown voltage in the path R2 may be used. The value of the breakdown voltage in path R2 can be
1 is even lower than the value of the breakdown voltage.

That is, the breakdown voltage increasing circuit 30
May be composed of two or more cascaded MOS transistors, that is, the breakdown voltage increasing circuit 30 is composed of at least one cascaded MOS transistor. Sometimes they are connected to a power supply line that turns on these cascaded MOS transistors.

In the description of the above embodiment, the M
Although the gate channel length of the OS transistor is not particularly described, the breakdown voltage can be increased by increasing the gate channel length, and this may be used to make a difference in the breakdown voltage value. . That is, the gate channel length of at least one of the N-channel MOS transistor 31, the N-channel MOS transistor 41, and the P-channel MOS transistor 42 is set to be equal to the N-channel MOS transistor 2
By designing to be longer than 1, 22, the value of the breakdown voltage in the path R2 can be made relatively lower than the value of the breakdown voltage in the path R1.

In each of the above embodiments, if the diode 60 is formed of a well diode, the diode 60 can be formed without forming a pattern on the bulk substrate. Note that a lateral diode may be provided instead of the well diode.

[0063]

According to the present invention, when a semiconductor input circuit is formed on an SOI substrate and a signal having a potential higher than a power supply voltage used for an internal circuit is input to the semiconductor input circuit, a sufficient surge withstand voltage is obtained. It has the effect of being able to do so.

[Brief description of the drawings]

FIG. 1 shows a semiconductor input circuit SI1 according to an embodiment of the present invention.
FIG.

FIG. 2 is an operation explanatory diagram when a surge current enters a semiconductor input circuit SI1.

FIG. 3 shows a semiconductor input circuit SI according to another embodiment of the present invention.
FIG. 2 is a diagram showing SI3.

FIG. 4 is a diagram showing a configuration of a conventional semiconductor input circuit SI4.

FIG. 5 shows a case where a surge current flows into a conventional semiconductor input circuit SI4 and the surge current is a high potential power supply line V;
It is a figure showing routes R2 and R3 leading to DD.

FIG. 6A shows a current path R viewed from a cross section of a device when a bulk substrate is used in the conventional example.
FIG. 6B is a diagram showing a cross section of the device in the case where an SOI substrate is used in the conventional example.

FIG. 7A is a diagram illustrating breakdown characteristics of an N-channel MOS transistor and a surge protection circuit when a bulk substrate is used, and FIG.
FIG. 4 is a diagram showing breakdown characteristics of an N-channel MOS transistor and a surge protection circuit when an SOI substrate is used.

[Explanation of symbols]

 SI1, SI2, SI3: semiconductor input circuit, VDD: high-potential power supply line, GND: low-potential power supply line, 10: pad, 20: surge protection circuit, 30: breakdown amplifier circuit, 40: signal level lowering circuit, 50: internal circuit, 60: diode, 70: N-channel MOS transistor, 71: P-channel MOS transistor.

────────────────────────────────────────────────── ─── Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI H02H 3/24 H01L 27/08 102F 7/20 (56) References JP-A-4-230072 (JP, A) JP-A-6 JP-A-112422 (JP, A) JP-A-6-125048 (JP, A) JP-A-3-27566 (JP, A) JP-A-62-145918 (JP, A) (58) Fields investigated (Int. . ^7, DB name) H01L 29/78 H01L 21/8234 H01L 27/06 H01L 27/088 H01L 29/786 H02H 3/24 H02H 7/20

Claims (4)

(57) [Claims] A signal input pad and a semiconductor integrated circuit;
Disposed between the internal circuit, comprising a surge protection circuit and the signal level reduction circuit, an input terminal of the surge protection circuitry is connected to an input signal line connected to the pad, the output of the signal level drop circuit Terminal is the input terminal of the above internal circuit
The semiconductor input circuit connected to an output signal line connected to the child, the breakdown voltage increases circuit connected between the input terminal of the input signal line and the signal level reduction circuit and; n side is the internal circuit and is connected to the power supply line of the common high-potential, a pn junction diode that is connected to the power line of the common low potential and p side is the internal circuit; have a, the surge protection circuit comprises a first N-channel MOS transformer
Composed of a transistor and a second N-channel MOS transistor
And the drain of the first N-channel MOS transistor
Is connected to the input signal line, and the gate is connected to the high potential
And the source is the second N-channel M
Connected to the drain of the OS transistor;
The gate and source of the channel MOS transistor
Connected to a potential power supply line, and the breakdown voltage increasing circuit includes at least one stage.
The cascaded MOS transistors are composed of cascaded MOS transistors.
All gate terminals of the transistor will be
Connected to the power supply line that turns on the column MOS transistor.
Is, the signal level drop circuit, the third N-channel MOS DOO
Transistors, p-channel MOS transistors, and
And the third N-channel MOS transistor.
The drain of the transistor is the input terminal of the signal level reduction circuit.
And the gate is connected to the high potential power line
The source is the drain of the P-channel MOS transistor.
Connected to the input terminal of the inverter
The gate of the channel MOS transistor is
The source is connected to the high-potential power line
The output terminal of the inverter is connected to the output signal line.
A semiconductor input circuit characterized by being connected . 2. The semiconductor input circuit according to claim 1, wherein said pn junction diode is a well diode. 3. The MOS transistor according to claim 1, wherein said pn junction diode is replaced by a MOS transistor having a source connected to said high potential power supply line and a drain connected to said low potential power supply line .
The gate of the transistor, at the time of voltage application, the semiconductor input circuit, characterized in that it is connected to the power supply line of the power supply line or a low potential of high potential having a side potential to turn off the MOS transistor. 4. A any one of claims 1 to 3, at least one gate channel length of the MOS transistors constituting the breakdown voltage increases circuit, the gate of the MOS transistor constituting the surge protection circuit A semiconductor input circuit having a length longer than a channel length.