JPH0992829A - Semiconductor input circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a sufficiently high surge breakdown voltage when a potential signal higher than a power source voltage used for an internal circuit is inputted to a semiconductor input circuit by forming the semiconductor input circuit on an SOI substrate. SOLUTION: Between a pad 10 and the input terminal of a signal level lowering circuit 40, at least one N-channel MOS transistor 31 is interposed in which the gate is connected to a power source line VDD of high potential, the drain is connected to the pad 10, and the source is connected to the input terminal of the signal level lowering circuit 40, and at the same time a diode 60 on an SOI substrate is formed by a circuit pattern between the power source line VDD of high potential and the power source line GND of low potential.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor input circuit used in a semiconductor integrated circuit, and more particularly, to inputting a signal having a potential higher than a power supply voltage used for an internal circuit to an SOI (S
ilocon On Insurator) A semiconductor input circuit suitable for an integrated circuit formed on a substrate.

[0002]

2. Description of the Related Art FIG. 4 shows a structure of a conventional semiconductor input circuit SI4.

A conventional semiconductor input circuit SI4 is composed of a surge protection circuit 20 and a signal level lowering circuit 40.

The semiconductor input circuit SI4 inputs a signal from the pad 10, and an input signal line L1 is connected between the pad 10 and the input terminal of the surge protection circuit 20. This input signal line L1 is a signal level lowering circuit. It is connected to 40 input terminals. The output terminal of the signal level lowering circuit 40 is connected to the input terminal of the internal circuit 50 via the output signal line L2, and the power supply line VDD of the signal level lowering circuit 40 and the power supply line VDD of the internal circuit 50 are common.

The surge protection circuit 20 is an N channel MOS.
Transistor 21 and N-channel MOS transistor 22
It is composed of N-channel MOS transistor 2
1, the drain is connected to the pad 10, the gate is connected to the high potential power line VDD in the LSI,
Its source is connected to the drain of the N-channel MOS transistor 22. The gate and source of the N-channel MOS transistor 22 are connected to the low potential power supply line GND in the LSI.

The signal level lowering circuit 40 includes an N channel M
It is composed of an OS transistor 41, a P-channel MOS transistor 42, and an inverter 43. The N-channel MOS transistor 41 has its drain connected to the input terminal of the signal level lowering circuit 40, its gate connected to the high-potential power supply line VDD, and its source connected to
It is connected to the drain of the P-channel MOS transistor 42 and the input terminal of the inverter 43. P channel M
The gate of the OS transistor 42 has the inverter 4
3 is connected to the output terminal and the source thereof is connected to the high potential power supply line VDD. The output terminal of the inverter 43 is connected to the input terminal of the internal circuit 50.

In the conventional semiconductor input circuit SI4, if the voltage of the high-potential power supply line VDD is set to 2.0 V, for example, during operation, high level 3.3 V and low level 0
The V signal is input, that is, the high-level voltage is input at a value higher than the voltage of the high-potential power supply line VDD.

Here, the surge protection circuit 20 is composed of two stages of N-channel MOS transistors 21 and 22 which are connected in cascade. A breakdown is caused between the source and drain of each of the N-channel MOS transistors 21 and 22. Designed not to wake up. This point is shown in JP-A-7-160033.

Further, the signal level lowering circuit 40 lowers the high level 3.3V of the input signal to the VDD voltage value 2.0V and outputs it. This point is related to JP-A-62-14.
No. 5918. MOS in internal circuit 50
The high level 3.3 of the input signal is input to the gate of the transistor.
When V is applied, the reliability of the gate oxide film decreases, but the input signal level is decreased in order to prevent this decrease in reliability. That is, in the signal level lowering circuit 40,
The 3.3V high-level input input to the drain terminal of the N-channel MOS transistor 41 is
VDD-Vthn (Vthn is the threshold voltage of the N-channel MOS transistor).

Then, the P-channel MOS transistor 4
In order to prevent the leak current of the inverter 43, the potential of the input terminal (source terminal of the N-channel MOS transistor 41) of the inverter 43 is changed from VDD-Vthn to V2.
It has been raised to DD. That is, the potential of the input terminal of the inverter 43 is not raised to VDD, and VDD-Vthn
If left as it is, both the N-channel MOS transistor and the P-channel MOS transistor forming the inverter 43 are turned on and the leak current flows from the terminal VDD to the GND, but the potential of the input terminal of the inverter 43 is raised to VDD. For example, neither the N-channel MOS transistor nor the P-channel MOS transistor forming the inverter 43 is turned on, and no leak current flows.

FIG. 5 is a diagram showing paths R2 and R3 through which the surge current flows to the power supply line VDD having a high potential when the surge current flows into the conventional semiconductor input circuit SI4.

Although there is a route through which the surge current passing through the pad 10 passes through the low-potential power supply line GND, in FIG. 5, the surge current passes through the high-potential power supply line VDD (or, conversely, enters through VDD). It is shown. In this case, the low-potential power supply line GND is floating.

In the path R2, the surge current flows from the surge protection circuit 20 to the internal circuit 5 via the low-potential power supply line GND.
It is a path that passes through 0 and reaches the high-potential power supply line VDD. The route R3 is a route through the N-channel MOS transistor 41 and the P-channel MOS transistor 42 to reach the high potential power supply line VDD. Here, since the breakdown potential of the gate oxide film which is the input terminal of the inverter 43 in the signal level lowering circuit 40 is high, the breakdown potential of the path R3 passing through the inverter 43 is high.

Here, the breakdown voltage V of the path R2
bd _R2 is Vbd _R2 = n · Vb + Vb ′ ... (1). Note that Vb is a source / drain breakdown voltage of the MOS transistor 21 or 22, and n
Vb is a two-stage N-channel MOS transistor 21,
22 is the total breakdown voltage at Vb ′.
Is a breakdown voltage of the internal circuit 50.

Further, the breakdown voltage Vb of the path R3
d _R3 is Vbd _R3 = Vb + Vb ″ ... (2) where Vb is the breakdown voltage of the N-channel MOS transistor 41, and Vb ″ is the breakdown voltage of the P-channel MOS transistor 42.

Which of the paths R2 and R3 the surge current passes through depends on which of the paths has a lower breakdown voltage, that is, among the breakdown voltages of the paths R2 and R3, the one in the path. The surge current passes through the path with the lower breakdown voltage. And when using a bulk Si wafer as is usually considered,
Breakdown voltage Vbd _R2 route R2, becomes smaller than the breakdown voltage Vbd _R3 route R3, through the route R2 that includes a surge protection circuit 20 is the surge current.

By the way, the surge protection circuit 2
The surge breakdown is prevented by flowing through the path R2 including 0, so that the problem of surge breakdown does not occur in the conventional semiconductor input circuit SI4.

Next, the reason why the surge current flows through the path R2 including the surge protection circuit 20 in the above conventional example will be described.

FIG. 6 (1) is a diagram showing a current path R2 seen in a cross section of the device when a bulk substrate is used in the above conventional example.

In the N channel MOS transistor 21 and the N channel MOS transistor 22 forming the surge protection circuit 20, the N channel MOS transistor 21 is included.
There is a current that directly reaches the source of the N-channel MOS transistor 22 from the drain of the. This current causes the breakdown voltage of the surge protection circuit 20 to rise to the level shown in FIG.
As shown in (1), 1.1 Vb (Vb is the N channel M
The breakdown voltage of the OS transistor, which is 1.1
Vb is about 1.1 times Vb).

On the other hand, the breakdown voltage Vd 'of the internal circuit 50 becomes the forward voltage portion Vd (= 0.8V) of the well diode of FIG. 6 (1). Therefore, in the bulk substrate, the equation (1) is as follows. Vbd _R2 (bulk) = 1.1 Vb + 0.8 (3) Note that Vbd _R2 (bulk) is a breakdown voltage when the surge current passes through the route R2 when the bulk substrate is used.

Further, a P channel MOS in the route R3
According to experiments, the breakdown voltage of the transistor 42 can be regarded as about 30% of the breakdown voltage Vb of the N-channel MOS transistor. Therefore, in the bulk substrate, the equation (2) is as follows. Vbd _R3 (bulk) = 1.3 Vb (4) Note that Vbd _R3 (bulk) is a breakdown voltage when the surge current passes through the route R3 when a bulk substrate is used.

Here, Vb is about 8 V in the 0.5 μm MOS process, and Vb is given by the equations (3) and (4).
Substituting b = 8, Vbd _R2 (bulk) = 9.6V
(1.1 Vb + 0.8) and Vbd _R3 (bulk) =
10.3V (1.3Vb), thus the path R
The breakdown voltage Vbd _R2 (bulk) of 2 is the path R
The breakdown voltage is smaller than the breakdown voltage Vbd _R3 (bulk) of 3, and the surge current flows through the path R2, so that the breakdown due to the surge current does not occur.

[0024]

FIG. 6 (2) is a view showing a cross section of a device in the case of using an SOI substrate in the above conventional example.

A conventional semiconductor input circuit is an SOI (Silocon O
n Insurator) substrate, the N-channel MOS transistor 2 forming the surge protection circuit 20 is viewed from the path R2 on the SOI substrate as shown in FIG. 6B.
There is no path for the current to directly flow from the drain of 1 to the source of the N-channel MOS transistor 22. For this reason, the breakdown voltage of the surge protection circuit 20 is as shown in FIG.
As shown in (2), the breakdown voltage Vb of one MOS transistor approaches the value obtained by multiplying the breakdown voltage Vb by 2
It is about b.

Further, in the SOI substrate, since the well diode shown in FIG. 6 (1) does not exist, the surge current is generated by the N-channel MOS transistor and the P-channel MOS transistor of the internal circuit 50 as shown in FIG. 6 (2). High-potential power line VDD that passes between the source and drain of the transistor
Reach.

Therefore, in the SOI substrate, Vbd
_R2 (SOI) is as follows corresponding to the equation (1). Vbd _R2 (SOI) = 2Vb + Vb (5) Note that Vbd _R2 (SOI) is a breakdown voltage when the surge current passes through the route R2 when the SOI substrate is used. Further, here, N of the internal circuit 50 is
It is assumed that the source-drain breakdown voltage of the channel MOS transistor and the P-channel MOS transistor is Vb. That is, when a surge current is input, the gate potential of the internal circuit 50 temporarily becomes high or low, and the N-channel MOS transistor or P
Since one of the channel MOS transistors is turned on, the source-drain breakdown voltage of the N-channel MOS transistor and the P-channel MOS transistor of the internal circuit 50 is Vb.

On the other hand, the breakdown voltage of the path R3 is S
Vbd _R3 (SOI) as it does not change on the OI substrate
Is equal to equation (4). Vbd _R3 (SOI) = 1.3 Vb (6) Vbd _R3 (SOI) is a breakdown voltage when the surge current passes through the route R3 when the SOI substrate is used.

In the above-mentioned conventional example, when the SOI substrate is used, by comparing the equations (5) and (6),
The breakdown voltage (= 3Vb) of the route R2 is
It can be seen that the breakdown voltage becomes higher than the breakdown voltage of 3 (= 1.3 Vb). Therefore, in the above conventional example, S
When using the OI substrate, the surge current flows through the path R3 shown in FIG. Therefore, the N-channel MOS transistors 41 and P that constitute the signal level lowering circuit 40
Since a large current flows into the channel MOS transistor 42 and both transistors 41 and 42 are minute, the N channel MOS transistor 41 and the P channel MOS transistor 42 are destroyed.

Therefore, the conventional semiconductor input circuit is
When it is formed on the I substrate, there is a problem that even if the surge protection circuit 20 is added, it is not possible to prevent the surge breakdown.

According to the present invention, when a semiconductor input circuit is formed on an SOI substrate and a signal having a potential higher than the power supply voltage used for the internal circuit is input to the semiconductor input circuit, the semiconductor can have a sufficient surge withstand voltage. It is intended to provide an input circuit.

[0032]

According to the present invention, between the pad 10 and the input terminal of the signal level lowering circuit 40, the gate is connected to the high potential power source line VDD and the drain is the pad 10.
And at least one N-channel MOS transistor 31 whose source is connected to the input terminal of the signal level lowering circuit 40 are inserted, and the diode 60 realized on the SOI substrate is connected to the high-potential power supply line VDD and the low potential line. It is formed as a circuit pattern between the power supply line GND and the potential.

[0033]

DESCRIPTION OF THE PREFERRED EMBODIMENTS FIG. 1 is a diagram showing a semiconductor input circuit SI1 which is an embodiment of the present invention.

The semiconductor input circuit SI1 has a surge protection circuit 20, a breakdown voltage increasing circuit 30, a signal level decreasing circuit 40, and a diode 60.

In the semiconductor input circuit SI1, the pad 1
A signal is input from 0, and the input signal line L1 connected to the pad 10 is connected to the input terminal of the surge protection circuit 20,
It is connected to the input terminal of the breakdown voltage increasing circuit 30, and the output terminal of the breakdown voltage increasing circuit 30 is connected to the input terminal of the signal level lowering circuit 40. The output terminal of the signal level lowering circuit 40 is connected to the input terminal of the internal circuit 50. Power supply V for internal circuit 50, signal level lowering circuit 40, breakdown voltage increasing circuit 30
DD is common. The diode 60 is a pn junction diode whose n side is connected to the high potential power supply line VDD line and whose p side is connected to the low potential power supply line GND line.

The surge protection circuit 20 is an N channel MOS.
Transistor 21 and N-channel MOS transistor 22
It is composed of N-channel MOS transistor 2
1, the drain is connected to the pad 10, the gate is connected to the high potential power line VDD in the LSI,
Its source is connected to the drain of the N-channel MOS transistor 22. The gate and source of the N-channel MOS transistor 22 are connected to the low potential power supply line GND in the LSI.

The breakdown voltage increasing circuit 30 is composed of an N-channel MOS transistor 31. The N-channel MOS transistor 31 has its gate connected to the high potential power supply line VDD and its drain connected to the pad 10. The source is connected to the input terminal of the signal level lowering circuit 40.

The signal level lowering circuit 40 includes an N channel M
It is composed of an OS transistor 41, a P-channel MOS transistor 42, and an inverter 43. The N-channel MOS transistor 41 has its drain connected to the input terminal of the signal level lowering circuit 40, its gate connected to the high-potential power supply line VDD, and its source connected to
It is connected to the drain of the P-channel MOS transistor 42 and the input terminal of the inverter 43. Further, the P-channel MOS transistor 42 has its gate connected to the output terminal of the inverter 43, and its source connected to the high-potential power supply line VDD. The output terminal of the inverter 43 is connected to the input terminal of the internal circuit 50.

Next, the operation of the above embodiment will be described.

In the semiconductor input circuit SI1, when the high potential VDD is set to 2.0 V, for example, a high level signal of 3.3 V and a low level signal of 0 V are input during operation. That is, the high level is input at a voltage higher than the high potential VDD.

The surge protection circuit 20 is composed of two stages of N-channel MOS transistors 21 and 22 connected in cascade.
No breakdown occurs between the source and drain of each 22. Also, the breakdown voltage increasing circuit 30
And the signal level lowering circuit 40 lowers the high level 3.3V of the input signal to 2.0V which is the voltage value of the high potential power supply line VDD and outputs it. In this way, the high level 3.3V is not applied to the gate of the MOS transistor of the internal circuit 50, and therefore the reliability of the gate oxide film can be prevented from lowering due to the high level 3.3V being applied. .

By the way, the 3.3V high level input at the drain terminal of the N-channel MOS transistor 31 is VDD-Vth at the source of the N-channel MOS transistor 31 in the breakdown voltage increasing circuit 30.
It is lowered to n. Note that Vthn is an N-channel MO
It is the threshold voltage of the S transistor 31.

The input signal of the semiconductor input circuit SI1 is an N channel MOS in the signal level lowering circuit 40.
Although it passes through the transistor 41, since the N-channel MOS transistor 41 is on, its drain and source have almost the same potential, and the source terminal of the N-channel MOS transistor 41 outputs a high level potential of VDD-Vthn. To do. Then, the P-channel MOS transistor 42 is provided in order to prevent the leakage current of the inverter 43.
The potential of the input terminal of the inverter 43 (the source terminal of the N-channel MOS transistor 41) is raised from VDD-Vthn to VDD.

Next, the operation when a surge current enters the above embodiment will be described.

FIG. 2 is a diagram for explaining the operation when a surge current enters the semiconductor input circuit SI1.

The substrate is an SOI substrate. Although the surge current that has entered from the pad 10 also has a path through which it escapes to GND, the case where it escapes to the high-potential power supply line VDD (or conversely, it enters from VDD) is shown here. At this time,
The low-potential power supply line GND is floating.

There are a route R1 and a route R2 shown in FIG. 2 as the routes through which the surge current passes to the high potential power supply line VDD.
The route R1 is a route to the high-potential power supply line VDD through the N-channel MOS transistor 31, the N-channel MOS transistor 41, and the P-channel MOS transistor 42, and the input potential (gate of the inverter 43 of the signal level lowering circuit 40 (gate Oxide film break potential) is high. Route R
Reference numeral 2 is a path from the surge protection circuit 20 to the high potential power supply line VDD via the diode 60 via the low potential power supply line GND.

When a surge current flows through the path R2 including the surge protection circuit 20, surge breakdown is prevented,
Which path the surge current passes through depends on which path has the lower breakdown voltage, that is, the surge current passes through the path having the lower breakdown voltage.

When the SOI substrate is used, the breakdown voltage when the surge current passes through the route R1 is Vb.
If d _R1 (SOI), then Vbd _R1 (SOI) = 2Vb + Vb ″ (7) where Vb is the source-drain breakdown voltage of the MOS transistor and 2Vb is the N-channel MOS transistor 31. The sum of the breakdown voltage of the N-channel MOS transistor 41 and V
b ″ is a breakdown voltage of the P-channel MOS transistor 42.

When the SOI substrate is used and the breakdown voltage when the surge current passes through the path R2 is Vbd _R2 (SOI), Vbd _R2 (SOI) = 2Vb + 0.8 (8) . Here, 2Vb is the breakdown voltage in the two-stage N-channel MOS transistors 21 and 22, and 0.8 (V) is the forward voltage Vd of the diode 60.
It is.

The experimental value of the breakdown voltage Vb ″ of the P-channel MOS transistor 42 is about 30% of the breakdown voltage Vb.
Vb ″ = 1.3Vb. Therefore, the breakdown voltage Vbd _R1 (SOI) = 2Vb + Vb ″ of the path R1.
= 2Vb + 0.3Vb = 2.3Vb. On the other hand, the breakdown voltage Vbd _R2 (SOI) = 2Vb of the path R2
It is +0.8. Therefore, if the breakdown voltage Vb of the MOS transistor is higher than about 3V, the breakdown voltage of the path R2 becomes lower than the breakdown voltage of the path R1. Therefore, since the surge current passes through the path R2 and does not pass through the breakdown voltage increasing circuit 30 and the signal level lowering circuit 40, the breakdown voltage increasing circuit 30 and the signal level lowering circuit 4
When 0, surge damage can be prevented.

FIG. 3 is a circuit diagram showing another embodiment of the present invention, and FIG. 3 (1) is a circuit diagram showing a semiconductor input circuit SI2 which is a second embodiment of the present invention.

The semiconductor input circuit SI2 is basically the same as the semiconductor input circuit SI1, but the semiconductor input circuit S1
N-channel MO instead of diode 60 in I1
The S transistor 70 is provided.

The N-channel MOS transistor 70 has its source connected to the high-potential power supply line VDD, its drain connected to the low-potential power supply line GND, and its gate connected to the drain. Then, when the voltage is applied, the N-channel MOS transistor 70 is turned off. Therefore, the N-channel MOS transistor 70 is used like the diode 60.

FIG. 3B is a circuit diagram showing a semiconductor input circuit SI3 according to the third embodiment of the present invention.

The semiconductor input circuit SI3 is basically the same as the semiconductor input circuit SI1, but the semiconductor input circuit S1
P-channel MO instead of diode 60 in I1
The S transistor 71 is provided.

The P-channel MOS transistor 71 has its source connected to the high potential power supply line VDD, its drain connected to the low potential power supply line GND, and its gate connected to the source. And when voltage is applied,
The P-channel MOS transistor 71 is turned off, so the P-channel MOS transistor 71 is used in the same manner as the diode 60.

That is, the semiconductor input circuits SI2 and SI3
Comprises a surge protection circuit and a signal level lowering circuit,
In a semiconductor input circuit in which the input terminal of the surge protection circuit is connected to the input signal line and the output terminal of the signal level lowering circuit is connected to the output signal line, it is connected between the input signal line and the input terminal of the signal level lowering circuit. And a MOS transistor having a source connected to a high-potential power supply line and a drain connected to a low-potential power supply line, and a potential on the side for turning off the MOS transistor when a voltage is applied. Is an example of a semiconductor input circuit in which the gate of a MOS transistor is connected to a high-potential power line or a low-potential power line.

In each of the above embodiments, one N-channel MOS transistor 31 is used as the breakdown voltage increasing circuit 30, but as the breakdown voltage increasing circuit 30, a plurality of N-channel MOS transistors are arranged vertically. The above circuit may be used, and by doing so, the value of the breakdown voltage in the path 1 becomes large, and the difference between the value of the breakdown voltage of the path R1 and the value of the breakdown voltage of the path R2 is reduced. Can be widened, and the value of the breakdown voltage on the route R2 is
It is even lower than the value of the breakdown voltage at 1.

That is, the breakdown voltage increasing circuit 30
May be composed of two or more stages of cascaded MOS transistors, that is, the breakdown voltage increasing circuit 30 is composed of at least one cascaded MOS transistor, and all gate terminals of these cascaded MOS transistors are applied with a voltage. It is sometimes connected to the power supply line on the side where these column MOS transistors are turned on.

In the description of the above embodiment, the M used
Although no particular reference is made to the gate channel length of the OS transistor, the breakdown voltage can be increased by increasing the gate channel length, and by utilizing this, the breakdown voltage values may be differentiated. . That is, the gate channel length of at least one of the N-channel MOS transistor 31, the N-channel MOS transistor 41, and the P-channel MOS transistor 42 is set to the N-channel MOS transistor 2
By designing the voltage longer than 1 and 22, the value of the breakdown voltage in the route R2 can be made relatively lower than the value of the breakdown voltage in the route R1.

In each of the above embodiments, if the diode 60 is a well diode, the diode 60 can be built without forming a pattern on the bulk substrate. A lateral diode may be provided instead of the well diode.

[0063]

According to the present invention, when a semiconductor input circuit is formed on an SOI substrate and a signal having a potential higher than the power supply voltage used for the internal circuit is input to the semiconductor input circuit, it has a sufficient surge withstand voltage. There is an effect that can be.

[Brief description of drawings]

FIG. 1 is a semiconductor input circuit SI1 which is an embodiment of the present invention.
FIG.

FIG. 2 is an operation explanatory diagram when a surge current enters a semiconductor input circuit SI1.

FIG. 3 is a semiconductor input circuit SI which is another embodiment of the present invention.
2 is a diagram showing SI3. FIG.

FIG. 4 is a diagram showing a configuration of a conventional semiconductor input circuit SI4.

FIG. 5 is a power supply line V having a high surge current when a surge current flows into a conventional semiconductor input circuit SI4.
It is a figure which shows the paths R2 and R3 which go out to DD.

FIG. 6 (1) is a current path R seen in a cross section of the device in the case of using a bulk substrate in the above conventional example.
FIG. 6B is a diagram showing a cross section of the device in the case where an SOI substrate is used in the above conventional example.

FIG. 7 (1) is a diagram showing breakdown characteristics of an N-channel MOS transistor and a surge protection circuit when a bulk substrate is used, and FIG.
It is a figure which shows the breakdown characteristic of an N-channel MOS transistor and a surge protection circuit when an SOI substrate is used.

[Explanation of symbols]

 SI1, SI2, SI3 ... Semiconductor input circuit, VDD ... High potential power line, GND ... Low potential power line, 10 ... Pad, 20 ... Surge protection circuit, 30 ... Breakdown amplifier circuit, 40 ... Signal level lowering circuit, 50 ... Internal circuit, 60 ... Diode, 70 ... N channel MOS transistor, 71 ... P channel MOS transistor.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI Technical display location H02H 3/24 H01L 23/56 A 7/20 29/78 623Z

Claims (5)

[Claims] 1. A surge protection circuit and a signal level reduction circuit are provided, wherein an input terminal of the surge protection circuit is connected to an input signal line, and an output terminal of the signal level reduction circuit is connected to an output signal line. A breakdown voltage increasing circuit connected between the input signal line and an input terminal of the signal level lowering circuit in a semiconductor input circuit;
A semiconductor input circuit comprising: a pn junction diode whose n-side is connected to a high-potential power line and whose p-side is connected to a low-potential power line. 2. The semiconductor input circuit according to claim 1, wherein the pn junction diode is a well diode. 3. A surge protection circuit and a signal level reduction circuit are provided, wherein an input terminal of the surge protection circuit is connected to an input signal line and an output terminal of the signal level reduction circuit is connected to an output signal line. A breakdown voltage increasing circuit connected between the input signal line and an input terminal of the signal level lowering circuit in a semiconductor input circuit;
A MOS transistor having a source connected to a high-potential power line and a drain connected to a low-potential power line; and a high-potential power source having a potential on the side for turning off the MOS transistor when a voltage is applied. A semiconductor input circuit, wherein the gate of the MOS transistor is connected to a power line or a low-potential power line. 4. The breakdown voltage increasing circuit according to claim 1, wherein the breakdown voltage increasing circuit is composed of at least one column MOS transistor, and all the gate terminals of the column MOS transistor are the column MOS when a voltage is applied. A semiconductor input circuit, characterized in that it is connected to a power supply line on the side where a transistor is turned on. 5. The gate channel length of at least one of the MOS transistors forming the breakdown voltage increasing circuit according to claim 1, wherein the gate channel length of the MOS transistor forming the breakdown voltage increasing circuit is the gate of the MOS transistor forming the surge protection circuit. A semiconductor input circuit having a length longer than a channel length.