JPH0212867A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To limit the amplitude of an output voltage without slowing down a speed, to eliminate the overshoot of a supply voltage or more and to make it possible to prevent the generation of a latch-up by a method wherein a semiconductor integrated circuit is constituted in such a way that an output level is detected and the gate signal of an output transistor is controlled. CONSTITUTION:A semiconductor integrated circuit having an output circuit constituted of first and second transistors 3 and 4 connected in series between a first potential VDD and a second potential is provided with a means 2 to detect the level of a connection point between the transistors 3 and 4 and a means (an output transistor gate voltage control circuit) 5 to control a gate signal of at least one of the transistors 3 and 4 by an output signal from said detecting means 2. For example, an output circuit which is constituted of a P-channel transistor 3 and an N-channel transistor 4, an output level detecting circuit 2 and a circuit 5 which receives a signal from the circuit 2 and controls a gate signal of the transistor 3 and a circuit (a contact circuit) 7 to control the ON and OFF of the transistors 3 and 4 are provided.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a semiconductor integrated circuit, It is related to.

[Conventional technology]

In particular, the general configuration of a conventional complementary MO8) run lister three-state output circuit is shown in FIG.

P-channel transistor 3 and N-channel transistor 4
A complementary MO8) run lister circuit is constructed, and its output is connected to output terminal 1. The gate input of the P-channel transistor 3 receives the output of an AND gate 17 which receives a control signal from the control terminal 8 and a signal from the input terminal 9. The gate input of the N-channel transistor 4 receives the output of an OR gate 18 which receives an inverted control signal and an input signal.

With this circuit, when a low level input is made to the control terminal 8, the P-channel transistor 3 is turned off and the N-channel transistor 4 is also turned off, regardless of the signal level of the input terminal 9, and the output terminal 1 becomes a high impedance state. When a high level input is made to the control terminal 8 and the input terminal 9, as shown in FIG.
A gate voltage as shown in a) is applied to transistors 3 and 4, P-channel transistor 3 is turned on, N-channel transistor 4 is turned off, and the capacitive load is charged through P-channel transistor 3, and the fifth A high level is output as shown in Figure (b). When a high level is input to the control terminal 8 and a low level is input to the input terminal 9, a gate voltage as shown in FIG. 5(a) is applied to the transistors 3 and 4, and the P-channel transistor 3 is turned off. N-channel transistor 4
turns on, discharges the charge stored in the capacitive load through the N-channel transistor 4, and outputs a low level to the output terminal 1 as shown in FIG. 5(b).

In this case, the output amplitude is from the ground potential GND to the power supply voltage VD.
D, and due to factors such as reductance, there is an overshoot in which the voltage tries to rise to a higher voltage for a while after reaching the power supply voltage, and even after reaching the ground potential, the voltage tends to fall to a lower voltage for a while. A phenomenon called undershoot can be seen. This phenomenon becomes more noticeable as the charging/discharging current is increased to increase the speed.

Next, the 3-state circuit of E/E push pull is shown in Figure 6.
The output waveform is shown in FIG. N-channel transistor 19
．． 20 are connected in series between the power supply voltage vnn and the ground potential GND, the output terminal is connected to the output terminal 1, the gate input of the transistor 19 is connected to the OR output terminal of the control signal and the inverted signal of the input signal, and the gate input of the transistor 20 is connected in series between the power supply voltage vnn and the ground potential GND. are respectively connected to the logical sum output terminals of the control signal and the input signal. The operation of this circuit is the complementary MO3) run lister 3 described earlier.
This is similar to the state output circuit. However, since the transistor 1.9 connected to the power supply terminal side is an N-channel transistor, the source terminal is the output terminal, and when the output terminal attempts to go high, the gate voltage decreases relatively and current flows. Complementary MO
8) Rising time is slower than that of a run lister output circuit. In addition, since it is an N-channel transistor, the output voltage cannot be higher than (power supply voltage VDD) (threshold voltage of N-channel transistor V, 4).
The output amplitude does not have the full amplitude from the ground potential to the power supply voltage unlike the output circuit of complementary MOS transistors.

This operation will be explained with reference to FIG. 7. When the control terminal 8 is at a high level, the transistors 19 and 20 are in an off state regardless of the input signal, and the output terminal 1 is in a high impedance state.

Control terminal 8 is low level, input terminal 9 is high
In the case of the level, gate voltages as shown in FIGS. 7(a) and 7(b) are applied to transistors 19 and 20, respectively, transistor 19 is turned on, transistor 20 is turned off, and as shown in FIG. 7(C). The output potential increases as follows. However, since the transistor 19 connected to the power supply terminal side is an N-channel, the output is (V!ID
Subsequently, when the input terminal 9 becomes Low level, the transistor 19 is turned off and the transistor 20 is turned on, so that the output potential drops as shown in FIG. 7(c).

[Problem to be solved by the invention]

In the conventional complementary MO3) run lister output circuit as described above, the output waveform is as shown in FIG. 5, and although the speed is fast, overshoot and undershoot occur. 8th
The figure shows a cross-sectional view of the complementary MO8, and this overshoot causes the base voltage (well potential
When a voltage higher than that is applied, a collector current icx+ flows through the parasitic PNP transistor 31.

Furthermore, the source 29 of the N-channel transistor and the P substrate 2
1 and the N well 22, the base voltage (P substrate potential) of the parasitic NPN transistor 33 exists between the collector current i
. 8, increases and becomes higher than the emitter voltage, and the collector current i. 8□ flows. Collector current i.

82 flows, the base voltage of the parasitic PNP) run lister 31 decreases, and the collector current ici+ further decreases.
begins to flow.

Repeating this causes a phenomenon in which current continues to flow unless the power is turned off. This phenomenon is called latch-up phenomenon, and undershoot also causes latch-up phenomenon.

This phenomenon can be said to be a drawback specific to complementary MO8) run lister circuits.

In addition, in the E/E push-pull, the output circuit is entirely composed of N-channel transistors, so even if an overshoot occurs, the P substrate and the drain of the N-channel transistor are reverse biased, so latch-up can be avoided. Don't cause it. However, as mentioned above, since the transistor connected to the power supply terminal side is an N-channel transistor, when the output attempts to reach a high level, the gate voltage decreases relatively, making it difficult for current to flow. ) The disadvantage is that the rise time is slower than that of the run lister output circuit.

〔the purpose〕

The present invention detects the output level and controls the gate signal of the output transistor to limit the output amplitude without slowing down the speed, eliminate overshoot above the power supply voltage, and prevent the phenomenon of run-up. In addition, the amplitude limit reduces the charge stored in the output load capacitance,
Reduces transient current when signal is reversed. Therefore, undershoot is reduced, latch-up is prevented, and the power supply and GN caused by the LSI itself, which is a problem with current multi-pin LSIs, are reduced.
This also suppresses the occurrence of D noise.

[Means to solve the problem]

The semiconductor integrated circuit of the present invention is a semiconductor integrated circuit having an output circuit composed of a first M08) run lister of a first polarity and a second M08) run lister of a second polarity connected in series between a power supply terminal and a ground terminal. a circuit for detecting an output level at a connection point between the first MOS transistor and the second M08) run lister; and the first M08) run lister and the second M03
) A circuit for controlling at least one gate signal of the run lister by a signal from the detection circuit.

By detecting the output level and controlling the gate signal of the output transistor, the amplitude of the output voltage is limited without slowing down the speed, eliminating overshoot above the power supply voltage and preventing latch-up. . In addition, due to the t amplitude limit, the charge stored in the output load capacitance becomes smaller, and the transient current becomes smaller. Therefore, undershoot is reduced, latch-up phenomenon is prevented, and the power supply by the LSI itself, which is a problem with current multi-bin LSIs, is eliminated.
It is also possible to suppress the generation of GND noise.

〔Example〕

DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention.

In FIG. 1, a P-channel transistor 3 and an N-channel transistor 4 are connected in series between the power supply and ground terminals.
an output circuit consisting of an output circuit 2, an output level detection circuit 2 for the output terminal 1, a circuit 5 that receives a signal from the output level detection circuit and controls the gate signal of the P-channel transistor 3, and a circuit 5 for controlling the gate signal of the P-channel transistor 3 and the N-channel It is composed of a circuit 7 that controls on/off of the transistor 4.

The operation of this circuit is as follows.

When the output 6 of the control circuit 7 changes from High to Low, the N-channel transistor 4 is turned off.

Complementary MO8) When the output of the run lister circuit has not reached the output level, the output transistor gate voltage control circuit 5 outputs the output 6 of the control circuit 7 as it is,
P-channel transistor 3 is turned on, and the voltage at output terminal 1 increases. However, when the output voltage exceeds the output level, the signal from the control circuit 7 is not transmitted from the output level detection circuit 2 to the output transistor gate voltage control circuit 5, and the output is unconditionally set to High, and the P-channel transistor 3 is turned off. controlled. Therefore, the output voltage does not increase any further. Therefore, even if overshoot occurs, the voltage will not exceed the power supply voltage.

Further, when the output of the control circuit 7 changes from Low to High, the N-channel transistor 4 is turned on, the P-channel transistor 3 is turned off, and a low level is outputted to the output terminal 1.

FIG. 2 shows the detailed configuration of the present invention.

The control circuit 7 receives a control signal from a control terminal 8 and an input terminal 9.
The NAND gate 18 receives the input signal from the output transistor gate voltage control circuit 5, and the NOR gate 18 receives the inverted signal of the control signal and the input signal. In addition, the outputs of the NOR gates 18 are connected to the gate inputs of the N-channel transistors 4, respectively. NAND game) 17. The logic levels output from the NOR game (NOR game) 18 are the same. Further, the inverted signal of the control signal is also supplied to the gate input of the P-channel transistor 11 of the output level detection circuit 2.

The output level detection circuit 2 includes a P-channel transistor 11.
12 and a protection resistor 10, and a series circuit consisting of a P channel transistor 13 and an N channel transistor 15, and the gates of P channel transistors 12 and 13 are connected to each other. The other end of the resistor 10 is connected to the output terminal 1, and the output of the series circuit of transistors 13 and 15 is supplied to the output transistor gate voltage control circuit 5.

The output transistor gate voltage control circuit 5 is composed of a transfer gate 16 and a P channel transistor 14, and the signal from the output level detection circuit 2 is supplied together with its inverted signal to the gate inputs of the P and N channel transistors forming the transfer gate 16. be done.

Next, the operation will be explained with reference to FIG.

When a low level is applied to the control terminal 8, a high level is output from the NAND gate 17 regardless of the level of the input terminal 9, and a low level is output from the NOR gate 18.

At this time, N-channel transistor 4 is turned off, and P-channel transistor 11 is also turned off.

Therefore, no current flows through P-channel transistors 12 and 13, and the output from output level detection circuit 2 is Low.
level. In response to this Low level from the detection circuit 2, the P channel transistor 14 is turned on, the transfer gate 16 is turned off, and a High level is applied to the gate of the P channel transistor 3.
Turns off. Therefore, the output terminal 1 becomes in a high impedance state.

Next, when a High level is applied to the control terminal 8 and the input terminal 9, the NAND 17 and N0R18 of the control circuit 7 output a Low level as shown in FIG. 3(a). Therefore, N-channel transistor 4 is turned off and P-channel transistor 11 is turned on. When the output terminal 1 is at a low level, current flows through the p-channel transistor 11 to the p-channel transistors 12 and 13, and the output level detection circuit 2 outputs a high level. This High
In response to the h level, transfer gate 16 is turned on and P channel transistor 14 is turned off.

In this way, the output Low of NANDl 7 is as shown in Fig. 3(b).
It is transmitted to the P-channel transistor 3 as shown in FIG.
increase the voltage. However, the output voltage (power supply voltage V
nn Threshold voltage V of P-channel transistor 12
? When i) is reached, no current flows through the P-channel transistor 12, and the output of the output level detection circuit 2 is inverted and becomes Low level.

Therefore, the transfer gate 16 in the output transistor gate voltage control circuit 5 is turned off, and the 2NAND gate 17
The output of is no longer transmitted to the P-channel transistor 3. At this time, the P-channel transistor 14 is turned on, and the gate voltage of the P-channel transistor 3 becomes Hi.
gh, the P-channel transistor 3 is turned off, and the output voltage no longer increases as shown in FIG. 3(c). If the output terminal 1 is at a high level, such an operation is not necessary.

High level at control terminal 8, Lo at input terminal 9
When a w level input is made, a high level is output from NANDl7 and N0R18 as shown in FIG. 3(a), and N channel transistor 4 and P channel transistor 11 are turned on.

Therefore, current flows from the P-channel transistors 12 and 11 to the N-channel transistor 4, and the output of the output level detection circuit 2 is inverted and becomes High. Therefore, since the transfer gate 16 is turned on, 2
The output of the NAND gate 17 is the P-channel transistor 3
The P-channel transistor 3 is turned off, and the output voltage gradually decreases as shown in FIG. 3(c).

〔Effect of the invention〕

As is clear from the above description, the semiconductor integrated circuit of the present invention detects the output level and controls the gate signal of the output transistor to limit the output amplitude without slowing down the speed, and Overshoot can be eliminated and latch-up can be prevented. In addition, amplitude limiting reduces the charge stored in the output load capacitance and reduces transient current, which reduces undershoot and suppresses latch-up.
Power supply and GND caused by the LSI itself, which is a problem with SI
It is also possible to suppress noise generation.

[Brief explanation of the drawing]

Figure 1 is a configuration diagram of the present invention, Figure 2 is a circuit diagram of an embodiment of the present invention, Figure 3 is an explanatory diagram of the output waveform of the present invention, and Figure 4 is composed of a conventional complementary MO8) run lister. 3-state output circuit diagram, Figure 5 is the output waveform diagram of the circuit in Figure 4, and Figure 6 is the output waveform diagram of the circuit in Figure 4.
The figure is a three-state output circuit diagram configured with an E/E push pull, FIG. 7 is an output waveform diagram of the circuit of FIG. 6, and FIG. 8 is a cross-sectional view of a complementary MOS transistor circuit. 1... Output terminal, 2... Output level detection circuit, 3.11 to 14... P channel transistor, 4.15, 19.20... N-channel transistor, 5... Output transistor gate voltage control circuit, 6... Output of control circuit, 7...
...Control circuit, 8...Control terminal, 9...
...Input terminal, 10...Protection resistor, 16...
...Transfer Gate, 17...NAN
D gate, 18...NOR gate, 21...
...P type substrate, 22...N well, 23...
...P type drain region, 24.28 ... Gate electrode, 25 ... P type source region, 26 ...
...Well contact, 27...N type drain region, 29...N type source region, 30...
... Substrate contact, 31 ... Parasitic PNP
) Run lister, 32...N-well resistance, 33
...parasitic NPN) run lister, 34...
・Resistance of P type board. Agent: Susumu Uchihara, Patent Attorney

Claims (1)

[Claims] In a semiconductor integrated circuit having an output circuit including a first transistor and a second transistor directly connected between a first potential and a second potential, the first transistor and the second transistor 1. A semiconductor integrated circuit comprising: means for detecting a level at a connection point; and means for controlling a gate signal of at least one of the first transistor and the second transistor by an output signal from the detecting means.