JPH02223222A - Output circuit - Google Patents

Abstract

PURPOSE:To suppress the temporal change of a current, to reduce the fluctuation of the ground potential, and to prevent the malfunction of the inside of an IC by attaching a transfer gate and a gate signal control circuit to control the conductance of the transfer gate on an output circuit. CONSTITUTION:A P-type transistor M1 connected between an output terminal Oi and a power source potential terminal, a first N-type transistor M2 connected between the output terminal Oi and a reference potential terminal, first and second inverter circuits INV1 and INV2 which set a data input signal, the inverse of DATAi as input, and a two-input NAND circuit NA and a two-input NOR circuit NO which set the output signals A and B and output control signals OC and the inverse of OC of the inverters as input are provided. And the transfer gate M3 inserted between the output terminal of the NOR circuit NO and the gate of the first N-type transistor M2 and a gate control circuit INV3 which controls the magnitude of the conductance of the transfer gate M3 in an opposite direction corresponding to the level of the potential of the output terminal are attached. Thereby, the gate input signal of the N-type transistor M2 for output driving is controlled, and the temporal change of the current can be suppressed to a low level.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to a CMO3 output circuit built into a semiconductor memory or a microcomputer.

[Conventional technology]

Conventionally, this type of output circuit generally has a circuit configuration as shown in FIG. Here, INVI, 2 is an inverter circuit, No is a 2-input NOR circuit, NA is a 2-input NAND circuit, 1M1 is a P-type transistor for output drive,
M2 is an N-type transistor for output driving. Also DAT
Ai is a data input terminal, ol is an output terminal, and these two
One is parallel. However, i indicates the number of bit configurations. Further, QC and QC are first and second output control signal terminals having opposite phases to each other, and control the output state.

For example, when inputting OC="H", ■=L, an output signal appears at 01, and conversely, ○C="L IIoc="H"
When input, Oi becomes high impedance state.

[Problem to be solved by the invention]

In the conventional output circuit described above, when the output driving N-type transistor is rapidly turned on, the GN is
This has the disadvantage that the D potential fluctuates, resulting in malfunction inside the IC.

An object of the present invention is to provide an output circuit that can control the gate input signal of an output driving N-type transistor and suppress temporal changes in current.

1 [Means for Solving the Problems] The output circuit of the present invention includes a P-type transistor connected between an output terminal and a power supply potential terminal, and a first N-type transistor connected between the output terminal and a reference potential terminal. a transistor, a first inverter circuit that receives a data input signal as input, and two inputs that receive an output signal of the first inverter circuit and a first output control signal and supply the output to the gate of the P-type transistor. a NAND circuit, a second inverter circuit 8 which receives the data input signal as input, and receives an output of the second inverter circuit and a second output control signal having an opposite phase to the first output control signal; 2-input NOR circuit and the NOR circuit
A transmission gate inserted between the output end of the R circuit and the gate of the first N-type transistor, and a gate control circuit that controls the conductance of the transmission gate in opposite directions depending on the level of the potential of the output terminal. This includes the following.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of a first embodiment of the present invention.

DATAi is a data input terminal, Ol is an output terminal,
Each has an opposite phase. M, , and M2 are P-type and N-type transistors for output driving, respectively, and their gate input signals are C and E.M3 is a depletion type transistor (transmission gate), and its drain and source are respectively designated as E. , the gate input signal is F. INVI, 2
is an inverter circuit, INV3 is an inverter circuit as a gate control circuit, NA is a 2-input NAND circuit, and NO is a 2-input NAND circuit.
It is an input NOR circuit, and the input signal of INVI is DATA.
i, and the output signal is A.

The input of INV2 is DATAi, and the output signal is B. The input signal of NA is the first output control signal OC and A, the output signal is C, and the input signal of NO is the second output control signal OC.
and B, the output signal is connected to D.

The input of INV3 is the output signal oi, and the output is connected to the gate F of the n-channel depletion type MoS transistor M3.

FIG. 4 shows the operation timing.

As shown in FIG. 4(b), DATAi is “L”→ll
When changing to HI+, ``Since the initial output Oi is ``81 lvl, F becomes ``LI+ level,'' and E becomes F-.
(Threshold voltage of M3), M2 starts to turn on, and Ol starts to decrease. In this region, gm of M2 is small and current changes can be suppressed.

When Of further decreases, INV3 detects the decrease in Ol and outputs an "H" level signal to F. As a result, E also fully swings to the "H" level, and M2 operates in the gm-large region, accelerating the decrease in Oi. By doing the above, the sudden switching (off → on) of M2 is suppressed, and M2 remains on for a while in the low gain region (g
It is possible to operate at low gain (m small) and then shift to a high gain region upon feedback of the output level, thereby suppressing sudden changes in current.

FIG. 2 is a circuit diagram of a second embodiment of the invention.

In this embodiment, a P-type transistor M whose source is connected to a power supply potential terminal and whose gate is applied with a second output control signal oC,
and the source connected to the drain of M5 and the output signal terminal O
a P-type transistor M4 having a gate connected to f;
The resistor R inserted between the drain of M4 and the GND terminal constitutes a gate control circuit. When OC is "HT1," this gate control circuit is reliably turned off, which has the advantage of lower power consumption than in the first embodiment.

〔Effect of the invention〕

As explained above, the present invention suppresses temporal changes in current by adding a transmission gate and a gate signal control circuit that controls its conductance to the output circuit.
This has the effect of reducing fluctuations in the D potential and preventing malfunctions inside the IC.

Transmission type transistor (transmission gate), M4 0M5・
・P-type transistor, R...resistance, INV1~3・
...Inverter circuit, NA...2-input NAND circuit,
NO...2 input NOR circuit.

Claims (1)

[Claims] a P-type transistor connected between the output terminal and the power supply potential terminal; and a first N transistor connected between the output terminal and the reference potential terminal.
a first inverter circuit which receives a data input signal as an input, and a first inverter circuit which receives an output signal and a first output control signal of the first inverter circuit and whose output is connected to the P.
a two-input NAND circuit that supplies the data input signal to the gate of the type transistor; a second inverter circuit that receives the data input signal as input; a two-input NOR circuit that receives an output control signal as input; a transmission gate inserted between the output terminal of the NOR circuit and the gate of the first N-type transistor; and a gate control circuit that controls the magnitude of conductance of the gate in the opposite direction.