JPH0567961A - Output buffer circuit - Google Patents

Abstract

PURPOSE:To change the output drive capability matching the operating condition by connecting plural transistors(TRs) of an output final stage in parallel and using a control signal so as to turn off part of the TRs of the output final stage. CONSTITUTION:When an H level is inputted to a control signal input terminal 3, an output of a NOR gate 40 goes to an L level and an output of a NAND gate 35 goes to an H level and TRs 10, 20 are turned off. On the other hand, since an inverse signal at an input terminal 1 is inputted to output TRs 11, 21 through an inverter 31, the TRs are always operated independently of the state of the input terminal 3. Conversely, when an L level is inputted to the input terminal 3, since an inverse signal at the terminal 11 is inputted to the TRs 10, 20, the TRs 10, 11 are simultaneously in operation and the TRs 20, 21 are simultaneously in operation. Thus, a larger output drive capability is obtained in comparison with that when an H level is inputted to the terminal 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to a semiconductor integrated circuit,
Particularly, it relates to the output buffer circuit.

[0002]

2. Description of the Related Art In a general semiconductor integrated circuit, an output buffer or an input buffer which plays a role of an interface is often placed between the inside of the semiconductor integrated circuit and an external terminal. In particular, the output buffer has a large external load. It may have to be driven, and often has a large drive capacity.

In recent years, the number of output buffers built in one semiconductor integrated circuit has also become very large in order to meet the needs of large scale. An output buffer having a large driving capability consumes a large amount of power and may generate a large amount of noise during operation, which may cause a malfunction.

FIG. 4 shows an example of a conventional output buffer circuit of a CMOS semiconductor integrated circuit. In FIG. 4, 1 is an input terminal, 2 is an output terminal, 8 is a connection to a power supply, 9 is a connection to ground, 13 is a P-channel type MOS transistor, 2
Reference numeral 4 is an N-channel MOS transistor, and 31 is an inverter for driving the output transistor.

The circuit of FIG. 4 is an ordinary output buffer, but FIG. 5 shows a circuit example of a 3-state output buffer.
In FIG. 5, 1 is an input terminal, 2 is an output terminal, 6 is a control input terminal, 14 is a P-channel type MOS transistor, 25 is an N-channel type MOS transistor, 3
3 is an inverter, 37 is a NAND gate, 43 is NO
It is an R gate. In the circuit of FIG. 5, the output terminal 2 can be in a high impedance state.

In general, the output buffer of a semiconductor integrated circuit has a large load capacity, and it is necessary to operate at a high speed to some extent. Therefore, the driving capability of the output buffer is often made sufficiently large. Driving capacity is generally expressed by output current,
In some CMOS gate arrays and the like, 2 mA to 24 mA are prepared depending on the driving load.

The larger the driving capacity is, the faster the movement can be made. On the other hand, if the driving capacity is too large, the current flowing at the time of operation becomes large, and a large noise is generated. May cause. Therefore, conventionally, a large number of output buffer circuits having different driving capacities are prepared, and the most suitable one is selected and used according to the intended use, the connected load capacity, and the operating speed.

Therefore, once selected, the driving ability can no longer be changed, and it has been impossible to change the driving ability due to changes in usage conditions.

[0009]

The conventional output buffer cannot change the driving capacity according to the connected load capacity, and can only drive the load with a predetermined driving capacity.

Therefore, the problem to be solved by the present invention is to realize an output buffer whose drive capability can be freely changed.

[0011]

According to the output buffer of the present invention, a plurality of transistors at the final stage of output are connected in parallel, a part of the transistors at the final stage of output is turned off by a control signal, and the output drive capability is set to a usage condition. It should be changed in accordance with it.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An output buffer circuit of the present invention will be described with reference to the drawings. FIG. 1 shows an embodiment of the present invention.
In FIG. 1, 1 is an input terminal, 2 is an output terminal, 3 is a control signal input terminal, 8 is a power supply, 9 is GND, 10 and 11 are P-channel type MOS transistors, 20 and 21 are N-channel type MOS transistors, and 30. , 31 is an inverter, 35
Is a NAND gate and 40 is a NOR gate.

Now, assuming that a high level is input to the control signal input terminal 3, the output of the NOR gate 40 is low and the output of the NAND gate 35 is high. Therefore, the P-channel type MOS transistor 10 and the N-channel type MOS transistor 20 are in the off state.

On the other hand, the output transistors 11 and 21 are always operated regardless of the state of the control signal input terminal 3 because the inverted signal of the input terminal 1 is input by the inverter 31.

On the contrary, when a low level is input to the control signal input terminal 3, the inverted signal of the input terminal 1 is input to the output transistors 10 and 20, so that the output transistor 1
0 and 11 operate simultaneously and output transistors 20 and 21
Work at the same time. Therefore, a larger output drive capability can be obtained as compared with when a high level is input to the control input terminal 3.

As described above, if the output drive capability can be dynamically changed by the control signal, the output power can be controlled by an external circuit to increase the drive power when the same output buffer has a large load capacity to operate at a higher speed. When the load capacity is small, it is possible to reduce the noise by reducing the driving ability.

FIG. 2 shows another embodiment of the present invention. Figure 2
Then, the output P channel type MOS transistors 10 and 1
1 and 12 are connected in parallel and output N channel type MOS
Transistors 20, 21, 22 are connected in parallel. Further, 1 is an input terminal, 2 is an output terminal, 3 and 4 are control input terminals. 30 to 32 are inverters, 35,
36 is a NAND gate, and 40 and 41 are NOR gates. Since the circuit of FIG. 2 has two control input terminals, the drive capability can be controlled more finely than the circuit of FIG.

FIG. 3 shows another embodiment of the present invention.
In FIG. 3, N-channel MOS transistors 21 and 23 are shown.
Are in parallel, and the P-channel type MOS transistors are not connected in parallel. Therefore, it is possible to control whether the N-channel type MOS transistor 23 is turned on or off by the control input signal 5, so that only the low level output current can be changed. When driving a TTL IC, a high level output current is not necessary so much, and a low level output current is sufficient, so the circuit of FIG. 3 is very effective.

Although the circuits shown in FIGS. 1 to 3 are all for normal output buffers, they can be easily applied to 3-state output buffers. For example, in the case of the circuit of FIG. 1, the inverter 31, the MOS transistors 11 and 2,
1 can be realized by replacing the conventional 3-state output buffer circuit of FIG. Similarly, it can be applied to a bidirectional output block.

In the above description, the embodiment in the case of CMOS has been described, but TTL, Bi-CMOS, EC
Obviously, this can be applied to the L semiconductor integrated circuit.

[0021]

As described above, if the output buffer circuit of the present invention is used, the driving capacity can be changed according to the load capacity connected to the output, so that the current consumption, the noise generated, and the delay time are increased. Can be freely changed according to the intended use and the required operation speed.

Further, when designing a semiconductor integrated circuit, it is not necessary to make many output buffers having different driving capabilities, and there is an advantage that the design efficiency can be improved.

[Brief description of drawings]

FIG. 1 is an output buffer circuit diagram of the present invention.

FIG. 2 is another circuit diagram of the output buffer circuit of the present invention.

FIG. 3 is a circuit diagram of an output buffer circuit according to a third embodiment of the present invention.

FIG. 4 is a conventional output buffer circuit diagram.

FIG. 5 is a conventional 3-state output buffer circuit diagram.

[Explanation of symbols]

 1: Input terminal 2: Output terminal 3-5: Control input terminal 6: 3-state control terminal 8: Power supply (VDD) 9: Ground (GND) 10-14: P-channel type MOS transistor 20-25: N-channel type MOS Transistors 30-33: Inverters 35-37: NAND gates 40-43: NOR gates

Claims (5)

[Claims] 1. An output circuit of a semiconductor integrated circuit, wherein a plurality of transistors at a final stage of output are connected in parallel, a data input terminal and at least one control signal input terminal are provided, and a part of the plurality of transistors is provided. Is always operated by the signal of the data input terminal, and the other transistors can be selected to be always off or operated by the signal of the data input terminal depending on the state of the control input terminal. Output buffer circuit. 2. The output buffer circuit according to claim 1, wherein the output buffer circuit is a 3-state output. 3. The output buffer circuit according to claim 1 or 2, wherein the circuit is composed of CMOS. 4. The output buffer circuit according to claim 1 or 2, wherein the circuit is formed of a bipolar circuit. 5. The output buffer circuit according to claim 1 or 2, wherein the circuit is composed of a CMOS and a bipolar.