JPH0258925A - Output circuit - Google Patents

Abstract

PURPOSE:To prevent an error action and simultaneously, to reduce an energy consumption by increasing/decreasing a driving ability according to the load of an external part to be connected. CONSTITUTION:When a signal to an input terminal 2 is at a low level, to the driving ability and energy consumption, only a first C-MOS circuit composed of a P-channel transistor 11 and an N-channel transistor 12 is related. When the signal to the input terminal 2 is at a high level, to the driving ability and energy consumption, two C-MOS circuits of the first C-MOS circuit and a second C-MOS circuit composed of a P-channel additional transistor 13 and an N- channel additional transistor 14 are related. In such a manner, the C-MOS circuit to be driven can be increased/decreased according to the load of the external part to be connected, the driving ability can be increased/decreased, thereby, the error action can be prevented, and simultaneously, the energy consumption can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an output circuit, and particularly to an output circuit used as an output buffer circuit or the like of a semiconductor integrated circuit.

[Conventional technology]

Conventionally, an output buffer circuit of a semiconductor integrated circuit has been used to transmit a logic signal inside the semiconductor integrated circuit to an external load and to control the external load. The ability of an output buffer to control an external load is called drive capacity, and the greater the drive capacity, the greater the ability to control an external load.

FIG. 3 is a circuit diagram showing an example of a conventional output circuit, and FIG. 4 is a timing chart of the circuit shown in FIG. As shown in FIG. 3, the conventional output circuit includes a P-channel transistor 34 and an N-channel transistor 35 whose gates are connected to an input terminal 31 via an inverter 32.
A C-MO9 circuit is configured by connecting the output terminal 36 to each drain of
The power source was connected to the second power supply, which caused the power supply to go sideways.

Next, the operation of the circuit will be explained. As shown in FIG. 3, when a low level signal is input to the input terminal 31, the output 33 of the inverter 32 becomes high level, so the operation of the P channel transistor 34 is OFF and the operation of the N channel transistor 35 is ON. Therefore, the output signal of the output terminal 36 becomes low level. The driving capability is that of the N-channel transistor 35, which drives an external load. Next, when a high level signal is input to the input terminal 31, the output 33 of the inverter 32 becomes low level, so the operation of the P channel transistor 34 is turned on.
The operation of N-channel transistor 35 is turned off, and the output signal of output terminal 36 becomes high level. The driving capacity is
This becomes the driving capability of the P-channel transistor 34 and drives an external load.

[Problem to be solved by the invention]

In the conventional output circuit described above, the driving capability is limited to one transistor of the C-MOS circuit, so if a larger external load is connected, there is a problem that malfunction may occur. As a countermeasure, it is considered to increase the size of the P-channel transistor and N-channel transistor that constitute the C-MOS circuit, or to connect two or more C-MOS circuits in parallel. However, in this case, when the external load is equal to the maximum driving capacity of the output circuit, the power consumption of the circuit is small, but there is a drawback that the power consumption increases as the external load becomes lighter.

SUMMARY OF THE INVENTION An object of the present invention is to provide an output circuit that can increase/decrease drive capability according to a connected external load, prevent erroneous operation, and reduce power consumption.

[Means to solve the problem]

The output circuit of the present invention has a first P-channel transistor and a first N-channel transistor connected in series, each gate connected to an input terminal, and each drain connected to an output terminal. a first C-MOS circuit; a logic circuit that outputs an AND signal of an input signal from the input terminal and a control signal from the control signal input terminal; a second P-channel transistor connected in series; and at least one second C-MOS circuit having two N-channel transistors, each gate of which is connected to the logic circuit output, and each drain of which is connected to the output terminal.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

Fig. 1 is a circuit diagram showing one embodiment of the present invention, and Fig. 2 is a circuit diagram showing an embodiment of the present invention.
3 is a timing chart of the circuit shown in the figure.

As shown in FIG. 1, the gates of the P-channel transistor 11 and N-channel transistor 12 connected in series are connected to the input terminal 1 via the inverter 5, and the drains of each are connected to the output terminal 15. C-MO
An S circuit is configured, and the source of P-channel transistor 11 is connected to a first power source, and the source of N-channel transistor 12 is connected to a second power source. On the other hand, the gates of P channel addition 1 to transistor 13 connected in series are N
It is connected to the input terminal 1 and the input terminal 2 to which the control signal is input via AND7, and is connected to the N-channel sized transistor 1.
The gate of 4 is connected to the input terminal 1 via N0R9 and the input terminal 2 via the inverter 3, and the drain of each is connected to the output terminal 15 to form a second C-MOS circuit. The source of the transistor 13 is connected to the first power supply, and the source of the N-channel additional transistor 14 is connected to the second power supply.

Next, the operation of this circuit will be explained. As shown in FIG. 2, when a high level is input to input terminal 1 and a low level is input to input terminal 2, output 4 of inverter 3 is high level, output 6 of inverter 5 is low level, output 8 of NAND 7 is high level, N0R9 output 10 becomes low level,
Therefore, the operation of P channel 1 to transistor 11 is on.
Since the operation of the transistor in the pond is off, the output terminal 1
The output level of transistor 5 is high level, and the driving ability and power consumption are related only to the P-channel transistor 11. Next, when the signal to the input terminal 2 is changed from low level to high level, the output 4 of the inverter 3 changes from high level to low level, and the output 8 of NAND 7 changes from high level to low level. turns on. As a result, the output level 15 is similarly high, but the driving ability and power consumption are lower than that of the P-channel transistor 11 and the P-channel addition 1.
- will be related to both transistors 13. Further, when a low level is input to the input terminal 1 and a low level to the input terminal 2, the operation of the N-channel transistor 12 is turned on and the operation of the other transistors is turned off. Therefore, the output level 15 becomes a low level, and the driving ability and power consumption are N
Only channel transistor 12 will be involved.

Next, when the signal to the input terminal 2 is changed from low level to high level, the N-channel additional transistor 14 is turned on, so the output level 15 is also low level, but the driving ability and power consumption are Both transistor 12 and N-channel additional transistor 14 will be involved.

In other words, when the signal to input terminal 2 is at low level, only the first C-MOS circuit composed of P-channel transistor 11 and N-channel transistor 12 is concerned with the driving ability and power consumption, and the signal to input terminal 2 When is at a high level, the driving ability and power consumption of the P-channel transistor 11
A first C-
A second CM composed of a MOS circuit, a P-channel additional transistor 13, and an N-channel additional transistor 14
It is related to the two C-MOS circuits of the OS circuit. In this embodiment, the P
NAND7. N0R9
and is connected to input terminal 2 via inverter 3, but when the signal to input terminal 2 is high level, the second C-MOS
A similar effect can be achieved if the circuit is a driving logic circuit.6Furthermore, although this example uses two C-MOS circuits, it is also possible to use three or more 0M03 circuits. be.

〔Effect of the invention〕

As explained above, the present invention is capable of controlling a connected external load by connecting a control signal input terminal to the gate of at least one C-MOS circuit among a plurality of C-MOS circuits connected in parallel. Since the driving capacity can be increased or decreased by increasing or decreasing the number of C-MOS circuits to be driven depending on the current, it is possible to prevent erroneous operation and reduce power consumption.

1...Input terminal, 2...Input terminal, 3
．． 5...Inverter, 7...NAND
, 9...N0R211...P channel transistor, 12...N channel transistor, 13...P channel additional transistor, 1
4...N-channel additional transistor, 15...
...Output terminal, 31...Input terminal, 32.
...Inverter, 34...P channel transistor, 35...N channel transistor,
36... Output terminal.

Claims (1)

[Claims] a first P-channel transistor connected in series;
a first C-MOS circuit having N-channel transistors each having a gate connected to an input terminal and each drain connected to an output terminal; an input signal from the input terminal and a control signal input terminal; a logic circuit that outputs an AND signal with a control signal from the logic circuit; a second P-channel transistor and a second N-channel transistor connected in series, each gate of which is connected to the output of the logic circuit; at least one second C-MOS circuit, each drain of which is connected to an output terminal.