JPH01225223A - Cmos logic circuit - Google Patents

Cmos logic circuit

Info

Publication number
JPH01225223A
JPH01225223A JP63050839A JP5083988A JPH01225223A JP H01225223 A JPH01225223 A JP H01225223A JP 63050839 A JP63050839 A JP 63050839A JP 5083988 A JP5083988 A JP 5083988A JP H01225223 A JPH01225223 A JP H01225223A
Authority
JP
Japan
Prior art keywords
input
circuit
channel
cmos logic
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63050839A
Other languages
Japanese (ja)
Inventor
Yukio Sawada
沢田　幸男
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC IC Microcomputer Systems Co Ltd
Original Assignee
NEC IC Microcomputer Systems Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC IC Microcomputer Systems Co Ltd filed Critical NEC IC Microcomputer Systems Co Ltd
Priority to JP63050839A priority Critical patent/JPH01225223A/en
Publication of JPH01225223A publication Critical patent/JPH01225223A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/0021—Modifications of threshold
    • H03K19/0027—Modifications of threshold in field effect transistor circuits

Abstract

PURPOSE:To control an input threshold from an external part with being matched to a using condition by selecting the outputs of plural input circuits which are respectively operated by the plural types of the different input thresholds. CONSTITUTION:A basic inverter circuit is composed of FETs1 and 2. When a '0' level is given to a control terminal 7, this circuit goes to be an inverter circuit, with which only the FETs1 and 2 are operated. When a '1' level is given to the control terminal 7, an additional channel FET3 executes the same operation as the N-channel FET2. Thus, the ability of the N-channel FET2 is improved and the input threshold goes to be low.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明はＣＭＯＳ論理回路に関する。[Detailed description of the invention] [Industrial application field] The present invention relates to CMOS logic circuits.

〔従来の技術〕[Conventional technology]

従来のＣＭＯＳ論理回路は、ＰチャネルＦＥＴとＮチャ
ネルＦＥＴの能力によって定まるある一定の入力しきい
値で動作するようになっていた。Conventional CMOS logic circuits operate at a certain input threshold determined by the capabilities of the P-channel FET and N-channel FET.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

上述した従来のＣＭＯＳ論理回路では、入力信号が振幅
の中心に合っていない場合が有るので、入力信号自身に
ノイズが重畳しているような場合、ノイズに対するマー
ジンが少なくなりζ安定性が低く、ノイズにより誤動作
しやすいという欠点が有る。In the conventional CMOS logic circuit described above, there are cases where the input signal does not match the center of the amplitude, so if noise is superimposed on the input signal itself, the margin against noise is reduced and ζ stability is low. It has the disadvantage of being prone to malfunction due to noise.

本発明の目的は、このような欠点を除き、使用状態に合
わせて入力しきい値を外部から制御できるようにしたＣ
ＭＯＳ論理回路を提供することにある。It is an object of the present invention to eliminate such drawbacks and to provide a C that enables input thresholds to be externally controlled according to usage conditions.
The purpose of this invention is to provide a MOS logic circuit.

〔課題を解決するための手段〕[Means to solve the problem]

本発明のＣＭＯＳ論理回路の構成は、複数種類の相異な
る入力しきい値でそれぞれ動作する複数の入力回路と、
これら入力回路のうちの１つの出力を外部からの制御信
号により選択する制御回路とを備えることを特徴とする
。The configuration of the CMOS logic circuit of the present invention includes a plurality of input circuits each operating at a plurality of types of different input thresholds,
It is characterized by comprising a control circuit that selects the output of one of these input circuits using a control signal from the outside.

〔実施例〕〔Example〕

次に本発明について図面を参照して説明する。 Next, the present invention will be explained with reference to the drawings.

第１図は本発明の一実施例のインバータの回路図である
。図中、１はＰチャネルＦＥＴ、２はＮチャネルＦＥＴ
であり、これらＦＥＴ１．２で基本的なインバータ回路
となる。さらに、３は付加されたＮチャネルＦＥＴ、４
はＦＥＴ３を制御するＡＮＤ回路である。また、５は入
力端子、６は出力端子７はしきい値の制御端子である。FIG. 1 is a circuit diagram of an inverter according to an embodiment of the present invention. In the figure, 1 is a P-channel FET, and 2 is an N-channel FET.
These FETs 1.2 form a basic inverter circuit. Furthermore, 3 is an added N-channel FET, 4
is an AND circuit that controls FET3. Further, 5 is an input terminal, and 6 is an output terminal 7 is a threshold control terminal.

通常、制御端子７に“０”レベルを加えていると、この
回路はＦＥＴＩ、２のみ動作するインバータ回路となっ
ているが、制御端子７に“１パレベルを加えると付加Ｎ
チャネルＦＥＴ３がＮチャネルＦＥＴ２と同じ動作を行
う。これにより、ＮチャネルＦＥＴ２の能力が上がり、
入力しきい値を通常よりも低くすることができる。Normally, when a "0" level is applied to the control terminal 7, this circuit becomes an inverter circuit in which only FETI and 2 operate, but when a "1 level" is applied to the control terminal 7, an additional N
Channel FET3 performs the same operation as N-channel FET2. This increases the capacity of N-channel FET2,
The input threshold can be lower than normal.

第２図は本発明の第２の実施例の回路図である。本実施
例は、入力しきい値の高いインバータ８部よび入力しき
い値の低いインバータ９を設け、これを制御端子７から
の制御信号によりインバータ１０．ＡＮＤ回路１１．１
２およびＯＲ回路からなる切換回路で切換えて出力する
ものである。FIG. 2 is a circuit diagram of a second embodiment of the invention. In this embodiment, an inverter 8 with a high input threshold and an inverter 9 with a low input threshold are provided, and these are connected to the inverter 10 . AND circuit 11.1
2 and an OR circuit to switch and output.

この制御端子７に“０”レベルを入力すると、インバー
タ８の高い入力しきい値で動作し、また“１″ルベルを
入力するとインバータ９の低い入力しきい値で動作する
。When a "0" level is input to the control terminal 7, the inverter 8 operates at a high input threshold, and when a "1" level is input, the inverter 9 operates at a low input threshold.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明は、制御信号により入力しき
い値を変化させる事により、入力信号の振幅の最適値に
合わせる事ができ、電源等による外部ノイズが入力信号
に重畳された場合にも誤動作し難くすることができる効
果が有る。As explained above, the present invention can adjust the amplitude of the input signal to the optimum value by changing the input threshold value using the control signal, and even when external noise from the power supply etc. is superimposed on the input signal. This has the effect of making it difficult to malfunction.

【図面の簡単な説明】[Brief explanation of the drawing]

第１図、第２図は本発明の第１および第２の実施例の回
路図である。 １・・・ＰチャネルＦＥＴ、２．３・・・ＮチャネルＦ
ＥＴ、４．１１．１２・・・ＡＮＤ回路、５・・・入力
端子、６・・・出力端子、７・・・制御端子、８・・・
高しきい値インバータ、９・・・低しきい値インバータ
、１０・・・インバータ、１３・・・ＯＲ回路。1 and 2 are circuit diagrams of first and second embodiments of the present invention. 1...P channel FET, 2.3...N channel FET
ET, 4.11.12...AND circuit, 5...Input terminal, 6...Output terminal, 7...Control terminal, 8...
High threshold inverter, 9...Low threshold inverter, 10...Inverter, 13...OR circuit.

Claims (1)

【特許請求の範囲】[Claims] 複数種類の相異なる入力しきい値でそれぞれ動作する複
数の入力回路と、これら入力回路のうちの１つの出力を
外部からの制御信号により選択する制御回路とを備える
ことを特徴とするＣＭＯＳ論理回路。A CMOS logic circuit comprising a plurality of input circuits that each operate with a plurality of different input thresholds, and a control circuit that selects the output of one of these input circuits in response to an external control signal. .
JP63050839A 1988-03-03 1988-03-03 Cmos logic circuit Pending JPH01225223A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63050839A JPH01225223A (en) 1988-03-03 1988-03-03 Cmos logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63050839A JPH01225223A (en) 1988-03-03 1988-03-03 Cmos logic circuit

Publications (1)

Publication Number Publication Date
JPH01225223A true JPH01225223A (en) 1989-09-08

Family

ID=12869911

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63050839A Pending JPH01225223A (en) 1988-03-03 1988-03-03 Cmos logic circuit

Country Status (1)

Country Link
JP (1) JPH01225223A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04207310A (en) * 1990-11-30 1992-07-29 Hitachi Ltd Monostable multivibrator

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04207310A (en) * 1990-11-30 1992-07-29 Hitachi Ltd Monostable multivibrator

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