JPH0457250B2 - - Google Patents

Description

[Detailed description of the invention]

[Industrial Field of Application] The present invention relates to a tri-level input buffer circuit made of CMOS and capable of recognizing three different input logic states. The input buffer circuit that recognizes these three different input logic states usually has a built-in integrated circuit filter.
It is used to test the main internal circuit functions and characteristics in CODECs, etc. This tri-level input buffer is capable of generating several control signals for testing various functions and characteristics of the internal circuitry through three different voltage levels. [Prior Art] FIG. 3 shows a circuit diagram of an example of a conventional tri-level input buffer circuit. In the figure, 10 is the fourth
The inverter shown in FIG. 4a, the 2-input NOR circuit 11 shown in FIG. 4b, and the inverter 12 shown in FIG. 4c. Input terminal 1 has 2 inputs
The output of the inverter 12 is connected to the 2-input NOR 11 and the output terminal 3, and the output of the 2-input NOR 11 is connected to the output terminal 2. Before explaining the operation of this circuit, 2 in Fig. 4c.
The power inverter will be explained. In the figure,
V _DD is a positive supply voltage higher than the ground (GND) level, V _SS is a negative supply voltage lower than the GND level, and the P-channel MOS transistor (hereinafter referred to as
This is a CMOS inverter composed of an N-channel MOS transistor (hereinafter abbreviated as NMOS) 21 and an N-channel MOS transistor (hereinafter abbreviated as NMOS) 22. Note that the inverter 10 is connected to the power supply V _SS in FIG. 4c as shown in FIG. 4a.
corresponds to the ground level. these
By setting the ratio (W/L) of the gate width (W) and gate length (L) of each of PMOS21 and NMOS22 to an appropriate value, for example, the W/L of NMOS can be made larger than the W/L of PMOS. As a result, as shown in the inverter input/output characteristic diagram of FIG. 5, the output of the inverter can be inverted when the input voltage is between the GND level and the V _SS level. In addition, the 2-input NOR circuit 12 includes two PMOSs 23, 24 and two NMOSs 2, as shown in FIG. 4b.
It consists of 5,26. Next, the operation of the conventional circuit shown in FIG. 3 will be explained. When voltage V _DD (“1” level) is input from input terminal 1, the output of inverter 12 is voltage V _SS (“−
1” level), and the output of 2-input NOR11 is
GND (“0” level), and therefore the output of the inverter 10 becomes V _DD . Also, when input terminal 1 is GND, the output of inverter 12 is V _SS , 2
The output of input NOR11 will be V _DD and therefore,
The output of the inverter 10 becomes GND. Next, when input terminal 1 is V _SS , the output of inverter 12 is
V _DD , the output of the 2-input NOR 11 becomes GND, and therefore the output of the inverter 10 becomes V _DD .
The psychological value table for the above logic is shown in Table 1.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to eliminate such drawbacks and provide a tri-level input buffer circuit that consumes less power and has a large drive capacity. [Configuration of the Invention] The configuration of the input buffer circuit of the present invention includes a first logic circuit to which an input signal is connected and operates with a single power supply, and a first logic circuit to which the input signal is connected and operates with two positive and negative power supplies and has a positive and negative logic output. and an inverter circuit that inverts the output of the second logic circuit and operates on the single power supply, and extracts outputs from the first logic circuit and the inverter circuit, respectively. , the ratio of the gate width to the gate length of the MOS transistor constituting the second logic circuit constitutes the inverter circuit.
It is characterized by having a ratio of gate width to gate length that is smaller than that of a MOS transistor. [Examples] Examples of the present invention will be described below with reference to the drawings. FIG. 1 is a circuit diagram of an embodiment of the present invention, and Table 2 is a truth table for the circuit of FIG.

[Table] This example uses the inverter and 2-input NOR shown in Fig. 4 a, b, and c.
Inverter 12 with a first input and two power sources
Connect input terminal 1 to , and connect the output of inverter 12 to the second input of 2-input NOR 11 and
0, the output of the 2-input NOR 11 is connected to the output terminal 2, and the output of the inverter 10 is connected to the output terminal 3. This inverter 12 also has the DC input/output characteristics shown in FIG. Next, the operation of the present invention will be explained. In the figure, input terminal 1 is V _DD (“1” level)
When , the output of the inverter 12 is V _SS (“-1” level), therefore the output of the inverter 10 is V _DD ,
Further, the output of the 2-input NOR 11 becomes GND (“0” level). Next, when the input terminal 1 is GND, the output of the inverter 12 is V _SS , therefore the output of the inverter 10 is V _DD , and the output of the 2-input NOR 11 is V _DD . Furthermore, when input terminal 1 is V _SS ,
The output of the inverter 12 is V _DD , so the output of the inverter 10 and the output of the 2-input NOR 11 are both GND. Therefore, the second truth table
As shown in the table, different combinations of binary output signals are output to output terminals 2 and 3, and the three input levels of input terminal 1 can be recognized. Since this embodiment is configured with CMOS, no direct current flows when input terminal 1 is at V _DD or V _SS , similar to the conventional circuit. However, input terminal 1
When GND is on, both PMOS and NMOS are in the ON state, so a current flows from DC current V _DD to V _SS . However, since the current of the MOS transistor is proportional to W/L, the PMOS and NMOS of inverter 12
By reducing the W/L of the NMOS, the DC current can be reduced and the drive capability of the inverter 10 can be increased. FIG. 2 is a circuit diagram of another embodiment of the invention, and Table 3 is a truth table for the circuit of FIG.

〔Effect of the invention〕

As described above in detail, the tri-level input buffer circuit of the present invention has low power consumption and
Moreover, there is an effect that a buffer with a large driving capacity can be constructed.

[Brief explanation of the drawing]

1 and 2 are circuit diagrams of the first and second embodiments of the present invention, FIG. 3 is a circuit diagram of an example of a conventional tri-level input buffer, and FIGS. 4a, b, and c are circuit diagrams of an inverter, FIG. 5 is a circuit diagram in which a 2-input NOR inverter and a 2-power inverter are configured in CMOS, and FIG. 5 is a DC input/output characteristic diagram of the inverter shown in FIG. 4c. In the figure, 1...input terminal, 2, 3...output terminal, 10...inverter, 11...2 inputs
NOR, 12...2 power supply inverter, 21,2
3, 24...PMOS, 22, 25, 26...
It is NMOS.

Claims (1)

[Claims] 1. The first one to which the input signal is connected and operates from a single power supply.
a second logic circuit to which the input signal is connected and operates on two positive and negative power supplies and has a positive and negative logic output; and an inverter that inverts the output of the second logic circuit and operates on the single power supply. a circuit, which extracts outputs from the first logic circuit and the inverter circuit, respectively;
An input buffer circuit characterized in that the ratio of the gate width to the gate length of the MOS transistors constituting the logic circuit is smaller than the ratio of the gate width to the gate length of the MOS transistors constituting the inverter circuit.