JPH0431630Y2 - - Google Patents

Description

[Detailed explanation of the idea]

[Industrial Application Field] This invention relates to a full adder circuit that aims to reduce the number of elements. [Prior Art] Conventionally, a static full adder circuit includes AND circuits 2, 4, 6, 8, OR circuits 10, 12, NOR circuits 14, 16, and inverters 18, 20, as shown in FIG. It is composed of a logic circuit, and has two inputs A, which are applied to input terminals 22 and 24.
B and a carry input C for carry applied to the input terminal 26, a carry output Q _c is taken out from the output terminal 28 and a full addition output Q _s is taken out from the output terminal 30. In this full adder circuit, the following relationship holds between inputs A and B, carry input C, and carry output Q _c : Q _c =A·B+(AB)·C (1). However, "・" is a logical product,
"+" represents a logical sum, and "" represents an exclusive logical sum.
Therefore, when inputs A and B are both at H (high) level, or when either input A or B is at H level and carry input C is at H level, this is converted to the state logic and the carry output Q _c is obtained. [Problem that the invention aims to solve] When such a full adder circuit is constructed with a CMOS circuit, for example, AND circuits 2, 4, 6, and 8 are composed of a combination of a NAND circuit and an inverter, so the NAND circuit is Since the circuit is composed of 4 elements and the inverter is composed of 2 elements, the entire circuit is composed of 28 elements, which has the disadvantage that the number of elements is large and the IC chip becomes large. Additionally, as the number of elements increases, when adding n bits, it takes time for the carry to go to the next bit, causing a delay in logic operation, which reduces the operating speed and limits the maximum frequency. become the cause. Therefore, the object of this invention is to provide a full adder circuit that reduces the number of elements and improves operating speed. [Means for solving the problem] As shown in FIG. 1, the full adder circuit of this invention has an AND circuit 36 and a first NOR circuit 38 that receive first and second input signals arranged in parallel. ,
a second circuit that receives the outputs of the AND circuit and the first NOR circuit and generates a NOR output of both;
A first exclusive OR circuit 34 includes a NOR circuit 40 and obtains an exclusive OR output of the first and second input signals, and a gate receives the output of the first exclusive OR circuit to provide a carry input. The output of the first NOR circuit of the first exclusive OR circuit is applied to the gate of a first n-channel transistor 42 to which the clock pulse is passed, and a second p-channel transistor 44 to which a clock pulse is applied. N-channel type third transistors 46 are connected in series, and a series circuit of these second and third transistors is connected between a power supply and an inverted clock pulse source, and the second and third transistors are connected in series. It is equipped with a gate circuit which takes out an output through a connection point, and a second exclusive OR circuit 54 which receives the output of the first exclusive OR circuit and the carry input and obtains an exclusive OR output of both these inputs. be. [Operation] In this way, the first and second exclusive
A full adder circuit is configured by an OR circuit, a switching element, and a gate circuit, and the first exclusive OR circuit receives the first and second input signals.
An AND circuit and a first NOR circuit are arranged in parallel,
A second NOR circuit receives the outputs of the AND circuit and the first NOR circuit and generates a NOR output of both, and is configured to obtain an exclusive OR output of the first and second input signals. The switching element is composed of an n-channel type first transistor that receives the output of the first exclusive OR circuit at its gate and passes the carry input, and
The gate circuit includes a second p-channel transistor to which a clock pulse is applied, and a first NOR of the first exclusive OR circuit to the gate.
A third n-channel transistor to which the output of the circuit is applied is connected in series, and a series circuit of the second and third transistors is connected between the power supply and the inverted clock pulse source, and the second and third transistors are connected in series. Since the output is taken out through the connection point of the transistor, the number of components is reduced, the chip size when configured with an IC can be reduced, and the operating speed can be increased. [Embodiment] FIG. 1 shows an embodiment of the full adder circuit of this invention. 2 to be added added to input terminals 31 and 32
Inputs A and B are the first exclusive OR circuit 3
Added to 4. Exclusive OR circuit 34
is composed of an AND circuit 36 and first and second NOR circuits 38 and 40, and generates an exclusive OR output of inputs A and B. The output of this exclusive OR circuit 34 is applied to the gate of an n-channel first transistor 42, which is a switching element. The transistor 42 is made conductive by the H (high level) output of the exclusive OR circuit 34, and constitutes a gate circuit that passes the carry input C for carry applied to the input terminal 33. In other words, , functions as an AND circuit that takes the logical product of the output of the exclusive OR circuit 34 and the carry input C. The carry input C that has passed through this transistor 42 is transferred to a p-channel type second transistor 44.
and the connection point of the n-channel type third transistor 46. The transistor 44 has
Supply voltage V _DD to the source through terminal 48, terminal 5
The transistor 46 also has an inverted clock pulse φ applied to its source through a terminal 51 from an inverted clock pulse source, and a NOR circuit 38 at its gate as a particular output of the exclusive OR circuit 34.
The output is added from. That is, the series circuit of transistors 44 and 46 is installed as a gate means, and constitutes a clock gate circuit that allows a signal to pass in response to a clock pulse φ. Therefore, transistor 44 receives clock pulse φ
, and the transistor 46 is turned on by the H output of the NOR circuit 38, but when the carry input C is present in the section where both the transistors 44 and 46 are in the cut-off state, A carry output Q _c based on the carry input C is taken out from the output terminal 52 . That is, the carry output Q _c is raised to the H level during the period in which the clock pulse φ is at the L (low) level, and when the inputs A and B are both at the H level, the transistor 4
2,46 becomes non-conductive, so the carry output Q _c
becomes H level. Further, when both inputs A and B are at H level and carry input C is at H level, transistor 46 is non-conductive, transistor 42 is conductive, carry input C is transmitted to carry output Q _c , and carry output Q _c is high. level. and,
When inputs A and B are both at the L level, the transistor 42 is non-conductive and the transistor 46 is conductive, so the carry output Q _c becomes the L level. The carry input C applied to the input terminal 33 and the output signal of the exclusive OR circuit 34 are applied to the second exclusive OR circuit 54. Like the exclusive OR circuit 34, the exclusive OR circuit 54 includes an AND circuit 56 and NOR circuits 58 and 60, and obtains the exclusive OR of the killer input C and the output of the exclusive OR circuit 34. Therefore, the logical output is taken out from the output terminal 62 as the full addition output _Qs . The operation of this full adder circuit corresponds to the clock pulse φ shown in a of FIG. 2, and when inputs A and B are applied as shown in b of FIG. 2, as shown in c of FIG. A full addition output Q _s is obtained, and c in Fig. 2 is obtained.
The part T shown in is the effective output. Table 1 shows the truth table of this full adder circuit.

[Effect of idea]

According to this invention, the number of constituent elements can be reduced, the chip size can be reduced when integrated into an IC, the operating speed can be increased, and the maximum drive frequency can be set high.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the full adder circuit of this invention, FIG. 2 is a timing chart showing the operation of the full adder circuit shown in FIG. 1, and FIGS.
The figure shows an example of the configuration of a full adder circuit, Figure 5 is a circuit diagram showing a specific example of the circuit configuration of the full adder circuit of this invention, and Figure 6 is a circuit diagram showing the configuration of a conventional full adder circuit. be. 34...first exclusive OR circuit, 36
...AND circuit, 38...First NOR circuit, 40
... second NOR circuit, 42 ... first transistor, 44 ... second transistor (gate circuit), 46 ... third transistor (gate circuit), 54 ... second exclusive OR circuit.

Claims (1)

[Claims for Utility Model Registration] An AND circuit and a first NOR circuit that receive first and second input signals are arranged in parallel, and in response to the outputs of the AND circuit and the first NOR circuit, the negative logic of both is provided. a first exclusive OR circuit comprising a second NOR circuit that generates a sum output and obtains an exclusive OR output of the first and second input signals; and a gate for the output of the first exclusive OR circuit. a first transistor of the n-channel type to which the clock pulse is applied at the gate thereof and a second transistor of the p-channel type to which the clock pulse is applied to the gate;
An n-channel type third transistor to which the output of the first NOR circuit of the exclusive OR circuit is applied is connected in series, and the series circuit of these second, third, and third transistors is connected to a power source and an inverted clock pulse source. a gate circuit that is connected between the gates and takes out an output through the connection point of the second and third transistors; and a gate circuit that receives the output of the first exclusive OR circuit and the carry input, and outputs an exclusive OR of both inputs. A full adder circuit comprising: a second exclusive OR circuit that obtains; and a full adder circuit.