JPS60114028A - Logical circuit - Google Patents

Logical circuit

Info

Publication number
JPS60114028A
JPS60114028A JP58221618A JP22161883A JPS60114028A JP S60114028 A JPS60114028 A JP S60114028A JP 58221618 A JP58221618 A JP 58221618A JP 22161883 A JP22161883 A JP 22161883A JP S60114028 A JPS60114028 A JP S60114028A
Authority
JP
Japan
Prior art keywords
circuit
channel
input terminal
input
transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP58221618A
Other languages
Japanese (ja)
Inventor
Kiminori Kanamori
金森　公則
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP58221618A priority Critical patent/JPS60114028A/en
Publication of JPS60114028A publication Critical patent/JPS60114028A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/02—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components
    • H03K19/08—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices
    • H03K19/094—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits using specified components using semiconductor devices using field-effect transistors
    • H03K19/09425—Multistate logic
    • H03K19/09429—Multistate logic one of the states being the high impedance or floating state

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Computing Systems (AREA)
  • General Engineering & Computer Science (AREA)
  • Mathematical Physics (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE:To realize a tri-state logical circuit constituted with less number of components by adopting the circuit that an output section of an NAND circuit is connected to the input electrode of the 1st and 2nd transistors (TRs), the 2nd input terminal is connected to the input electrode of the 3rd TR and the 1st and 2nd TRs have different conduction type. CONSTITUTION:Since an output of the NAND circuit 10 is logical level ''1'' independently of a signal at the input terminal 11 when the input terminal 12 is logical level ''0'', a P-channel MOSTR16 is turned off and an N-channel MOSTR19 is also turned off. When the input terminal 12 is at logical level 1 next, an N-channel MOSTR19 is turned on, the NAND circuit 10 acts like an inverter to a signal at the input terminal 11, and a signal in phase to that at the input terminal 11 is outputted from the output terminal 18. In an example of this execution, the number of components of the circuit is; four NAND circuits 10, one P-channel MOSTR and two N-channel MOSTRs, in total seven.

Description

【発明の詳細な説明】 （発明の技術分野） 本発明は相補型ＭＯ８論理回路（以降ＣＭＵＳと称す）
で３ステート出力會有する論理回路に関する− （従来技術） 集積回路の為機能化、高集積化が進むにつれ。[Detailed Description of the Invention] (Technical Field of the Invention) The present invention relates to a complementary MO8 logic circuit (hereinafter referred to as CMUS).
(Prior art) As integrated circuits become more functional and highly integrated.

回路設計を行う上で少ない素子数で構成すること理回路
である。入力電極１．２からそれぞれ人力される１ぎ号
はＮＡＮＤ回路４に人力されるとともに、入力電極ｌか
らの入力信号とインバーター３を介して入力される入力
電極２からの人力信号とはＮＯＲ回路５に人力される。It is a logical circuit that can be constructed with a small number of elements when designing a circuit. The input signals from the input electrodes 1 and 2 are input to the NAND circuit 4, and the input signal from the input electrode 1 and the input signal from the input electrode 2 input via the inverter 3 are connected to the NOR circuit. 5 is man-powered.

ＮＡＮＤ回路４の出力がＰチャンネルＭＯ８）ランジス
タロのゲートに加えられ、ＮＯＲ回路５の出力がＮチャ
ンネルＭＯ８）ランジスタフに入力され、出力は出力電
極８から取〕出される。トランジスタ６．７は電源端子
２へ２１間に直列接続されている・このような３ステー
ト出力を有する論理回路′ｌｋｍ成するのＫｉ＆低１２
ケ（インバータ＝２ケ、　ＮＡＮＩＪ回路：４り、ＮＯ
Ｒ回路：４ヶ、ＰチャンネルＭＯ８）ランジスタ：ｌヶ
、ＮチャンネルＭＯ８）ランラスタ：１ケ）のトランジ
スタ全必要とする・ （発明の目的） 不発明の目的は少い素子数で構成できる３ステ一ト論理
回路を得ることにある。The output of the NAND circuit 4 is applied to the gate of the P-channel MO8) transistor, the output of the NOR circuit 5 is input to the N-channel MO8) transistor, and the output is taken out from the output electrode 8. Transistor 6.7 is connected in series between power supply terminal 2 and 21. Ki & low 12 constitutes a logic circuit 'lkm with such a 3-state output.
(Inverter = 2 pcs, NANIJ circuit: 4 pcs, NO
R circuit: 4, P channel MO8) transistor: 1, N channel MO8) Run raster: 1) All transistors are required. The objective is to obtain a one-to-one logic circuit.

（発明の構成） 不発明によれば、第１および第２の入力端子と。(Structure of the invention) According to the invention, first and second input terminals.

これらの入力端子に入力端が接続されたＮＡＮＤ回路と
ご直列接続され−ｆｃ第１．第２．第３のトランジスタ
とを有し、第１および第２のトランジスタは互いに導電
型が異なっており、これら第１および第２のトランジス
タがＮＡＮＤ回路の出力全受け、第３のトランジスタが
第２の入力端子に加えられる入力１６号を受け、第１お
よび第２のトランジスタの接続点から出力が取力出され
る３ステ一ト論理回路ｔ−得る。These input terminals are connected in series with a NAND circuit whose input end is connected to -fc1. Second. The first and second transistors have different conductivity types, and the first and second transistors receive all the outputs of the NAND circuit, and the third transistor receives the second input. A three-state logic circuit t- is provided which receives an input number 16 applied to its terminal and outputs an output from a connection point between the first and second transistors.

（実施例） 次に１図面を参照して１本発明をより詳細に説明する。(Example) Next, the present invention will be explained in more detail with reference to the drawings.

第２図は本発明の一実施例によメーテート論理回路であ
る０人力喘子１１．１２はＮＡＮＩ）回路ｌＯに接続さ
れている。電源端子３０．３１間にｒｉＰチャンネル八
ｔへｓトランジスタ１６とＮチャンネルＭＯＳトランジ
スタ１７．１９とが直列接続されている。　ＮＡＮＩ）
ＩＣ！ｌ路１０路用０はＰチャンネルＭ（ＪＳトランジ
スタ１６．！ｌ：ＮチャンネルＭＵ８トランジスタ１７
とに加えられ、入力端子１２に加わる１６号がＮチャン
ネル八４０Ｓ）ランジスタ１９にノ用見られている。Ｐ
ナヤン不ルＭＯＳトランジスタ１６とＮチャンネルへ４
（ＪＳ）ランジスタ１７との接続点に出力端子１８かａ
＋絖されている。FIG. 2 shows that in accordance with one embodiment of the present invention, a metered logic circuit 11.12 is connected to a NANI) circuit 10. An s transistor 16 and an N channel MOS transistor 17, 19 are connected in series to the riP channel 8t between power supply terminals 30, 31. NANI)
IC! l path 10 path 0 is P channel M (JS transistor 16.! l: N channel MU8 transistor 17
No. 16, which is added to the input terminal 12, is applied to the N-channel transistor 19 (840S). P
Nayan MOS transistor 16 and 4 to N channel
(JS) Output terminal 18 or a at the connection point with transistor 17
+ It is threaded.

次に、動作について−ｚｔｉｅする。入力端子１２がｉ
＋〜理レベしＩｌ　ＯＮ　、、、ときＮＡＮＬ１回路ｌ
Ｏの出力は入力端子１１１の１ｄ号に無関係に１ｉｕｉ
ｉ埋レベル６１′″であるため、ＰチャンネルＭＵＳト
ランジスタ１６はＵｌｉ’　Ｆ状悪に６．０．　Ｎチャ
ンネルＭＯ８トランジスタ１９もＯＦＦ状態にある。従
って、出力端子１８はハイインピーダンスとなる６次に
入力端子１２が調理レベル＠１″のと＠は、Ｎチャンネ
ルＭＯ８）ラン、ジスタ１９はＯＮ状態にあり、ＮＡＮ
Ｉ）回路１０は入力端子１１の信号に対してインバータ
ーとして動作し、出力端子１８は入力端子１１と同相匿
号が出力される。Next, let's discuss the operation. Input terminal 12 is i
＋〜When leveling Il ON ,,, NANL1 circuit l
The output of O is 1iui regardless of the 1d number of the input terminal 111.
Since the i buried level is 61''', the P channel MUS transistor 16 is in the Uli' F state of 6.0. The N channel MO8 transistor 19 is also in the OFF state. When input terminal 12 is at cooking level @1'', @ is N channel MO8) run, register 19 is in ON state, and NAN
I) The circuit 10 operates as an inverter for the signal at the input terminal 11, and the output terminal 18 outputs a code in the same mode as the input terminal 11.

不実施例によれば回路の構成素子数は、ＮＡＮＤ回路１
０に４個、ＰチャンネルＭＯＳトランジスタ１個、Ｎチ
ャンネルＭ（ＪＳ）ランラスタ２個の合計７個のトラン
ジスタで可能となる。According to non-embodiments, the number of circuit elements is 1 NAND circuit.
This is possible with a total of seven transistors: four for 0, one P-channel MOS transistor, and two N-channel M (JS) run raster transistors.

したがって不発明による回ｗ！ヲ採用することにより大
幅な素子数の低減となり高集積化を可能にするものであ
る。Therefore, times due to non-invention lol! By adopting this, the number of elements can be significantly reduced, making it possible to achieve high integration.

【図面の簡単な説明】[Brief explanation of drawings]

第１図は従来の３ステー）　ＣＭＯ８論理回路を示す回
路図、第２図は本発明の一実施例による３ステ一トＣＭ
Ｏ８論理回路を示す回路図である。 １．２，１１．１２・・・・・・入力端子％　２０，２
１゜３０．３１・・・・・・電源端子、３・・・・・・
インバーター。 ４．１０・・・・・・ＮＡＮＩ）回路、５・・・・・・
ＮＯＩも回路、６゜１６・・・・・・ＰチャンネルＭＯ
８）ランジスタ、７゜１７．１９・・・・・・Ｎチャン
ネルＭ（ＪＳ　トランジスタ。 ８．１８・・・・・・出力端子。 餞Ａ＊３！＋−ｆｆｉ”　町ｊ、　’、Ｆ：’ｌ’ｔニ
アゝ）第　１　図 第Ｚ区Figure 1 is a circuit diagram showing a conventional 3-stage CMO8 logic circuit, and Figure 2 is a 3-stage CM according to an embodiment of the present invention.
FIG. 3 is a circuit diagram showing an O8 logic circuit. 1.2, 11.12...Input terminal% 20,2
1゜30.31...Power terminal, 3...
inverter. 4.10...NANI) circuit, 5...
NOI is also a circuit, 6゜16...P channel MO
8) Transistor, 7゜17.19...N channel M (JS transistor. 8.18... Output terminal. 'l't Nearゝ) Figure 1 Section Z

Claims (1)

【特許請求の範囲】[Claims] 第１および第２の入力端子と、該第１および第２の入力
端子にそれぞれ入力部が接続されたＮＡＮＤ回路と、電
源端子間に直列接続された第１．第２および第３のトラ
ンジスタと、第１および第２のトランジスタの接続点に
接続された出力端子と全備え、前記Ｎ＆ＮＤ回路の出力
部は前記第１および第２のトランジスタの人力電極に接
続され、前記第２の入力端子は前記第３のトランジスタ
の人力電極に接続され、前記第１と第２のトランジスタ
は互いに導電型が異なることを特徴とする論理回路。A NAND circuit connected in series between first and second input terminals, a NAND circuit whose input section is connected to the first and second input terminals, and a power supply terminal. a second and a third transistor, and an output terminal connected to the connection point of the first and second transistors, the output part of the N&ND circuit being connected to the human power electrode of the first and second transistors; , wherein the second input terminal is connected to a human electrode of the third transistor, and the first and second transistors have different conductivity types.
JP58221618A 1983-11-25 1983-11-25 Logical circuit Pending JPS60114028A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP58221618A JPS60114028A (en) 1983-11-25 1983-11-25 Logical circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP58221618A JPS60114028A (en) 1983-11-25 1983-11-25 Logical circuit

Publications (1)

Publication Number Publication Date
JPS60114028A true JPS60114028A (en) 1985-06-20

Family

ID=16769573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP58221618A Pending JPS60114028A (en) 1983-11-25 1983-11-25 Logical circuit

Country Status (1)

Country Link
JP (1) JPS60114028A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179117A (en) * 1988-12-29 1990-07-12 Nec Corp Tri-state buffer circuit
KR101049705B1 (en) * 2008-05-22 2011-07-15 엘피다 메모리 가부시키가이샤 Signal output circuit and selector circuit using the same

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH02179117A (en) * 1988-12-29 1990-07-12 Nec Corp Tri-state buffer circuit
KR101049705B1 (en) * 2008-05-22 2011-07-15 엘피다 메모리 가부시키가이샤 Signal output circuit and selector circuit using the same

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