JPH02205110A - Flip-flop circuit device - Google Patents

Abstract

PURPOSE:To reduce the number of elements by providing a P-channel MOS transistor which fixes the state of a bidirectional transfer gate circuit at the time of setting as setting an FF circuit device without having a set function as a base, and adding a set circuit at a master side FF circuit. CONSTITUTION:A CMOS type FF circuit device is provided with the P-channel MOS transistor 5 which sets a source voltage terminal VDD as the source in a master side FF circuit 30 in which a set circuit is provided, and is comprised of a slave side FF circuit 31 without having the set circuit. The bidirectional transfer gate circuits 1 and 4 are turned off, and the bidirectional transfer gate circuits 2 and 3 are turned on. The master side FF circuit 30 is set at a holding state, and the P-channel MOS transistor 5 which inputs the inversion signal of a set signal is turned on, therefore, the output Q of the FF circuit device is held at the high level, which enables the FF circuit device to be set. In such a way, the number of elements can be reduced, and the reduction of an LSI chip can be realized.

Description

Detailed Description of the Invention (Field of Industrial Application) The present invention is applicable to flip-flop (hereinafter abbreviated as FF) circuit devices, particularly shift register circuit devices and synchronous frequency divider circuit devices often used in integrated circuit devices. The present invention relates to an FF circuit device used in a set circuit.

(Prior Art) FIG. 2 shows a conventional shift register circuit. Second
In the figure, 16 and 17 are inverter circuits, and 20 is an FF circuit device with a set. Also, Figure 3 shows the conventional commercial
An O5 type FF circuit device is shown.

In FIG. 3, numerals 4 to 4 are bidirectional transfer gate circuits;
11.12.18.19 is an inverter circuit, 30 is a master side FF circuit, 31 is a slave side FF circuit, 41゜42
is a NOR circuit.

Next, the operation of the above conventional example will be explained. When the set FF circuit device 20 shown in FIG. 2 is configured with a CMO8 type FF circuit device, as shown in FIG. It can now be set regardless of the state of the forward transfer gate circuit or 4.

Input set signal to both mask side and slave sideN
It has OR circuits 41 and 42, and sets the output Q of the FF circuit device to a high level in an initial state.

(Problem to be Solved by the Invention) However, since the conventional CMO8 type FF circuit device described above has logic circuits for setting both the mask side and the slave side, the set circuit can be simplified and the number of elements can be reduced. It is not suitable for measuring. In addition, the scale of custom LSIs for CMO8 type integrated circuit devices is increasing, and in particular, the density of FF circuit devices, which are the basic circuits often used in shift register circuit devices and synchronous frequency divider circuit devices, is increasing. There are problems such as not being suitable for standardization.

An object of the present invention is to solve the above-mentioned conventional problems and provide an FF circuit device that can be increased in density.

(Means for Solving the Problems) In order to achieve the above object, the present invention uses a P-channel MOS transistor that fixes the state of a bidirectional transfer gate circuit when it is set, based on an FF circuit device that does not have a set function. In addition, a set circuit is added to the mask side FF circuit.

(Function) Therefore, according to the present invention, the bidirectional transfer gate circuit of the data input section of the FF circuit device without a set function is turned off at the time of setting, and the feedback loop of the master side FF circuit is turned on at the same time. , the data on the mask side is forcibly held at a high level by a P-channel MOS transistor which receives an inverted signal of the set signal.

At this time, since the data on the mask side is transferred as is to the slave side, the FF circuit device can be set.

(Embodiment) FIG. 1 shows a schematic configuration of a CMOS type FF circuit device according to an embodiment of the present invention. In FIG. 1, numerals 4 to 4 are bidirectional transfer gate circuits, 5 is a P-channel MOS transistor, 6 is a NOR circuit, 10 to 15 are inverter circuits, 30 is a mask side FF circuit, and 31 is a slave side FF circuit.

Next, the operation of the above embodiment will be explained. In the above embodiment, the CMO5 type FF circuit device has a P-channel MOS transistor 5 whose source is the power supply voltage terminal (vDl) in the master side FF circuit 30 with a set circuit, and a slave side FF circuit without a set circuit. 31. When the set signal is at a high level, the NOR circuit 6 that receives the control clock signal and the set signal turns off the bidirectional transfer gate circuits 1 and 4, and turns on the bidirectional transfer gate circuits 2 and 3. do. At this time, the master side FF circuit 30 is in a hold state, and the P-channel MOS transistor 5, which inputs the inverted signal of the set signal, is turned on, so that the FF circuit device output Q becomes high level. Here, when the initial value is low level, the N-channel MOS transistor of the inverter circuit 11 is on, so the P-channel MOS transistor 5 has a sufficiently large driving capacity and inputs a voltage lower than the switching voltage of the inverter circuit 10. do. At this time, an instantaneous current flows, but the hold loop immediately operates, so there is no effect on the device.

(Effects of the Invention) As is clear from the above embodiments, the present invention can reduce the number of MOS transistors per FF circuit by three compared to the conventional circuit. Therefore, when applied to a multistage shift register circuit device or a synchronous frequency divider circuit device, the number of elements can be significantly reduced, which has the effect of downsizing the LSI chip.

4. Brief explanation of the drawings `` □Figure 1 is a circuit diagram of a CMOg type F'F circuit device according to an embodiment of the present invention.
FIG. 2 is a conventional shift register circuit diagram, and FIG. 3 is a circuit diagram of a conventional σMO8 type FF circuit.

1.2.3.4 ... Bidirectional transfer gate 5 circuit, 5
...P-channel MOS transistor, 6,4
1.42...NC1 circuit, 10 to 19...Inverter circuit, 20...FF circuit device with set, 30.
...Master side FF circuit, 31...Slave side pp'1
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Claims (1)

[Claims] A flip-flop circuit using multiple bidirectional transfer gate circuits, which has a P-channel MOS transistor that inputs an inverted signal of a set signal at the coupling part between the mutual bidirectional transfer gate circuits, and a control clock signal is set. What is claimed is: 1. A flip-flop circuit device characterized by having a configuration for setting a bidirectional transfer gate circuit to a specific state when the flip-flop circuit is in a specific state.