JP2527199Y2 - IC test mode setting circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION INDUSTRIAL APPLICATIONS The present invention is provided in an IC (integrated circuit), and when testing the IC circuit, according to a voltage value externally applied to a predetermined terminal pin. The present invention relates to a test mode setting circuit for setting a test mode.

2. Description of the Related Art In general, ICs are provided with terminal pins for testing.
When a certain voltage is applied to this pin, a test mode is set.
FIG. 6 shows a conventional example of such a test mode setting circuit. In the figure, first and second inverters (21) and (22) having different thresholds are commonly connected to a terminal pin (20). A decoder circuit (23) decodes the outputs (a) and (b) of the inverters (21) and (22) to set a mode.

Now, when a voltage of 0 volt is applied to the terminal pin (20), [a, b] becomes [11] as shown in FIG. 7, but in this case, the decoder circuit (23) operates in the test mode. No, set the normal operation mode. Then if half of V _DD / 2 of the power supply voltage V _DD applied usually is applied to the terminal pin (20) includes a first inverter (21) is operated, the second inverter (22) and inoperative Output [a, b] is [01]
And the test mode I is set. Terminal pins (20)
When V _DD is applied to the first and second inverters (21) and (2)
2) operates together, and the output [a, b] becomes [00]. In this case, test mode II is set. However, the threshold voltages VT ₁ and VT _{2 of} the first and second inverters (21) and (22)
_{Are in} a relationship of VT ₁ ≦ V _DD / 2 <VT ₂ ≦ V _DD .

Problems to be Solved by the Invention In the above conventional example, [a, b] can be taken only in three cases of [00], [01], and [11]. Among them, [11] is a normal operation mode, so that only two test modes can be realized. On the other hand, as for the test function, it is desirable to have more functions, so it is conceivable to increase the number of test terminal pins in order to realize this. Therefore, it is not preferable to provide a large number of terminal pins, as well as to reduce the functions of the application by sacrificing the original number of terminal pins.

The present invention has been made in view of such a point,
An object of the present invention is to provide a test mode setting circuit for an IC designed to increase the number of test modes without increasing the number of test terminal pins.

Means for Solving the Problems The test mode setting circuit of the present invention which achieves the above object has a first mode having a threshold VT ₁ lower than 1/2 of the power supply voltage V _DD .
A threshold circuit, a second threshold circuit with said threshold value VT ₁ higher than V _DD lower than a threshold value VT _2, a third threshold circuit having a high threshold VT ₃ from V _DD And a decoder circuit for decoding the outputs of the first, second, and third threshold circuits are formed in an IC chip, and the first, second, and third threshold circuits are shared by terminal pins. And the third threshold circuit has a voltage conversion circuit for dividing the input voltage of the terminal pin.

Operation According to such a configuration, four modes can be obtained by combining the outputs of the three threshold circuits. For example, even if one of the modes is set to the normal mode, the three modes are used as the test mode. Because it is possible, the range of the test function is expanded. When one or two modes are used as test modes, the remaining three or two modes can be used as normal modes.

Embodiment In FIG. 1 embodying the present invention, (2) is a first inverter constituting a _first threshold circuit (SC ₁ ), the input terminal of which is connected to a terminal pin (1). . This first inverter (2) inverts at V _DD / 2. On the output side of the first inverter (2) is a second inverter (3)
Are connected, and the output is supplied to a decoder circuit (9).

(4) is a third inverter whose input terminal is connected to the terminal pin (1), and the inverter (4) is inverted at _VDD . The output is provided to the decoder circuit (9) via the fourth inverter (5). The third inverter (4) forms a _second threshold circuit (SC ₂ ).

Next, (6) is a voltage conversion circuit connected to the terminal pin (1), the output path (10) of the third inverter (4), and the output path (11) of the fourth inverter (5), respectively. The output terminal of this voltage conversion circuit (6) is connected to a fifth inverter (7) which inverts at V _DD / 2, and the fifth inverter (7) is connected to a decoder circuit (9) via a sixth inverter (8). It is connected. The voltage conversion circuit (6) and the fifth inverter (7) constitute a _third threshold circuit (SC3). The voltage conversion circuit (6) has a P-channel MOS type first transistor (Q ₁ ) having a gate connected to the output path (10), and an N-channel MOS type transistor having a gate connected to the terminal pin (1). An N-channel MOS type third transistor (Q ₃ ) having two transistors (Q ₂ ) and a gate connected to the output path (11); and an N-channel MOS type transistor having a gate connected to the output path (10). It is configured by connecting four transistors (Q ₄ ) as shown in the figure.
Taken out of the point.

When the first, second, and third transistors (Q ₁ ), (Q ₂ ), and (Q ₃ ) are all turned on, their conduction resistances are changed to R ₁ , R ₂ ,
If R ₃ is used, an equivalent circuit as shown in FIG. 2 is obtained. At this time, if the voltage applied to the terminal pin (1) is plotted on the horizontal axis and the output voltage at the point (a) is plotted on the vertical axis, the characteristics are as shown in FIG. Here, when V _DD is given as the input voltage,
(A) The voltage at the point is designed to be lower than V _DD / 2. The threshold values VT ₁ , VT ₂ , VT ₃ of the first, second, and third threshold circuits (SC ₁ ), (SC ₂ ), (SC ₃ ) are VT ₁ <V
_DD / 2 <VT ₂ <V _DD <VT ₃

Next, the operation will be described. First, when 0 volt is externally applied to the terminal pin (1), the first inverter (2), the third inverter (4), and the fifth inverter (7) do not operate, and the output is "1". " Therefore, these outputs are output to the second, fourth and sixth inverters (3)
(5) After being set to "0" in (8), they are input to the decoder circuit (9). At this time, the decoder circuit (9)
Determines that the operation mode is the normal operation mode, and sets the mode.

Next, when V _DD / 2 is input to the terminal pin (1), the first inverter (2) is turned on and its output is set to “0”, so that it is input to the decoder circuit (9) ( a) becomes "1". Since the third and fifth inverters (4) and (7) do not change and remain as they are, (b) and (c) are "0" and "0". At this time, the decoder circuit (9) operates in the test mode I.
Set.

Next, when _VDD is applied to the terminal pin (1), the first
Inverter (2) and third inverter (4) are both ON
However, since the fifth inverter (7) remains unchanged,
(A), (b), and (c) become "1", "1", and "0", and the decoder circuit (9) sets the test mode II.

When V _DD + α higher than V _DD is applied to the terminal pin (1), in this case, the first, third, and fifth inverters (2) and (4)
Since (5) is turned ON, (a), (b), and (c) are "1", "1", and "1", and the decoder circuit is in the test mode III.
Set.

Here, the operation of the voltage conversion circuit (6) will be described in detail. First, in the normal operation mode in which 0 volt is applied to the terminal pin (1), the output path (10) becomes "1". Therefore, the fourth transistor (Q ₄ ) is turned on and the point (a) is at a low level, so that the fifth inverter (7) does not operate. The same applies to the test mode I in which V _DD / 2 is applied to the terminal pin (1). Since in the case of the test mode II the V _DD is applied to the terminal pin (1) output channel (10) becomes "0", the fourth transistor (Q ₄₎ becomes OFF, the first transistor (Q ₁₎ Turns ON. At this time, the third transistor (Q ₃ ) to which “1” of the output path (11) is given turns ON,
The second transistor (Q ₂ ) to which V _DD is applied is also turned on, and the state of the equivalent circuit shown in FIG. 2 is obtained. In this case, the point (A) is V _DD / 2 Since it is set lower, the fifth inverter (7) is inactive. V _DD
When + α is given, the first, second, and third transistors (Q ₁ ) (Q ₂ ) (Q ₃ ) are turned on, and the fourth transistor (Q ₄ ) is turned on.
OFF mode is the same as test mode II,
(A) Since the potential at the point becomes V _DD / 2 or more, the fifth inverter (7) is turned on.

The test voltage applied to the terminal pin (1) described above and the first, second, and third threshold circuits (SC ₁ ) (SC ₂ )
FIG. 4 shows the relationship between the outputs (a), (b), and (c) of (SC ₃ ) and the modes in an easily understandable manner. Here, since there are three test modes, more test functions can be achieved. For example, when the number of test modes is small as in the conventional example in FIG. 6, when the block (C) is tested by the circuit in the IC chip shown in FIG. 5, the block (A) as shown in FIG. Inevitably, a technique of indirectly testing the block (C) while operating is used, and the amount of operation at the time of testing increases. However, when the number of test modes is large as in this embodiment, FIG. As shown in (i), block (A), block (B), and block (C) can be tested independently. That is, for example, when testing the block (C), the other blocks (A) and (B) are unnecessary and do not need to be operated. Therefore, this also has the advantage of reducing test time.

However, it is also possible to select not to use all the test modes I, II, and III for the test, but to use the test modes I and II for the normal mode and use only the test mode III as the test mode. When used in this way, applications in the normal mode increase.

It has become possible to use high test voltage V _DD + alpha than V _DD in the above embodiments but would widen the voltage range of the test mode, in this case, V _DD from the outside
The supply of + α can be easily prepared.

Effect of the present invention As described above, according to the present invention, without increasing the number of terminal pins, the types of test modes can be increased, and the efficiency of the test operation can be improved, and multi-functionality can be achieved. Become.

In the present invention, since the threshold value of the third threshold circuit is set to a voltage value (V _DD + α) exceeding the power supply voltage V _DD , the voltage range for forming the test mode is limited. Since the margin for the threshold value of each mode can be widened accordingly, a malfunction due to a variation in circuit components does not occur.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing a test mode setting circuit of an IC embodying the present invention, FIG. 2 is a partial equivalent circuit diagram, FIG. 3 is a characteristic diagram of FIG. 2, and FIG. Explanatory drawing of FIG.
The figure is a diagram for explaining the effect of the circuit of FIG. FIG. 6 is a circuit diagram of a conventional example, and FIG. 7 is an explanatory diagram thereof. (1) ... terminal pin, (9) ... decoder circuit, (S
C ₁ ): first threshold circuit, (SC ₂ ): second
Threshold circuit, (SC ₃ )... Third threshold circuit.

Claims (1)

(57) [Scope of request for utility model registration] 1. A first having a threshold value VT ₁ lower than half the power supply voltage V _DD and the threshold circuit, the second having the threshold VT ₁ higher than V lower than the _DD threshold VT ₂ a threshold circuit, a third threshold circuit having a high threshold VT ₃ than V _DD, the first, second, third decoder circuit and an IC chip for decoding the output of the threshold circuit And the first, second, and third threshold circuits are commonly connected to a terminal pin, and the third threshold circuit is configured to divide an input voltage of the terminal pin. Characterized by having a circuit
IC test mode setting circuit.