JPH05191239A - Multiplexer circuit - Google Patents

Abstract

PURPOSE:To attain a high speed operation of the circuit even when number of channels is increased. CONSTITUTION:The circuit is provided with a 1st parallel circuit comprising parallel connection of N(>=2) sets of series circuits each comprising n(>=2) sets of 1st conduction MOS transistors(TRs) TNi connected in series, with a 2nd parallel circuit comprising parallel connection of N(>=2) sets of series circuits each comprising n(>=2) sets of 1st conduction MOS transistors (TRs) TNi connected in series, and 1st and 2nd MOS TRs of 2nd conduction type whose sources are connected to a 1st power supply and whose gates and drains are cross-connected together. Each one terminal of the 1st and 2nd parallel circuits is connected to each drain of the 1st and 2nd MOS TRs, the other terminal connects to a 2nd power supply, the one terminal of the 1st and 2nd parallel circuits is used respectively as 1st and 2nd output terminals and a data signal is inputted to a gate of one TR of each series circuit of the 1st and 2nd parallel circuits, the inverse of the data signal is inputted to a gate of other TR of each series circuit and a selection control signal is inputted to a gate of the remaining TRs.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiplexer circuit constructed using CMOS devices.

[0002]

2. Description of the Related Art As shown in FIG. 8, a conventional 4-channel multiplexer has four 2-input AND gates 81, 82,
83, 84, a NOR gate 85, and an inverter 86, or four 2-input NAND gates 101, 102, 103, 104 as shown in FIG.
It is composed of one 4-input NAND gate 105. In FIGS. 8 and 10, X _i (i = 0, ... 3) represents a data signal, S _i (i = 0, ... 3) represents a selection control signal, and X _i when S _i is “1”. Is selectively output.

The multiplexer shown in FIG. 8 is represented by using a CMOS device as shown in FIG. In the 4-channel multiplexer shown in FIG. 9, four P-channel MOS transistors are connected in series, that is, in four stages, between the power supply _VDD and the output terminal OUT. Although the multiplexer shown in FIG. 8 has four channels, the number of P-channel MOS transistors connected in series increases as the number of channels increases.

When the multiplexer shown in FIG. 10 is similarly expressed by using a CMOS device (not shown), since the multiplexer has a 4-input NAND gate, four Ns are provided between the power supply and the output terminal. Channel M
This is a circuit in which OS transistors are connected in series, and the number of stages of N-channel MOS transistors connected in series increases in accordance with the number of channels.

[0005]

A multiplexer circuit constructed by using such a CMOS device operates faster as the ON resistance of the MOS transistor between the power supply and the output terminal is smaller. However, in the conventional multiplexer circuit, the number of MOS transistors corresponding to the number of channels is connected in series as described above, and therefore the ON resistance of the MOS transistors is connected in series. As a result, if the number of channels increases, the on-resistance of the entire circuit increases, which makes it difficult to operate at high speed. Further, in order to operate the conventional multiplexer circuit at high speed, the ON resistance of each MOS transistor must be reduced, and in order to reduce the ON resistance of the MOS transistor, the size of the MOS transistor (particularly the channel width) must be increased. Must. When the size of the MOS transistor is increased, there is a problem that the area occupied by the integrated circuit is increased and the parasitic capacitance is increased to increase the power consumption. The present invention has been made in view of the above circumstances, and an object of the present invention is to provide a multiplexer circuit that can perform high-speed operation even if the number of channels is increased without increasing the size of a MOS transistor.

[0006]

In the multiplexer circuit according to the present invention, a series circuit composed of n (≧ 2) first conductivity type MOS transistors connected in series is N (≧ 2).
A first parallel circuit connected in parallel, a second parallel circuit in which N series circuits composed of n first conductivity type MOS transistors connected in series are connected in parallel, and a source is A first MOS transistor of a second conductivity type connected to one power source and a drain connected to one end of the first parallel circuit; a source connected to the first power source and a drain connected to the second parallel circuit; A second MOS transistor of the second conductivity type connected to one end, the gate of the first MOS transistor is connected to the drain of the second MOS transistor, and the gate of the second MOS transistor is One MOS transistor of each series circuit connected to the drain of the first MOS transistor and the other ends of the first and second parallel circuits connected to a second power supply. A data signal is input to the gate of the series circuit, a selection control signal for selecting the data signal is input to the gates of the other MOS transistors of the series circuit, and one MOS transistor of each series circuit in the second parallel circuit is input. An inversion signal of the data signal is input to the gate, a selection control signal for selecting the inversion signal is input to the gates of the other MOS transistors of the series circuit, and each of the one ends of the first and second parallel circuits is input. It is characterized in that the first and second output terminals are used.

[0007]

According to the multiplexer circuit of the present invention thus constructed, the number of MOS transistors connected in series between the power supply and the output terminal is constant even if the number of channels is increased. Accordingly, high-speed operation can be performed even if the number of channels is increased without increasing the size of the transistor.

[0008]

FIG. 1 shows the configuration of a first embodiment of a multiplexer circuit according to the present invention. The multiplexer circuit of this embodiment has four channels and is composed of two P-channel MOS transistors TP1 and TP2 and 16 N-channel MOS transistors TNi (i = 1, ... 16). These 16 N-channel transistors TN
i (i = 1, ... 16) are 2 connected in series.
N-channel transistors TNi and TNi + 8 (i =
A first parallel circuit in which four sets of series circuits composed of 1, ... 4) are connected in parallel, and two N-channel transistors TNj, TNj + 8 (j = 5, ... 8) each connected in series. )
And a second parallel circuit in which four sets of serial circuits each of which is connected in parallel are formed.

P-channel transistors TP1 and TP2
_Has its source connected to the power supply V _{DD and} has a transistor TP
The drain of 1 is connected to one end of the first parallel circuit,
The drain of the transistor TP2 is connected to the second parallel circuit, and the other ends of the first and second parallel circuits are connected to the ground power supply. The gate of the transistor TP1 is connected to the drain of the transistor TP2, and the gate of the transistor TP2 is connected to the drain of the transistor TP1.

Transistor TN in the first parallel circuit
The data signal X _i-1 is added to the gate of i (i = 1, ... 4), and the selection control signal S _i-1 is added to the gate of the transistor TNi + 8 (i = 1, ... 4). .. Further, the transistors in the second parallel circuit TNi + 4 (i = 1, ... 4) to the gate of the additional inverted signal bar X _i-1 of the data signal X _i-1, the transistor TNi + 12 (i = The selection control signal S _{i- 1} is added to the gates of 1, ... 4). The multiplexer circuit includes a drain of the transistor TP1 and a connection node (output terminal Out1) of the first parallel circuit, an inverted output bar Q, a drain of the transistor TP2, and a second drain.
The normal output Q is output from the connection node (output terminal Out2) of the parallel circuit.

The operation of the above embodiment will be described with reference to FIG. Now, the data signals X ₀ , X ₁ , X ₂ , X ₃ shown in FIG.
And the selection control signals S ₀ , S ₁ , S ₂ , S ₃ are added to the multiplexer circuit shown in FIG. At timing t ₀ in FIG. 2, only the selection control signal S ₀ is “H”.
, And the because the other selection control signals S _1, S _2, S ₃ is "L", the transistor TN9, TN13 are turned on, the transistor TN10, TN11, TN12, TN
14, TN15, TN16 are off. Since the data signal X ₀ is "H" at this time, the transistor TN
1 is on and the transistor TN5 is off. Therefore, the output terminal Out2 and the ground terminal are disconnected from each other, but the output terminal Out1 and the ground terminal are in a conductive state via the on-resistances of the transistors TN1 and TN9. As a result, the output terminal Out1 goes to "L" level to turn on the transistor TP2, and the output terminal Out2 goes to "H" level to turn off the transistor TP1 and the output terminal Out1 goes to "L" level. The output terminal Out2 becomes "H" level. This state continues until the timing t ₁ when the selection control signal S ₀ becomes “L”. That is, the data signal X ₀ is selected and output from the node Out2.

At timing t ₁ , the selection control signal S ₁
Only "H" is set, so only the transistors TN10 and TN14 of the transistors TNi (i = 9, 1 ... 16) to which the selection control signal is added are turned on. At this time, the data signal X ₁ of the inverted signal bars X ₁ is because it is "H" transistor TN6 is turned on, the transistor TN2 is turned off. Therefore, the output terminal Out2 becomes "L" level, which turns on the transistor TP1 and sets the output terminal Out1 to "H" level. This state continues until the timing t ₂ when the selection control signal S ₁ becomes “L”,
The data signal X ₁ is selected and output from the output terminal Out2.

At timing t ₂ , the selection control signal S ₂
Only "H" becomes, and among the transistors to which the selection control signal is added, only the transistors TN11 and TN15 are turned on. Since the inverted signal bar X ₂ at this time the data signal X ₂ is "H", the transistor TN7 is turned on, the transistor TN3 is turned off. Therefore, the output terminal Out2 becomes "L" level, which turns on the transistor TP1 and sets the output terminal Out1 to "H" level. This state continues until timing t ₃ when the selection control signal S ₂ becomes “L”, and the data signal X ₂ is selected and output from the output terminal Out2.

Similarly, only the selection control signal S ₃ is "H".
Then, the data signal X ₃ is selected and the output terminal Out2
Is output from. As described above, the circuit shown in FIG. 1 has a multiplexer function, and the normal output signal Q is output from the output terminal Out2 and the inverted output signal bar Q is output from the node Out1. The circuit shown in FIG.
Although it is a channel multiplexer circuit, even if the number of channels increases, the number of series circuits composed of two N-channel transistors forming the first and second parallel circuits only increases, and the power supply and the output terminal The number of transistor stages between does not increase. As a result, even if the number of channels increases, the on-resistance of the transistor does not increase, and high-speed operation can be performed. Note that FIG. 7 shows a circuit diagram when the multiplexer circuit shown in FIG. 1 has eight channels.

Next, the configuration of the second embodiment of the multiplexer circuit according to the present invention is shown in FIG. The multiplexer circuit of this embodiment is the same as the multiplexer circuit of the first embodiment shown in FIG. It is one more. The data signal X _i (i = 0, ... 3) is selectively output by decoding the two types of selection control signals A and B.
In FIG. 3, transistors TN9, TN10, TN1
An inverted signal bar B of the selection control signal B is added to the gates of the transistors TN14, TN11, TN12, TN.
15, the selection control signal B is added to the gate of TN16,
Transistors TN17, TN19, TN21, TN23
An inverted signal bar A of the selection control signal A is added to the gate of the transistor TN18, TN20, TN22, TN.
The selection signal A is added to the gate of 24.

The operation of the second embodiment will be described with reference to FIG. Since the control signal bar A and the control signal bar B are “H” between the timings t ₀ and t _1, the transistor T
N9, TN17, TN13, TN21 turn on. As a result, the data signal X ₀ is selected and output from the output terminal Out2. Further, since the control signal A and the control signal bar B are "H" between the timings t ₁ and t ₂ , the transistors TN10, TN18, TN14, TN22 are turned on,
The data signal X ₁ is selected and output from the output terminal Out2. Further, since the control signal bar A and the control signal B are "H" between the timings t ₂ and t ₃ , the transistor T
N11, TN19, TN15 and TN23 are turned on, the data signal X ₂ is selected and output from the output terminal Out2. Further, since the control signals A and B are "H" between the timings t ₃ and t ₄ , the transistors TN12, TN20,
TN16, TN24 are turned on, the data signal X ₃ is output from the selected output terminal Out2.

The multiplexer circuit of the second embodiment can obtain the same effect as the multiplexer circuit of the first embodiment by using a small number of selection control signals. Next, FIG. 5 shows a first modification of the first embodiment of the present invention. The multiplexer circuit of this modified example is the multiplexer circuit of the first embodiment shown in FIG. 1 in which N-channel transistors TN51 and TN52 are newly provided for higher speed operation. And the transistor TN51
Is connected to the output terminal Out1, the source is connected to the ground power supply, and the gate is connected to the output terminal Out2.
The drain of the transistor TN52 is connected to the output terminal Out2.
, Its source is connected to the ground power supply, and its gate is connected to the output terminal Out1. By connecting in this way, the data signal X _{0 is} generated by the selection control signal S ₀ , for example.
Is selected, that is, the transistors TN1 and TN
When 9 is turned on at the same time and the output terminal Out1 becomes "L" level, the transistor TP2 is turned on and the output terminal O
ut2 goes to "H" level and the transistor T51 is turned on, so that the level of the output terminal Out1 is rapidly brought to "L" level.

As described above, the multiplexer circuit of the first modification can operate at a higher speed than the multiplexer circuit of the first embodiment. Next, the first of the present invention
FIG. 6 shows a second modified example of the above embodiment. The multiplexer circuit of this modification is the same as the multiplexer circuit of the first modification shown in FIG.
3, a TN 54 and an inverter 61 are newly provided.

The drain of the transistor TN53 is connected to the other end of the first parallel circuit and the source of the transistor TN51, and the source is connected to the ground power source. In addition, the transistor T54 is the second parallel circuit and the transistor TN.
52 is connected in parallel. And the transistor TN54
The control signal St is input to the gate of the transistor T
A signal bar St obtained by inverting the control signal St by the inverter 61 is input to the gate of N53.

In the multiplexer circuit of the second modification, when the control signal S _t is at "L" level, the transistor TN53 is turned on and the transistor TN54 is turned off, as shown in FIG.
The same operation as the multiplexer circuit shown in is performed. When the control signal St is at "H" level, the transistor TN53 is turned off and the transistor TN54 is turned on, whereby the output terminal Out1 is cut off from the ground power source and the output terminal Out2 becomes "L" level. As a result, the transistor TP1 is turned on, the output terminal Out1 becomes "H" level, and the transistor TN52 is turned on. Therefore, by setting the control signal St to the "L" level, the second
The multiplexer circuit of the modified example performs the same operation as the multiplexer circuit of the first modified example, and sets the control signal St to "H".
By setting the level, the output terminal Out1 can be set to the “L” level and the output terminal Out2 can be set to the “H” level. In this second modification, the transistor TN5
Even if the 1 and TN52 are removed, the same operation as in the second modification can be performed.

In the first and second embodiments and the first and second modified examples, the N-channel transistor is used for signal input. The P-channel transistor may be used for signal input by replacing the channel transistor with an N-channel transistor.

[0022]

According to the present invention, high-speed operation can be performed even if the number of channels is increased without increasing the size of the MOS transistor.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a configuration of a first embodiment of a multiplexer circuit according to the present invention.

FIG. 2 is a timing chart showing the operation of the first embodiment.

FIG. 3 is a circuit diagram showing a second embodiment of a multiplexer circuit according to the present invention.

FIG. 4 is a timing chart showing the operation of the second embodiment.

FIG. 5 is a circuit diagram showing a first modification of the first embodiment.

FIG. 6 is a circuit diagram showing a second modification of the first embodiment.

FIG. 7 is a circuit diagram when the number of channels of the multiplexer circuit of the first embodiment is eight.

FIG. 8 is a logic circuit diagram of a conventional multiplexer.

9 is a configuration circuit diagram of the multiplexer shown in FIG.

FIG. 10 is a logic circuit diagram of a conventional multiplexer.

[Explanation of symbols]

TPi (i = 1, 2) P-channel MOS transistor TNi (i = 1, ... 16) N-channel MOS transistor X _i (i = 0, 1 ... 3) Data signal S _i (i = 0, ... 3) Selection control signal

Claims (3)

[Claims] 1. A series circuit comprising n (≧ 2) first conductivity type MOS transistors connected in series is N (≧ 2).
A first parallel circuit connected in parallel, a second parallel circuit in which N series circuits composed of n first conductivity type MOS transistors connected in series are connected in parallel, and a source is A first MOS transistor of a second conductivity type connected to one power source and a drain connected to one end of the first parallel circuit; a source connected to the first power source and a drain connected to the second parallel circuit; A second MOS transistor of the second conductivity type connected to one end, the gate of the first MOS transistor is connected to the drain of the second MOS transistor, and the gate of the second MOS transistor is One MOS transistor of each series circuit connected to the drain of the first MOS transistor and the other ends of the first and second parallel circuits connected to a second power supply. A data signal is input to the gate of the series circuit, a selection control signal for selecting the data signal is input to the gates of the other MOS transistors of the series circuit, and one MOS transistor of each series circuit in the second parallel circuit is input. An inversion signal of the data signal is input to the gate, a selection control signal for selecting the inversion signal is input to the gates of the other MOS transistors of the series circuit, and each of the one ends of the first and second parallel circuits is input. A multiplexer circuit having first and second output terminals. 2. A first conductivity type first MOS transistor having a drain connected to the first output terminal, a source connected to the second power supply, and a gate connected to the second output terminal, and a drain. Is connected to the second output terminal, the source is connected to the second power supply, and the gate is connected to the first output terminal. A second MOS transistor of the first conductivity type is provided. The multiplexer circuit according to claim 1. 3. A third MOS transistor of a first conductivity type, which is connected in series between the other end of one of the first and second parallel circuits and a second power supply, Further comprising a fourth MOS transistor of the first conductivity type connected in parallel with the other parallel circuit, and inputting a control signal to the gate of one of the third and fourth MOS transistors, 3. The multiplexer circuit according to claim 1, wherein the inverted signal of the control signal is input to the gate of the other transistor.