JPH03179814A - Level shift circuit - Google Patents

Abstract

PURPOSE:To prevent malfunction by adding an N-channel MOS transistor(TR) to the level shift circuit, and making a latch output level set at a high level or a low level. CONSTITUTION:An N-channel MOS TR is added to the level shift circuit having a latch circuit 7, its drain is connected to the output terminal of a latch section 7, the source is connected to a ground terminal and the output signal of the latch section 7 is decreased to an L level by a signal applied to the gate. Even when noise is superimposed more or less onto a power terminal 12, the output signal of the level shift circuit is decreased to an L level to prevent malfunction.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit that converts a high-level voltage of an input signal to another voltage value, and particularly relates to a level shift circuit using a latch.

[Conventional technology]

FIG. 3 is an example of a circuit diagram showing a conventional level shift circuit. In Figure 3, 1 is input terminal 1.2 is input terminal 2
．． 3 is the 10th P-channel MOS transistor, 4 is the second
5 is a first N-channel MOS transistor, 6 is a second N-channel MOS transistor, and these MOS transistors 3 to 6 are P-channel MOS transistors.
This constitutes the latch section 7. Further, 8 is a buffer section formed by connecting two inverters in series, 9 is an internal terminal 1%, 10 is an internal terminal 2, and 11 is an output terminal.

Next, the operation of the circuit configured as described above will be explained. When the level of input terminal 1 is "H" and the level of input terminal 20 is "J, I+", transistors 4 and 5 are turned on, so =0■ is output to output terminal 11. When the level of input terminal 2 is "L" and the level of input terminal 2 is "H", transistors 3 and 6 are turned on, so 11
2V0 is output to the output terminal of. However, when the input terminal 1 and input terminal 20 levels both become "L"', the internal terminal 1 and the internal terminal 20 level become a high impedance state, and each transistor 3 to 6 returns to its previous state due to the charge stored inside it. However, if noise enters from the power supply terminal 12, the charge may move even with a slight change in potential, and the state of the latch section 1 may be reversed, causing malfunction.

In addition, in the case of a circuit configured as shown in Figure 3, input terminal 1
When signals with opposite phases are input to input terminal 2, a signal that is in phase with the signal input to input terminal 2 is output to output terminal 11.What are the rise time and fall time of this output signal? There's not much of a difference, and one isn't particularly faster than the other.

[Problem to be solved by the invention]

As mentioned above, in a conventional level shift circuit having a latch circuit, the internal terminals 9 and 10 may enter a high impedance state depending on the state of the input signal.
If noise enters from the power supply terminal, etc., the latch section may be inverted, potentially causing malfunction. Furthermore, regarding the rise time and fall time of the output signal of the conventional level shift circuit, one of them is not particularly shorter than the other.

[Means to solve the problem]

In order to solve this problem, the level shift circuit of the present invention adds a new N-channel MOS transistor to determine the output level of the latch section at a high level or a low level to prevent malfunction.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram of an embodiment of the present invention. This level shift circuit differs from the conventional circuit shown in FIG. 2 in that 14 N-channel MOS transistors are added. . These 14 N-channel MOS transistors A have their drains connected to internal terminal 1 of 9 which is the output terminal of the latch section, gates connected to internal terminal 2 of 10 of the latch section, and sources connected to ground terminal 13 of the latch section. ing.

Next, the circuit operation of this embodiment will be explained. When input terminal 1 of 1 is “H” and input terminal 2 of 2 is “L”,
Since transistors 4 and 5 are on and transistors 3 and 6 are off, the output terminal of 11 becomes =Ov. Also, when input terminal 1 of 1 is "L" and input terminal 2 of 2 is "H", transistors 4 and 5 are off and transistors 3 and 6 are on, so output terminal 11 is :■.

Here, when input terminal 1 of 1 and input terminal 2 of 2 both become "L", internal terminal 1 of 9 and internal terminal 2 of 10 try to enter a high impedance state, but before that, the internal terminal 1 of 14 Since the N-channel MOS transistor is turned on, the internal terminal 1 of 9 becomes =0■. In this state, the latch section will not be reversed even by some noise on the power supply terminal. Therefore, as described above, the present invention can prevent malfunctions.

Further, when signals having mutually opposite phases are inputted to the input terminal 1 of 1 and the input terminal 2 of 2, the fall time of the output signal in the circuit according to the embodiment of the present invention becomes faster than the fall time. This is the second N of 6 at the falling edge of the signal.
This is because the 14 N-channel MOS transistors are turned on at the same time that the channel MOS transistor is turned off, so that the discharge speeds up.

FIG. 2 is a circuit diagram of another embodiment of the present invention.

The level shift circuit shown in FIG. 2 is a circuit diagram of an embodiment of the present invention, which is the circuit shown in FIG. and the gate thereof is connected to the output terminal of the 16 voltage detection circuits. The operation of the circuit is the same as in the first embodiment, but since 15 N-channel MOS transistors are connected, if the voltage detection circuit is configured to detect when the power supply voltage becomes lower than a certain level, At that time, the output signal of the latch section is “L +
Since the voltage is fixed at 1, it is possible to prevent malfunctions that may occur when the power supply voltage becomes low.

〔Effect of the invention〕

As explained above, the present invention adds an N-channel MOS transistor, connects its drain to the output terminal of the latch section, connects its source to the ground terminal, and controls the output signal of the latch section by the signal applied to the gate. By lowering the level to "L", the output signal of the level shift circuit becomes "L" even if there is some noise on the power supply terminal, which has the effect of preventing malfunctions.

Further, the output waveform of the level shift circuit of the present invention has the effect that the fall time can be made shorter than the rise time.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram of one embodiment of the present invention, FIG. 2 is a circuit diagram of another embodiment of the invention, and FIG. 3 is a circuit diagram showing a conventional technique. l...Input terminal 1.2...Input terminal 2
．． 3...First P channel MOS transistor,
4...2nd P channel MO8I-ransistor,
5...First N-channel MOS transistor, 6
...Second N-channel MOS transistor, 7.
...Latch part, 8...Buffer part, 9...
...Internal terminal 1.10 ...Internal terminal 2.1
1... Output terminal, 12... Power terminal,
13... Ground terminal, 14... N channel MOS transistor ■, 15... N channel MOS transistor ■, 16... Voltage detection circuit.

Claims (3)

[Claims] (1) In a level shift circuit having a latch section and a buffer section, in the latch section, the drain of the first P-channel MOS transistor is set as internal terminal 1, the gate is set as internal terminal 2, and the source is connected to a power supply terminal; second P
A channel MOS transistor has a drain connected to the internal terminal 2, a gate connected to the internal terminal 1, a source connected to the power supply terminal, and a first N-channel MOS transistor.
The drain of the S transistor is connected to the internal terminal 1, the gate is connected to the input terminal 1, the source is connected to the ground terminal, the drain of the second N-channel MOS transistor is connected to the internal terminal 2, and the gate is connected to the input terminal 2. A level shift circuit characterized in that the source is connected to the ground terminal. (2) In the level shift circuit according to claim 1, one N-channel MOS transistor is further added, and its drain is connected to the internal terminal 1, its gate is connected to the internal terminal 2, and its source is connected to the ground terminal. A level shift circuit characterized by connecting. (3) An N-channel MOS transistor is further added to the level shift circuit according to claim 2, and its drain is connected to the internal terminal 1, its gate is used as an external input terminal, and its source is connected to a ground terminal. 2. The level shift circuit according to claim 1.