JPH04237214A - Clocked inverter - Google Patents

Abstract

PURPOSE:To exclude malfunction of a circuit due to a noise signal even when the noise signal whose level is over a threshold voltage of a transistor(TR) connecting to a power supply line or a ground line is introduced. CONSTITUTION:PMOS TRs 1, 2 and 6 and NMOS TRs 3-5 are provided corresponding to a load capacitor 7. Then a source input is set to a ground level (GND) and a gate input is set to an inverted clock signal 102 to decrease the gm, thereby increasing an on-resistance of the NMOS TR 5. Moreover, the source input is set to a power supply voltage VDD and the gate input is selected to be a clock signal 103 to decrease the gm, thereby increasing the on-resistance of the PMOS TR 6. Then corresponding to the inputs of the data signal 101, the inverse clock signal 102 and the clock signal 103, a prescribed level is outputted from a connecting point between a drain of the PMOS TR 2 and a drain of the NMOS TR 3.

Description

[Detailed description of the invention]

0001

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a clocked inverter, and more particularly to a clocked inverter constructed from a semiconductor integrated circuit.

0002

2. Description of the Related Art A conventional clocked inverter is constructed as shown in FIG.
When the transistor 10 is off, the output side (OUT) is in a high impedance state, and the load capacitance 12 holds charge. data signal 1
04 is high level, the reverse clock signal 105 is high level, and the clock signal 106 is low level, the PMOS
When the transistors 8, 9 and the NMOS transistor 10 are OFF and the output side (OUT) is in a high impedance state, a noise signal higher than the threshold voltage of the transistor is applied to the power supply voltage VDD, which is the source input of the PMOS transistor 8. When mixed, the PMOS transistor 8 is turned on due to the potential difference generated between the gate and source of the PMOS transistor 8, which causes a potential difference between the gate and source of the PMOS transistor 9, and the PMOS transistor 8 is turned on.
Transistor 9 is also turned on. As a result, PMOS transistor 8→PMO
The load capacitor 12 on the output side is charged through the path from the S transistor 9 to the load capacitor 12, and there is a possibility that the circuit will malfunction.

Furthermore, when the input data signal 104 is at a low level, the reverse clock signal 105 is at a high level, and the clock signal 106 is at a low level, the PMOS transistor 9 and the NMOS transistors 10 and 11 are turned off, and the output side (OUT) is turned off. When in a high impedance state, if a noise signal higher than the threshold voltage of the transistor is mixed into the ground voltage (GND) that is the source input of the NMOS transistor 11, the NMOS transistor 11
The NMOS transistor 11 is turned on due to the potential difference generated between the gate and source of the NMOS transistor 10, which causes a potential difference between the gate and source of the NMOS transistor 10, and the NMOS transistor 11 is turned on.
The S transistor 10 is also turned on. As a result,
The charge stored in the load capacitor 12 is discharged through the path of load capacitor 12 → NMOS transistor 10 → NMOS transistor 11 → ground potential (GND), and there is a possibility that the circuit will malfunction.

0004

[Problems to be Solved by the Invention] In the conventional clocked inverter described above, when using two power supplies including a positive power supply and a negative power supply, and a PROM circuit, etc., the PR
Power supply voltage VD applied to the source of OM transistor 8
When a noise signal higher than the threshold voltage of the corresponding transistor is mixed into the ground potential (GND) that is the source potential of the PMOS transistors 8 and 9 or the NMOS transistor 1
There is a drawback that 0 and 11 may turn on, causing a malfunction in the circuit itself.

[0005]

[Means for Solving the Problems] A clocked inverter of the present invention includes a first PMOS transistor whose source is supplied with a high-potential side power supply and whose gate is inputted with a predetermined data signal; a second PMOS transistor whose drain is connected to the drain of the second PMOS transistor and whose gate receives a predetermined clock signal; The first NM
an OS transistor, a second NMOS transistor whose drain is connected to the source of the first NMOS transistor, whose gate receives the data signal and whose source is supplied with a low-potential power supply; A power supply on the low potential side is supplied, and the drain is connected to the first PM.
a third NMOS connected to the drain of the OS transistor and having the gate input with the reverse clock signal;
a third PMOS transistor, the drain of which is connected to the source of the first NMOS transistor, the source of which is supplied with the high potential side power supply, and the gate of which is input with the reverse clock signal; It consists of

[0006]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be explained with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, this embodiment is configured to include PMOS transistors 1, 2, and 6 and NMOS transistors 3 to 5 corresponding to the load capacitance 7.

As is clear from FIG. 1, the difference between this embodiment and the conventional example is that the source input is connected to the ground potential (GND).
and gm with the gate input as the reverse phase clock signal 102
An NMOS transistor 5 has a high ON resistance by reducing gm, and a PMOS transistor 5 has a high ON resistance by reducing gm by setting the source input to the power supply voltage VDD and the gate input to the clock signal 103. The transistor 6 is newly added.

In FIG. 1, an input data signal 10
1 is high level, the reverse clock signal 102 is high level, and the clock signal 103 is low level, the PMOS
Transistors 1, 2 and NMOS transistor 3 are O
The NMOS transistors 4 and 5 and the PMOS transistor 6 are turned on, and the output side (OUT) is in a high impedance state. In this case, PMOS
To the power supply voltage VDD, which is the source input of transistor 1,
When a noise signal higher than the threshold voltage of the transistor is mixed in, the PMOS transistor 1 is turned on due to the potential difference generated between the gate and source of the PMOS transistor 8.
As a result, a potential difference occurs between the gate and source of the PMOS transistor 2, and the PMOS transistor 2 also tries to turn on, but as mentioned above, the NMOS transistor 5 whose gm value is set to a small value is turned on. Therefore, as the source input of PMOS transistor 2, N
Since it is at the ground potential (GHD) level through the equivalent resistance of the MOS transistor 5, P becomes ON due to the noise signal mixed in the power supply voltage VDD.
The influence of the drain output of MOS transistor 1 is
It is not transmitted to transistor 2, and PMOS transistor 2 is maintained in an OFF state.

Furthermore, when the input data signal 101 is at a low level, the reverse clock signal 102 is at a high level, and the clock signal 103 is at a low level, the PMOS transistor 2 and the NMOS transistors 3 and 4 are turned off.
However, the PMOS transistors 1 and 6 and the NMOS transistor 5 are turned on, and the output side (OUT) is in a high impedance state. In this case, to the ground potential (GND) which is the source input of the NMOS transistor 4,
When a noise signal higher than the threshold voltage of the transistor is mixed in, the NMOS transistor 4 is turned on due to the potential difference generated between the gate and source of the NMOS transistor 4.
As a result, a potential difference occurs between the gate and source of the NMOS transistor 3, and the NMOS transistor 3 also tries to turn on, but as mentioned above, the PMOS transistor 6, whose gm value is set to a small value, is turned on. Therefore, the source input of the NMOS transistor 3 is P.
Since the power supply voltage VDD level is reached through the equivalent resistance of the MOS transistor 6, the influence of the drain output of the NMOS transistor 4, which is in the ON state, is affected by the noise signal mixed into the ground potential (GND). , N.M.
It is not transmitted to the OS transistor 3, and the NMOS
Transistor 3 is maintained in an OFF state.

[0011]

As explained above, the present invention adds a PMOS transistor and an NMOS transistor with gm set to a small value to a conventional clocked inverter, thereby making it possible to Even when a noise signal higher than the threshold voltage of the corresponding transistor is mixed in, circuit malfunctions caused by this noise signal can be eliminated.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

FIG. 2 is a circuit diagram showing a conventional example.

[Explanation of symbols]

1, 2, 6, 8, 9 PMOS transistor 3~
5, 10, 11 NMOS transistor 7, 12
Additional capacity

Claims (1)

[Claims] [Claim 1] A high potential side power source is supplied to the source,
a first PMOS whose gate receives a predetermined data signal;
a second PMOS transistor whose source is connected to the drain of the first PMOS transistor and whose gate receives a predetermined reverse clock signal; whose drain is connected to the drain of the second PMOS transistor and whose gate is connected to the second PMOS transistor; A first clock signal is input to the first clock signal.
an NMOS transistor whose drain is connected to the first NM
A second NMOS transistor is connected to the source of the OS transistor, has its gate inputted with the data signal, and has its source supplied with low-potential power. is the first
A third NMOS transistor is connected to the drain of the PMOS transistor, and the gate of the third NMOS transistor is connected to the drain of the PMOS transistor.
a MOS transistor, the drain of which is the first NMOS transistor;
A clocked inverter comprising: a third PMOS transistor connected to the source of the transistor, the source of which is supplied with the high potential side power supply, and the gate of which is input with the reverse clock signal.