JPS63119323A - Insulated gate type output buffer circuit - Google Patents

Abstract

PURPOSE:To reduce the charging/discharging current of the parasitic capacitance of an output signal line and to improve the response speed and to reduce the current consumption by limiting the potential in the high level of an output node to a prescribed value. CONSTITUTION:If a data signal D rises to the high level when an output enable signal OE is in the high level, a P-channel transistor TR TP is turned on because the outout of a NAND gate 2 goes to the low level, and an output node NO starts rising to the high level. When the level of the output node NO exceeds the logical threshold of an inverter 4 on the way of this rise, the output of the inverter 4 goes to the low level and the output of a NAND gate 2 goes to the high level, therefore, the P-channel TR TP is turned off. Thus, the response speed is improved and the current consumption is reduced because the output node NO is stabilized in the logical threshold level of the inverter 4 and the charging/discharging current of the parasitic capacitance of the output signal line is reduced.

Description

[Detailed Description of the Invention] [Object of the Invention (Industrial Application Field) The present invention relates to an output buffer circuit of a semiconductor integrated circuit.
In particular, it relates to the 0MO8 (insulated gate) output passer circuit.

(Prior Art) A conventional output buffer circuit in a CMO8 type O8 circuit is configured as shown in FIG. That is, between the vDD power supply node and the v0 power supply node (ground terminal), I/cP channel transistors T, b and N channel transistor T
N are connected in series, and both transistors T,
, TH (output node N0) is connected to the output node 31 via a low resistance R't-. The output of a NAND 32 to which the data signal and output enable signal OE are input is led as the r-) input of the P-channel transistor TP. Further, as the gate input of the N-channel transistor TN, the output of a NOR gate 34 to which the OF multiplied signal obtained by inverting the oE signal and the data signal is input is led.

In the above output buffer circuit, when the OK double signal is low level, the output of NAND e-) 32 becomes high level,
Since the output of the NOR gate 34 becomes low level, the P channel transistor T and the N channel transistor TN
Both are in the off state, output node N. becomes a high impedance state. On the other hand, when the OE times signal is at a high level, the level of the output node N0 is determined by the data signal. That is, when the data signal is at a high level, the output of the NAND gate 32 and the output of the NOR gate 34 are both at a low level, the P-channel transistor T is on, the N-channel transistor T0 is off, and the output node N0 becomes high level. Contrary to the above, when the data signal is at a low level, both the output of the Nant gate 32 and the output of the NOR gate 34 are at a high level, the P-channel transistor T is in the off state, and the N-channel transistor TN is in the on state. None, output node N. will be at a low level.

By the way, the above CMO8 type output buffer circuit has an external TTL (transistor, transistor, logic)
When the circuit is t-driven, there are problems as described below.

That is, the high level (V□) of the input voltage of the TTL circuit is 2.
However, the high level of the output voltage of the 0M08 circuit is increased to 5V by the P-channel transistor T. Therefore, the parasitic capacitance of the output signal line is unnecessarily charged and discharged, resulting in a decrease in response speed and an increase in current consumption.

(Problems to be Solved by the Invention) The present invention has been made in order to solve the problem that an unnecessarily large amount of charge/discharge current flows through the parasitic capacitance of the output signal line when driving a TTL circuit as described above. It is an object of the present invention to provide an insulated gate type output parallel circuit that can reduce the charging and discharging current of the parasitic capacitance, improve response speed, and reduce current consumption.

[Configuration of the Invention (Means for Solving the Problems)] The CMO8 type old-fashioned single output 2777 circuit of the present invention is connected in series between the potential side power supply node and the low potential side power supply node, and each r- ) Inputs are applied separately to the P-channel transistor and N-channel transistor, and when it is detected that the output voltage of the output node to which the drains of both transistors are connected to each other has become higher than a predetermined threshold voltage, the P-channel transistor The present invention is characterized by comprising a circuit that controls the transistor to be in an off state.

(Function) The high level potential of the output node is limited to a predetermined threshold voltage, the charging/discharging current of the parasitic capacitance of the output signal line is reduced, the response speed is improved, and current consumption is reduced. Become.

(Example) Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

Figure 1 shows, for example, a CMO8 type integrated circuit.
The O8H1ieP output buffer circuit is shown, with vK and D power supply nodes on the high potential side and v0 on the low potential (ground potential) side.
A P-channel transistor T and an N-channel transistor TN are connected in series between the power supply node and the power supply node.

The drain interconnection point (output node N) of both the transistors T and ITN is connected to the output pad 1 through a low resistance R.
It is connected to the. The output of the three-power Nantes gate 2 is led to the r-) of the P-channel transistor T, and N
The gate of the channel transistor TH is equipped with a two-man Noah e.
−),? The output of is derived. The above NAND f-)2 is input with the data signal, the output enable signal OE, and the output of the inverter 4, and the NAND f-)
3, the 90E signal which is inverted by the OE double signal input 5 and the data signal RI are inputted. The input terminal of the inverter 4 is connected to the output node N0, and the logic threshold of the inverter 4 is set at a margin of 1. It is set to about 3.0V plus OV i.

Next, the operation of the output buffer circuit will be explained.

First, when the OE times signal is low level, the output of NAND gate 2 becomes high level and the output of NAND gate 2 becomes low level, so the P-channel transistor and N
Both channel transistors T and T are turned off, and the output node N0 is placed in a high impedance state. On the other hand, when the OE times signal is at a high level, a level corresponding to the data signal appears at the output node N0. That is, when the data signal is at a low level, the output of the NOR gate 3 is at a high level, so the N-channel transistor TN is not turned on, and the output node N0 is at a low level. Next, when the data signal rises to a high level, the output of the NAND gate 2 becomes a low level, so that the P-channel transistor T is not turned on and the output node N is turned on. begins to rise towards a higher level. In the process of this rise, the output node N. When the level of ? exceeds the logic threshold of inverter 4 (3.0 V in this example), the output of this inverter 4 becomes low level and the NAND gate, ? Since the output of T becomes high level, the P-channel transistor T is turned off. by this,
The level of the output node N0 becomes stable at the logic threshold level of the inverter 4. Further, when the data signal falls to a low level again, the P-channel transistor T remains off and the N-channel transistor T8 turns on, so that the output node N0 falls to a low level.

That is, in the output buffer circuit, when the data signal fluctuates between the ground potential and the vDD power supply potential, the level of the output node N0 fluctuates between the ground potential and the logic threshold level of the inverter 4. Therefore, due to the above output buffer circuit, the TTL circuit 't-f' outside the CMO8 type integrated circuit is
In the case of f1 movement, the parasitic capacitance of the output signal line and the amount of charging/discharging current are reduced compared to the conventional example, so it is possible to improve response speed and reduce current consumption.

It should be noted that the present invention is not limited to the above embodiments;
In the MO8 type Imadeka Ima output 2277, a circuit may be provided to detect that the level of the output node has become higher than a predetermined dark value voltage and to control the output stage P-channel transistor to the OFF state. 0MO8FIL-II shown in Figure 2)
The output puff and child circuits are not controlled by the output enable signal OE (do not have a tri-state function), and the OK signal system has been removed compared to the output buffer circuit shown in Fig. 1 described above. It is something that That is, the data signal is inverted by the inverter 21 and input to the r-) of the N-channel transistor TN, and the output of the two-man NAND gate 22 to which the data signal and the output of the inverter 4 are input is the f of the P-channel transistor T. -), low resistance R and output motherboard 1.
remains as is.

The operation of the output buffer circuit shown in FIG.
The operation is similar to the operation when the OE multiplied signal is at a high level in the output buffer circuit shown in the figure.

[Effects of the Invention] As described above, the CMO8 type of the present invention has a single output of 277
According to No. 7, since the high level potential of the output node is limited to a predetermined value, the charging/discharging current of the parasitic capacitance of the output signal line can be reduced.

Therefore, it is possible to improve response speed and reduce current consumption.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing one embodiment of the CMO8 type fist output puffer circuit of the present invention, FIG. 2 is a circuit diagram showing another embodiment,
FIG. 3 is a circuit diagram showing an embodiment of a conventional CMO8-type rare output buffer circuit. T,...P channel transistor, TN...N channel transistor, No...output node, 1...output pad, 2, 22...Nand r-), 3...Nor r-) , 4.5.21... Inverter.

Claims (1)

[Claims] A P-channel transistor and an N-channel transistor are connected in series between a high-potential side power supply node and a low-potential side power supply node, and each gate input is given separately, and an output node where the drains of both transistors are connected to each other. an insulated gate type output buffer circuit, comprising: a circuit for detecting that the output voltage of the P-channel transistor has become higher than a predetermined threshold voltage and controlling the P-channel transistor to an OFF state.