JP2919130B2 - Test signal generation circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test signal generating circuit, and more particularly to a test signal generating circuit used in a semiconductor integrated circuit.

[0002]

2. Description of the Related Art A conventional test circuit for a semiconductor integrated circuit includes:
As an example, as shown in FIG. 4, an N-channel MOS transistor 12 having a source and a gate connected to a high voltage input terminal 53, and an N-channel MOS transistor 1 having a source
2 is connected to the drain of P-channel MOS transistor 13 whose gate is connected to power supply terminal 54; the drain is connected to the drain of P-channel MOS transistor 13; the gate is connected to power supply terminal 54; A high voltage detection circuit including an N-channel MOS transistor 14 connected to a point is used.

[0003] In FIG 4, a power supply voltage supplied to the power supply terminal 54, a high voltage V _H as the input voltage V _i of the high voltage input terminal 53 is input, the level of the test signal at the node B becomes the "H" level , The test mode is set. Further, the high voltage input terminal 53, the potential of the normal of the ground potential up to the power supply voltage V _DD is input, the node B
Is at the "L" level, and the normal operation mode is set. 5 shows, the level of the input voltage V _i corresponding to the normal operation mode and test mode are shown.

[0004] Here, when in the state at the level "H" level of the test signal, the voltage input to the high voltage input terminal 53 is at a high voltage V _H at the node B, N-channel MOS transistor 12 Works when the threshold voltage is V _TN, when the potential at the node a and V _a, the potential V _a at the node a is to satisfy _{V a <V H -V TN,} N channel M
Assuming that the OS transistor 12 is turned on and the threshold voltage of the P-channel MOS transistor 13 is V _TP , when the potential of the node A satisfies the relationship of V _{DD −} {V _TP } <V _A , Channel MOS transistor 13 is turned on. In this case, the potential at the node B is the P channel M
It is determined by the on-resistance ratio between the OS transistor 13 and the N-channel MOS transistor 14. The value of the on-resistance ratio is set to a value at which the output of the “H” level at the node B can be recognized by the next-stage logic circuit.

[0005] A latch circuit is connected in cascade to the output side of the high voltage detection circuit shown in FIG. 4, and each latch circuit is provided with an input terminal corresponding to an individual test function. A test signal generating circuit that generates a large number of test signals with one high voltage input terminal is also used.

[0006]

In the above-described conventional test signal generating circuit, as shown in FIG. 4, the voltage input to the high voltage input terminal 53 of the high voltage detecting circuit is a high voltage _VH . The level of the test signal at the node B is switched.

In this case, the level of the high voltage V _H is MO
It depends on the threshold voltage of the S transistor. The threshold voltage generally varies depending on the diffusion conditions of the semiconductor integrated circuit, and is not a fixed numerical value. Therefore, depending on this variation, the margin between the high voltage V _H and the power supply voltage V _DD is reduced, and if high voltage noise equal to or higher than the high voltage V _H is input from the high voltage input terminal 53, the normal operation mode is set. There is a disadvantage that the mode is switched to the test mode, and the test mode intervenes during the normal operation mode, thereby hindering normal operation of the semiconductor integrated circuit.

[0008]

A test signal generating circuit according to the present invention is a test signal generating circuit for setting a normal operation mode and a test mode for testing a semiconductor integrated circuit. A differentiating circuit that detects a rise of the first power supply voltage and outputs a power-on signal having a predetermined pulse width; and receives the power-on signal, and sets a test mode from a rise of the first power supply voltage when a test mode is set. And a latch circuit that latches a second power supply voltage that rises after a predetermined time delay and rises simultaneously with the rise of the first power supply voltage when a normal operation mode is set.

The differentiating circuit includes a capacitor and a resistor connected in series between the first power supply voltage and the ground potential, and two inverters connected in cascade at a connection point between the capacitor and the resistor. The latch circuit is controlled to be turned on / off by the power-on signal, and has a first transfer gate involved in receiving the second power supply voltage and a second transfer gate for inverting and outputting the power-on signal. A first inverter, a second inverter that inverts and outputs the output of the first transfer gate, and a third inverter that inverts and outputs the output of the second inverter.
A second transfer gate that is turned on / off by an output of the first inverter, and controls whether or not to transmit an output of the third inverter to an input side of the second inverter. It may be formed.

[0010]

Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. As shown in FIG. 1, the present embodiment has a capacity of 2,
The differential circuit 1 includes a resistor 3, inverters 4 and 5, and a latch circuit 6 including inverters 7, 10 and 11, and transfer gates 8 and 9. FIGS. 2A, 2B, 2C, and 2D are timing charts showing operation signals in the test mode in the present embodiment, and FIGS. (b) and (c) are timing diagrams showing operation signals during normal operation.

Referring to FIG. 1, in a differentiating circuit 1, a power supply voltage V _DD1 (see FIG. 2A) is applied to a power supply terminal 51 so that an "H" level signal 101 (FIG.
(See (a)) to detect that the power supply voltage V _DD1 has been turned on. In the latch circuit 6, the “H” level signal 10 output from the differentiating circuit 1 is output.
1, the power supply voltage V _DD2 supplied from the power supply terminal 52 is latched via the transfer gate 8.

[0013] In the test mode, first, from application of the power supply voltage V _DD1 from the power supply terminal 51 (see FIG. 2 (a)), the supply voltage V _DD2 (Fig than the power supply terminal 52 at time T ₁ after 2 (b)). Output signal 1 of differentiating circuit 1 generated by turning on power supply voltage V _DD1
01 (see FIG. 2 (c)) during the period of time T ₂ shown in FIG. 2 (c), exceeds the logical threshold of the transfer gate 8 and inverter 7 is at "H" level state. Also, during this period of time T _2, the transfer gate 8 is in the ON state, the ground level corresponding to the power supply voltage V _DD2 is input to the inverter 11, the test signal 102 (see FIG. 2 (d)) Becomes "H" level, and the next stage logic circuit recognizes that the test signal is at "H" level. “H” of the test signal 102
Level state is maintained for the duration of time T ₃ in FIG. 2 (c).

Next, in the normal operation mode, the power supply terminals 51 and 52 are short-circuited, and the power supply voltages V _DD1 (see FIG. 3A) and V _DD2 (see FIG.
) Are applied simultaneously. The voltage level of the power supply voltage V _DD2 is input to the inverter 11 during the period (T ₄ ) in which the output signal 101 (see FIG. 3C) of the differentiating circuit 1 generated by the supply of the power supply voltage V _DD1 is “H” level. Then, the test signal 102 becomes "L" level, and the logic circuit at the next stage recognizes that the test signal 102 is at "L" level. "L" level state of the test signal 102 is held during the time T ₅ in FIG. 3 (c).

As described above, a required test signal is generated by providing a difference between the rise times of the two power supply voltages including the power supply voltages V _DD1 and V _DD2 .

[0016]

As described above, according to the present invention, by providing a time difference between the rise times of a plurality of power supply voltages,
By generating the predetermined test signal, there is an effect that it is possible to eliminate a failure that the normal operation mode is disturbed by noise at the input terminal.

[Brief description of the drawings]

FIG. 1 is a circuit diagram showing one embodiment of the present invention.

FIG. 2 is a timing chart of operation signals in a test mode of the embodiment.

FIG. 3 is a timing chart of operation signals in a normal operation mode of the embodiment.

FIG. 4 is a circuit diagram showing a conventional example.

FIG. 5 is a diagram showing a relationship between an operation mode and an input voltage in a conventional example.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Differentiating circuit 2 Capacity 3 Resistance 4, 5, 7, 10, 11 Inverter 6 Latch circuit 8, 9 Transfer gate 12, 14 N-channel MOS transistor 13 P-channel MOS transistor

Claims (2)

(57) [Claims] 1. A test signal generating circuit for setting a test mode for testing a semiconductor integrated circuit and a normal operation mode, wherein a power supply having a predetermined pulse width by detecting a rise of a first power supply voltage a differentiating circuit for outputting a on signal, receiving said power-on signal, during test mode setting rising delayed a predetermined time from the rising of the first power supply voltage, the normal operation mode setting said first A latch circuit for latching a second power supply voltage that rises simultaneously with the rise of the power supply voltage. 2. A test for setting a test mode and a normal operation mode for testing a semiconductor integrated circuit
A test signal generating circuit for generating a signal, wherein a differentiating circuit for detecting a rising edge of the first power supply voltage application and outputting a power-on signal having a predetermined pulse width;
And a capacitor and a resistor connected in series between a power supply voltage and a ground potential of the power supply voltage and a ground potential, and two inverters connected in cascade at a connection point between the capacitor and the resistor. A latch circuit for latching the second power supply voltage, the on / off of which is controlled by the power-on signal, a first transfer gate involved in receiving the second power supply voltage, and an inverted power-on signal for output A first inverter that inverts the output of the first transfer gate to output the test signal, and a third inverter that inverts and outputs the output of the second inverter. ON / OFF is controlled by the output of the first inverter,
And a second transfer gate for controlling whether or not to transmit the output of the inverter to the input side of the second inverter.