JPH01176964A - Testing circuit for integrated circuit device - Google Patents

Abstract

PURPOSE:To use an optional input terminal as a test terminal only in a test mode and to eliminate the need to provide a test terminal specially by providing a selector which selects the test mode with a control signal from a control signal generating circuit. CONSTITUTION:A selector SCi is put in an optional input means and a selector SC0 is put in all output stages; when the selector SCi and selector SC0 operate with a control signal from an input terminal CN, said selectors turns to the test mode. Then when '0' and '1' are inputted to an input terminal Ai, signals of 'L' level and 'H' level appear at an output terminal A0. Here, an input terminal CN is an internal terminal. Then the control signal generating circuit inputs the output signal PR of a power-on and reset circuit POR as the set signal of a FF circuit and the output of the FF circuit at the terminal CN as a control signal C or inversion control signal C. Further, the reset signal of the FF circuit is obtained from an input terminal Bi and operates as a test state exiting signal to enter a state wherein normal operation can not be handed.

Description

[Detailed Description of the Invention] [Summary] Regarding a test circuit suitable for being incorporated into an integrated circuit device to test or detect failures of the integrated circuit device, the test circuit is incorporated into the integrated circuit device and the test terminals are separated. The purpose is to make it possible to operate the test circuit without having to set it up, and a control signal generation circuit that generates a control signal by setting a latch circuit with a signal from a power-on reset circuit. , are inserted between any input terminal and the input side of the logic circuit, and between the output side of the logic circuit and all output terminals, and select the test mode with the control signal from the control signal generation circuit. and a selector.

[Industrial application field]

The present invention relates to a test circuit suitable for being incorporated into an integrated circuit device to test or detect failures of the integrated circuit device.

[Conventional technology]

Generally, when performing direct current (DC) tests on integrated circuit devices that include logic circuits, the output cover sofa circuit simply goes to a high level ("H"), except for tests such as power supply current. L/Hell) and Hero level (“L” level), and if it is 3-state, in addition to that, high impedance SMI level (“
Z″ level], the test will be completed.

However, in order to perform such tests, it is necessary to operate the logic gates within the integrated circuit device, and in this case, the internal logic must be considered and a pattern for DC testing must be created. First, in integrated circuit devices in which logic circuits have become large-scale, this work becomes a considerable burden.

FIG. 6 shows an explanatory diagram of the main part of the integrated circuit device.

In the figure, A and B indicate input terminals, LC indicates an internal logic circuit, and Ao and Bo indicate output terminals, respectively.

In this integrated circuit device, in order to output "H" level or "L" level to output terminals A0 and Bo, respectively,
It is necessary to input a test pattern that takes logic into consideration into the input terminals At and B, and the complexity of the logic is directly linked to the complexity of the test pattern.

Therefore, a test circuit that operates the output sofa circuit without operating the logic gate is incorporated into the integrated circuit device to reduce the burden of creating a DC test pattern.

Such an integrated circuit device is provided with a test terminal, and by inputting a control signal to the test terminal, the integrated circuit device is placed in a test mode.

FIG. 7 shows an explanatory diagram of a main part of an integrated circuit device incorporating a test circuit, and symbols used in FIG. 6 indicate the same parts or have the same meanings.

In the figure, TEST is the test terminal, sc is the selector, and i
nl and in2 are input terminals of the selector, 0utl and ou
t2 is the output terminal of the selector, A41 and Bit are the output signals of the large-power buffer circuit, C is the control signal from the test terminal TEST, and Aol and E3ot are the output signals of the logic circuit LC.

In this integrated circuit device, the selector sc is controlled by the control signal C from the test terminal TEST, and the output signals A, 1 and B from the internal logic circuit LC. l and input terminal A.
The signals A i + and B i I input from i and B and obtained via the input buffer circuit are directly transmitted to the output terminals A0 and Bo via the output buffer circuit.

In this way, input terminal A! Since signals are directly transmitted from output terminals A0 and B to output terminals A0 and Bo, test patterns can be created while ignoring internal logic circuits, and the work becomes extremely simple.

[Problem to be solved by the invention]

In the integrated circuit device explained with reference to FIG. 7, there is no need to create a test pattern corresponding to complicated logic, and although the work is very easy, it is not necessary to input control signals for testing. It is necessary to separately install a test terminal for this purpose. However, since the number of terminals of an integrated circuit device is limited, it is not possible to incorporate a test circuit if there is not enough room.

The present invention makes it possible to incorporate a test circuit into an integrated circuit device and operate the test circuit without separately providing a test terminal.

[Means to solve the problem]

Figure 1 is an explanatory diagram of the main circuit for explaining the present invention in detail, and the same symbols as those used in Figures 6 and 7 indicate the same parts or have the same meaning. do.

In the figure, SC3 is a selector incorporated in the input stage, and T
C, indicates a selector incorporated in the output stage, CN indicates a control signal input terminal, and TL indicates a test line.

In the present invention, a selector sci is provided at any input stage, and
A selector S00 is incorporated in each output stage, and selectors SC1 and SC are selected depending on the control signal from the input terminal CN.
0 is operated to establish the test state, and “O” is applied to input terminal A1.
, when the “l” signal is input, “
It is capable of outputting an L'' level signal and an 'H'' level signal.

Here, the input terminal CN of the control signal is not a terminal connecting the inside and outside of the integrated circuit device, but is an internal terminal, and may be a node within the integrated circuit device.

Now, in the present invention, selector SC5 or SC,
Since the aim is not to provide a separate input terminal to the integrated circuit device for inputting a control signal for operating the control signal, the input terminal CN for the control signal is provided with a control signal generated within the integrated circuit device. It is designed to input signals, and
It would be pointless to use a dedicated input terminal to operate the circuit that generates the control signal.

FIG. 2 is an explanatory diagram of a main circuit for explaining the present invention in detail, and is a circuit that generates a control signal to be input to the input terminal CN shown in FIG. In addition, Fig. 1, Fig. 6, Fig. 7
Symbols used in the drawings indicate the same parts or have the same meaning.

In the figure, FOR is the power-on reset circuit, F
F is a flip-flop circuit, 5ctb is a selector, S
T is the set terminal (preset terminal) of the flip-flop circuit, RT is the reset terminal (clear terminal) of the flip-flop circuit, D is the data input terminal, GK is the clock input terminal, Q is the output terminal, and XQ is the inverted output terminal. , PR are the output signals of the power-on reset circuit, C is the control signal, and PR is the inverted control signal.

In this control signal generation circuit, the output signal PR from the power-on reset circuit POR is input to the set terminal ST as a set signal of the flip-flop circuit FF, and the output of the flip-flop circuit FF is input as the control signal. C
Alternatively, an inverted control signal is inputted to the control signal input terminal CN shown in FIG. Which control signal to use may be selected so that the test mode is entered when the power is turned on.

Further, the reset signal of the flip-flop circuit FF is obtained from an arbitrary input terminal in which a selector is incorporated and which is separated from the internal logic circuit LC in the test mode. , is obtained from the input terminal Bi in which the selector 5C=b is incorporated. This reset signal acts as a test state exit signal, and the integrated circuit device becomes ready for normal operation.

After inputting a signal to cancel the test mode, the input terminal B (is disconnected from the flip-flop circuit FF due to the test mode being canceled, and
Connected to logic circuit LC.

Of course, such operations are similarly performed for other input/output terminals incorporating test circuits.

In this way, in the present invention, the test mode is automatically entered by using the signal from the power-on reset circuit FOR, and in the test mode, the internal logic Since the test state exit signal is obtained from an arbitrary input terminal, such as input terminal B, which is separated from the circuit LC, there is no need to separately provide a test terminal to the integrated circuit device.

In the test circuit explained with reference to FIGS. 1 and 2, a flip circuit with set (preset) and reset (clear) is used to set the test mode in response to the output signal PR from the power-on reset circuit POR. A flop circuit FF is used, but the point is that it is set by a signal from the power-on reset circuit POR, and any input terminal that is disconnected from the logic circuit LC in the test mode, for example, an input terminal. Since it is only necessary that the signal from Bi causes a reset and the control signal C etc. to change, any circuit having a latch function can serve as a control signal generating circuit.

For this reason, the test circuit according to the present invention requires a power-on reset circuit (for example, a power-on reset circuit).
A latch circuit (for example, a flip-flop circuit FF or a NAND latch circuit LH) is set by a signal from a reset circuit (FOR), and a control signal (for example, a control signal C) is set.
A control signal generation circuit (e.g., control signal generation circuit CG) that generates a
) and between the output side of the logic circuit and all output terminals (for example, output terminal OUT), and select a test mode using a control signal from the control signal generation circuit. (For example, selector SC and SC
0, etc.).

[Effect]

By adopting the above means, any input terminal in the integrated circuit device can be used as a test terminal only in the test mode, and there is no need to separately provide a test terminal.

〔Example〕

FIG. 3 shows a block diagram of main parts of one embodiment of the present invention, and the first
The same symbols as those used in the figures and FIG. 2 indicate the same parts or have the same meanings.

In the figure, t nil+ I n+1 1 n+3
is the input end of the selector SCi inserted on the input side, T autl+ Toutz+ Toot! is also the output terminal for test mode in selector sci,
outil.

Outi! , outl3 is the output terminal for normal mode, CT
Similarly, i is the control signal input terminal of the selector SC.
nol, 'B, ino,, is the input terminal of selector S00 inserted on the output terminal side, TtllT
'tz is also the input terminal for test mode in selector SC0, outl and out2 are also selector S0
0, the output terminal CT is also a control signal input terminal of the selector SC, and CG is a control signal generation circuit using the power-on reset circuit explained with reference to FIG. 2, TL+, TLz.

TL3 is the test line, ai+bi+' cage is the input signal from the input terminal Ai + Bi + C4, I)o
l is a signal created in the logic circuit LC to output from the output terminal out, bcI is a signal created in the logic circuit LC to control the output terminal out, bat is the selector S0
0 is the output signal to the output terminal out selected by selector S00, bct is the control signal for the output terminal out selected by selector S00, C is the control signal generated by the control signal generation circuit CG, a
t indicates a signal that controls (resets) the control signal generation circuit CG.

In this embodiment, in the test mode, the signal from the input terminal 1nlt of the selector SCz on the input side is sent to the output terminal Touy+, and the signal from the input terminal ink is sent to the output terminal T. The signal from input terminal ink, , to u1□ is output terminal T. In addition, the signal from the input terminal Ttl of the selector SC0 on the output side is output to outl, and the signal from the input terminal T'tz is output to out2. , its operation is no different from the principle of the invention described with reference to FIGS. 1 and 2. In the test mode, if the signals to be input to the input terminals A and B are appropriately selected, the output terminal OUT will have the 'H' level, 'L' level, and 'Z' level. It is possible to obtain the output.

FIG. 4 is a detailed circuit diagram of the main part of the embodiment shown in FIG. 3, and the same symbols as those used in FIGS. 1 to 3 indicate the same parts or have the same meanings. Shall have.

What should be noted in this embodiment is the content of the control signal generation circuit CG. That is, in the principle of the present invention, power
The explanation has been made using a flip-flop circuit FF which is set by a signal from the on-reset circuit FOR and reset by a signal from any input terminal of the integrated circuit device. Circuit F
It was suggested that F could be replaced by a circuit with an appropriate latch function. Control signal generation circuit C shown in Figure 4
In G, a NAND latch circuit LH is combined with a power-on reset circuit FOR instead of a flip-flop circuit FF. As described above, in the present invention, the configuration of the latch circuit that is set and reset to generate the control signal C or the selector that switches the signal is arbitrary, and various formats can be selected. Can be done.

Incidentally, in any of the above embodiments, switching from the test mode to the normal mode is achieved by selecting an arbitrary input terminal in the integrated circuit device, for example, the input terminal Ci, and transmitting a "0" signal. Enter this to exit from test mode.

It would be very desirable if the operation to escape from the test mode could also be used as an operation that is always performed when operating the logic circuit.

FIG. 5 shows an explanatory diagram of the main part circuit of an embodiment that can meet the above expectations, and the same symbols as those used in FIGS. 1 to 4 indicate the same parts or have the same meanings. shall be taken as a thing.

In the figure, RTic indicates a reset terminal in the integrated circuit device.

The difference between this embodiment and the embodiment shown in FIG. 4 is that the terminal handling the signal for switching from the test mode to the normal mode is the reset terminal RT1 in the integrated circuit device.
c.

Generally, in this type of integrated circuit device, it is necessary to input a reset signal to initialize the logic circuit LC after power is turned on, and a reset terminal is provided for this purpose.

Therefore, if the reset terminal RTic is used instead of the input terminal C4 shown in FIGS. 3 and 4, the test mode will be automatically exited before entering the normal mode operation. , the operator no longer needs to be concerned about the existence of the test circuit. If the above configuration is not adopted, for example, in the case of the embodiments shown in FIGS. 3 and 4, both the operation for exiting the test mode and the operation for initializing the logic circuit are performed. It is necessary to do this.

〔Effect of the invention〕

The test circuit for an integrated circuit device according to the present invention includes a control signal generation circuit in which a latch circuit is set by a signal from a power-on reset circuit to generate a control signal, and a control signal generation circuit that generates a control signal by a signal from a power-on reset circuit. It is equipped with a selector for selecting a test mode using a signal.

By adopting the above configuration, any input terminal in the integrated circuit device can be used as a test terminal only in the test mode, and there is no need to separately provide a test terminal.

[Brief explanation of the drawing]

1 and 2 are circuit explanatory diagrams of the main parts for explaining the present invention in detail, FIG. 3 is a block diagram of the main parts of an embodiment of the invention,
Fig. 4 is an explanatory diagram of the main part circuit of the embodiment shown in Fig. 3, Fig. 5 is an explanatory diagram of the main part circuit of another embodiment, and Figs. 6 and 7 are explanatory diagrams of the main part circuit of the conventional example. each represents. In the figure, SCi is a selector incorporated in the input stage, and T
C, is a selector incorporated in the output stage, CN is a control signal input terminal, TL is a test line, FOR is a power-on reset circuit, FF is a flip-flop circuit, 5C=b is a selector, ST is a flip-flop The set terminal (preset terminal) of the circuit, RT is the reset terminal (clear terminal) of the flip-flop circuit, D is the data input terminal, C
K is a clock input terminal, Q is an output terminal, XQ is an inverted output terminal, PR is an output signal of the power-on reset circuit,
C indicates a control signal, and C indicates an inverted control signal. Patent Applicant: Fujitsu Ltd. Representative Patent Attorney: Akira Aitani Representative Patent Attorney: Hiroshi Watanabe - Figure 5: Main circuit diagram of one embodiment

Claims (1)

[Claims] A control signal generation circuit whose latch circuit is set by a signal from a power-on reset circuit to generate a control signal, and between any input terminal and the input side of a logic circuit and the logic circuit. A test circuit for an integrated circuit device, comprising a selector inserted between the output side of the circuit and all output terminals, and selecting a test mode using a control signal from the control signal generating circuit.