JPH01263739A - Information processor - Google Patents

Abstract

PURPOSE:To read and write a specified register group by switching the output signal and the external signal of the front step register group of a scanning path, inputting them to one register group, switching the output signal and a scanning path output signal and making it into a scanning-out signal. CONSTITUTION:Register groups 1 to 4 are cascade-connected to constitute a scanning path I and register groups 2 and 3 respectively and individually constitute scanning paths II and III. A scanning-in signal and a clock signal CLK1 are inputted to a register group 1, an output signal is inputted to a multiplexer 5, selected from both output signals of the scanning-in signal inputted in the same way, by a scanning path selecting signal S1 and outputted to a register group 2. The register group of the next step or below also executes the input and selecting output, and for a multiplexer 7, the output signal from register groups 2 to 4 is inputted, selected in accordance with scanning selecting signals S0 and S1 and outputted to the external part as the scanning-out signal.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an information processing device, and more particularly to a configuration method of a scan path provided in the information processing device and used for diagnosis and troubleshooting.

Traditionally, in information processing equipment, there is a
One or more scan paths are provided.

In these information processing devices, when the scan path is enabled (hereinafter referred to as scan mode), the registers and various flip-flops in the information processing device are connected in cascade, and the diagnostic processor etc. and flip-flops.

Therefore, by setting the scan mode at the time of evaluating or diagnosing the information processing apparatus, it becomes possible to read out information inside the information processing apparatus or rewrite information inside the information processing apparatus.

For example, if the registers that make up the scan path include registers that store microinstructions for operating the processor, when evaluating an information processing device,
By stopping the processor on which the original microinstruction is being executed and inserting another microinstruction into the register via a scan path or replacing it with another microinstruction, the processor is given another microinstruction. It becomes possible to perform an action.

Also, if the registers that make up the scan path include a register that stores the address of a microinstruction,
By setting an arbitrary address in the register via a scan path and operating the processor, it becomes possible to execute a microprogram from an arbitrary address.

Further, in the event of a failure in the information processing device, various information can be obtained by reading the contents of the registers forming the scan path, and this information can be used to analyze the failure.

In such conventional information processing devices, it is possible to read or write to registers on the scan path, but only in specific registers, that is, registers in which microinstructions are stored, or the addresses of microinstructions. Even if there is a request to read or write only to a registered register, the values of all registers on the scan path can be read or
Alternatively, after reading the values of all registers, only the data corresponding to the registers that are not to be rewritten must be rewritten, and the values of all the registers must be reset using this data via a scan path.

In addition, the number of registers that make up the scan path defined in a part that implements a certain function is too large, and it is necessary to drive the scan operation and accept data from the scan path.
If the capability of the control unit to perform control such as inputting data to the scan path is exceeded, the entire scan path becomes unusable.

The present invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is possible to easily execute a request for reading or writing only to a specific register. It is an object of the present invention to provide an information processing device that can make access to a part of scan paths even when the number of scan paths is so large that it exceeds the capability of a control unit.

An information processing device according to the present invention has a scan path configured of a plurality of register groups in which each register is connected in cascade, and has an output signal from a previous register group and an external signal. a first switching means for switching one of the output signals from the register group and the output signal from the scan path according to an external selection signal and inputting the output signal to one register group; It is characterized by comprising a second switching means that switches in response to an external selection signal to output a scan-out signal from the scan path.

Next, one embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention. In FIG. 0, an information processing device according to an embodiment of the present invention includes register groups 1 to 4 and multiplexers 5 to 7. ing.

Register groups 1 to 4 are scan paths configured by connecting registers according to function, and register groups 1 to 4 are connected in cascade to form one scan path I. Further, register groups 2 and 3 are independently scan paths It,
It constitutes III.

Register group 1 has a scan-in signal and a tally signal Ct.
1 is input to the multiplexer 5, and its output signal is output to the multiplexer 5.

The multiplexer 5 inputs the scan-in signal and the output signal from the register group 1, selects one of these signals according to the scan path selection signal S1, and outputs the signal as an input signal to the register group 2. do.

The output signal from the multiplexer 5 and the quack signal C[2 are input to the register group 2, and the output signal is output to the multiplexer 6.

The multiplexer 6 inputs the scan-in signal and the output signal from the register group 2, selects one of these signals according to the scan path selection signal SO, and outputs that signal as an input signal to the register group 3. .

The output signal from the multiplexer 6 and the clock signal C[3 are input to the register group 3, and the output signal is output to the register group 4 and the multiplexer 7.

The output signal from the register group 3 and the clock signal CLKI are input to the register group 4, and the output signal is output to the multiplexer 7.

The multiplexer 7 inputs the output signals from each of the register groups 2 to 4, selects one of these output signals according to the scan canvas selection signals SO and SL, and uses the selected output signal as a scan out signal. Output to outside.

FIG. 2 is a diagram showing a clock generation circuit used in one embodiment of the present invention. In FIG.
This is a circuit that generates 1 to C[ to 3, and the inverter 81
-83 and Nant gates 84-90.

The inverter 81 inverts the input scan mode signal and outputs it to the Nant gate 84. The inverter 82 inverts the input scan canvas selection signal SO and outputs it to the Nant gates 85 and 86.

The inverter 83 receives the input scan canvas selection signal S1.
is inverted and output to the Nantes gate 85.87.

The Nandt gate 84 performs a NAND operation on the clock signal and the inverted value of the scan mode signal from the inverter 81, and outputs the result of the operation to the Nandt gates 88-90.

The Nant gate 85 performs a NAND operation on the scan mode signal, the scan clock signal, the inverted value of the scan canvas selection signal SO from the inverter 82, and the inverted value of the scan canvas selection signal S1 from the inverter 83, and The calculation result is output to the Nantes gate 88.

The Nandt gate 86 performs a NAND operation on the scan mode signal, the scan clock signal, and the inverted value of the scan canvas selection signal SO from the inverter 82, and outputs the result of the operation to the Nandt gate 89.

The Nant gate 87 performs a NAND operation on the scan mode signal, the scan clock signal, and the inverted value of the scan canvas selection signal S1 from the inverter 83, and outputs the result of the operation to the Nant gate 90.

The Nant gate 88 performs a NAND operation on the operation results from the Nant gates 84 and 85, respectively, and outputs the operation result to the register group 1.4 as a clock signal CLK1.

The Nant gate 8 performs a NAND operation on the operation results from the Nant gates 84 and 86, respectively, and outputs the operation result to the register group 2 as 2 on the clock signal C[.

The Nant gate 90 performs a NAND operation on the operation results from each of the Nant gates 84 and 87, and outputs the operation result to the register group 3 as a clock signal CLK3.

Figure 3 shows the scan scan screen in one embodiment of the present invention.
In Figure 0, which is a diagram showing the relationship between scan canvas selection signals so and si, scan canvas ■ represents register groups 1 to 1.
4, and when this scan canvas I is used, the scan canvas selection signals So and 31 are both logic "
0''.

The scan canvas (2) is composed of a register group 2, and when this scan canvas (2) is used, the scan canvas selection signal SO is logic "0" and the scan canvas selection signal S1 is logic "1".

The scan canvas (2) is composed of a register group 3, and when this scan canvas (2) is used, the scan canvas selection signal SO is logic "1" and the scan canvas selection signal S1 is logic "0".

That is, the register group 1.4 is supplied with the scan clock (clock signal C[to 1) from the clock generation circuit 8 only when the scan scan mode is used.

Also, in register group 2, scan canvas 1. The scan clock (
A clock signal CLK2) is supplied from the clock generation circuit 8.

Further, the register group 3 is supplied with a scan clock (clock signal C[3) from the clock generation circuit 8 only when the scan paths I and I[[ are used in the scan mode.

The operation of one embodiment of the present invention will be explained using these FIGS. 1 to 3.

When operating the scan path I, both the scan path selection signals so and si are set to logic "0" and are input to the multiplexers 5 to 7 and the tally clock generation circuit 8.

In the multiplexer 5, the scan canvas selection signal S1 is logic "0", so the output signal from the register group 1 is selected, and in the multiplexer 6, the scan canvas selection signal SO is logic "0", so the output signal from the register group 2 is selected. be done.

At multiplexer 7, scan path selection signal 5O2S1
Since both are logic "0", the output signal from register group 4 is selected and output as a scan-out signal.

At this time, scan clocks are supplied from the clock generation circuit 8 to the register groups 1 to 4, respectively.

Therefore, register groups 1 to 4 are multiplexers 5 and 6.
are connected in cascade to form a scan path, and all registers can be accessed.

When operating the scan path ■, the scan path selection signal SO is set to logic "0", and the scan path selection signal S
1 is inputted to the multiplexers 5 to 7 and the clock generation circuit 8 as logic "1".

In the multiplexer 5, since the scan path selection signal S1 is logic "1", the scan-in signal is selected, and in the multiplexer 6, since the scan path selection signal SO is logic "0", the output signal from the register group 2 is selected.

In the multiplexer 7, the scan canvas selection signal SO is logic "0" and the scan canvas selection signal S1 is logic "1", so the output signal from the register group 2 is selected and output as a scan out signal.

At this time, the scan clock is supplied from the clock generation circuit 8 only to the register group 2, and the scan clock is supplied to the other register groups 1 and 3.
．． 4 is not supplied with the scan clock from the clock generation circuit 8.

Therefore, the scan clock is supplied only to register group 2, and the signal for register group 2 is selected by multiplexers 5 and 7, so that scan path ■ is formed and only the registers of register group 2 can be accessed. .

Since the scan clock is not supplied to the other register groups 1, 3.4, the values of the respective registers of the register groups 1, 3.4 remain unchanged during this scan operation.

When operating the scan path ■, the scan path selection signal SO is set to logic "1", and the scan path selection signal S
1 is inputted to the multiplexers 5 to 7 and the clock generation circuit 8 as logic "0".

In the multiplexer 5, the scan path selection signal S1 is logic "0", so the output signal from the register group 1 is selected, and in the multiplexer 6, the scan path selection signal SO is logic "1", so the scan-in signal is selected.

In the multiplexer 7, the scan path selection signal SO is logic "1" and the scan path selection signal S1 is logic "0", so the output signal from the register group 3 is selected and output as a scan out signal.

At this time, the scan clock is supplied from the tarock generation circuit 8 only to the register group 3, and the scan clock is supplied only to the register group 3.
．． 4 is not supplied with the scan clock from the clock generation circuit 8.

Therefore, the scan clock is supplied only to register group 3, and the signal for register group 3 is selected by multiplexer 6.7, so that scan path ■ is formed and only the registers of register group 3 can be accessed. .

Since the scan clock is not supplied to the other register groups 1.2.4, the values of the respective registers of register groups 1 and 2.4 remain unchanged during this scan operation.

In this way, register group 1 in which each register is cascade-connected
4, one of the output signal and scan-in signal from the register group 1.2 in the previous stage is switched by multiplexers 5 and 6 according to the scan path selection signals so and si, and the register group 1. 2.3, one of the output signals from register groups 2 to 4 is switched by the multiplexer 7 according to the scan path selection signals so and si, and outputted as a scan out signal. Only register group 2.3 can be read or rewritten.

In this case, if each register group 2.3 is made up of registers having a specific function, for example, a register where a microinstruction is stored or a register where the address of the microinstruction is stored, the information processing device When accessing only a microinstruction or the address of a microinstruction during evaluation, scan path of the register you want to access■,■
This is possible by operating only the

Therefore, the scan path (■) is used when reading or rewriting only a specific register group 2.3.

It is possible to simplify the operation procedure (2) and shorten the time required to access the scan path LI [[.

Further, it is possible to maintain the values of registers other than the register group 2.3 to be accessed during this scan operation at the values before entering the scan mode.

Additionally, it controls the execution of scan operations and
Even if the capability of the circuit for exchanging scan-out signals is exceeded and all registers on the scan canvas I are inaccessible, access to specific register groups 2 and 3 is still possible. It becomes possible.

Note that in one embodiment of the present invention, register groups 2 and 3 can be made into a single scan path I[, I;
It is clear that each register group 1-4 could each be a single scan path.

As explained above, according to the present invention, in a scan path constituted by a plurality of register groups in which each register is cascade-connected, one of the output signal from the previous stage register group and the external signal is transmitted. is switched according to an external selection signal and inputted to one register group, and one of the output signal from this one register group and the output signal from the scan path is switched according to an external selection signal to input the output signal from the scan path. By outputting the scan-out signal as a scan-out signal, it is possible to easily execute a read or write request to only a specific register. This has the effect of making it possible to access a part of the scan path even if the scan path exceeds the scan path.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the invention, FIG. 2 is a diagram showing a clock generation circuit used in an embodiment of the invention, and FIG. 3 is a scan path in an embodiment of the invention. FIG. 4 is a diagram showing the relationship between the scan path selection signal and the scan path selection signal. Explanation of symbols of main parts 1 to 4...Register group 5 to 7...Multiplexer 8...Clock generation circuit

Claims (1)

[Claims] (1) An information processing device having a scan path in which each register is constituted by a plurality of register groups connected in cascade, which selects one of an output signal from a previous register group and an external signal in response to an external selection signal. a first switching means for switching an output signal from the one register group and an output signal from the scan path according to the external selection signal and inputting the signal to the one register group; An information processing device comprising: second switching means that outputs a scan-out signal from the campus.