JPH06160489A - Boundary scan interior test system - Google Patents

Abstract

PURPOSE:To diagnose a circuit to be tested such as an LSI, etc., mounted n a board within a practical time by utilizing sole diagnosis data. CONSTITUTION:Diagnosis cells 5-1-50n corresponding to necessary pulse signals are provided in a circuit to be tested. A boundary scan controller 4 for generating a control signal indicating that setting of diagnosis data necessary to the cell and the cell corresponding to the other internal logic circuit 2 is completed, and pulse generators 30, 31 which latch diagnosis data '1' or '0' to output a pulse signal of a predetermined pulse width under conditions for generating the control signal at a rear stage of the cell corresponding to the pulse signal are provided. The pulse signals to be output from the generators 30, 31 are applied to a necessary part of the corresponding circuit 2 to test a circuit interior to be tested.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary scan internal test system for performing an internal test of a circuit such as an LSI on a substrate having a boundary scan circuit.

[0002]

2. Description of the Related Art Conventionally, in an integrated digital circuit, particularly in an LSI, the physical intervals between its input / output terminals have become small, and tester pins have to be connected to these input / output terminals to apply a diagnostic signal. Since it has become impossible to do so, diagnostic / observation cells consisting of flip-flops for each input / output terminal, and a boundary scan circuit (hereinafter, BS circuit) for setting diagnostic data in these cells from diagnostic data input terminals. Is provided, and the function of the LSI is diagnosed by determining whether or not output data corresponding to the diagnostic data set in the cell is obtained.

This diagnostic method is a boundary scan test method, and its standard specifications are IEEE1149.1.
Stipulated in.

Therefore, if the BS circuit is provided on the substrate by applying this boundary scan test method, the internal test of the LSI arranged on the substrate can be performed. At that time, if the individual diagnostic data when the LSI is tested alone is used for diagnosing the LSI on the board, the number of manufacturing steps of the diagnostic data of the LSI on the board can be reduced, and a strict internal test is performed. be able to.

[0005]

However, when the BS circuit provided on the substrate is used to supply the internal circuit of the LSI, the path from the tester to the internal circuit of the LSI becomes longer than in the case of single diagnosis. Therefore, the pulse signal such as a clock pulse has a distorted waveform on its transmission path, and the delay time specification of the latch operation of the flip-flop cannot be satisfied. Therefore, in order to guarantee the test accuracy, it is necessary to apply the clock at a time interval with a margin compared with the normal operation.

Specifically, when a clock pulse is required in the internal circuit of the LSI, diagnostic data that changes in the order of 0 → 1 → 0 is given to the relevant diagnostic cell, or 1 →
It is necessary to provide diagnostic data that changes from 0 to 1.

Therefore, when the diagnostic data that rises to "1" or the diagnostic data that falls to "0" is given, the data input time required is three times as long as that in the case of the single diagnosis, which causes an increase in test time, There is a problem that diagnosis within a practical time becomes impossible.

In order to avoid this problem, there is a method in which the scanning operation itself for the LSI internal diagnosis is also performed by using the BS circuit. However, this method often does not match the scanning method for the device diagnosis. There is a problem that the time for the single diagnosis itself increases.

An object of the present invention is to use a single diagnostic data of a circuit to be tested to perform a boundary scan internal test capable of diagnosing a circuit to be tested such as an LSI on a substrate within a practical time. It is to provide a method.

[0010]

In order to achieve the above object, the present invention provides a diagnostic cell corresponding to a pulse signal required in the internal logic circuit inside a circuit to be tested and the diagnostic cell. Boundary scan control circuit for generating a control signal indicating that the setting of the diagnostic data necessary for the diagnostic cell corresponding to the other internal logic circuit and the subsequent stage of the diagnostic cell corresponding to the pulse signal,
Provided is a pulse generation circuit which outputs a pulse signal of a predetermined pulse width under the condition that the control data is latched with the diagnostic data of "1" or "0", and corresponds to the pulse signal output from this pulse generation circuit. It is applied to a necessary portion of the internal logic circuit to test the inside of the circuit to be tested.

[0011]

According to the above means, the diagnostic cell corresponding to the pulse signal required in the internal logic circuit of the circuit to be tested is
When the diagnostic data of “1” or “0” is set, this diagnostic data triggers the pulse generation circuit by the control signal generated from the boundary scan control circuit when the diagnostic data is set in all other diagnostic cells. To do.

As a result, a pulse signal having a predetermined pulse width is output and applied to the internal logic circuit of the corresponding LSI.

Therefore, it is only necessary to set the diagnostic data of "1" or "0" to the diagnostic cell corresponding to the internal logic circuit of the LSI which requires the pulse signal, and the input time of the diagnostic data is 1 It can be shortened to / 3, and the circuit to be tested such as LSI can be diagnosed on the substrate within a practical time.

In this case, since the pulse signal output from the pulse generation circuit is transmitted only inside the circuit to be tested, its waveform shape is less distorted and the delay time specification of the flip-flop constituting the diagnostic cell is sufficient. Can be satisfied with.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will now be described in detail with reference to illustrated embodiments.

FIG. 1 is a block diagram showing a main part configuration of an LSI to be tested using the boundary scan internal test method of the present invention.

In the figure, the LSI 1 includes an internal logic circuit 2 which requires a pulse signal, a pulse generation circuit section 3, a boundary scan control circuit (TAP) 4, and boundary scan registers (BS registers) 5-1 to 5-n. Composed.

The internal logic circuit 2 includes input point flip-flop groups (FF group) 7a1 to 7ak, output point flip-flop group (FF group) 7b, FF group 7a and LSI.
The signal input from the 1 input pin is used as the input, and the FF group 7
b and a combinational circuit 8 for sending an output signal to the output pin of the LSI 1.

The pulse generator circuit section 3 includes pulse generator circuits 30 corresponding to the number of pulse signals required by the internal logic circuit 2.
It consists of 31.

The boundary scan is inserted between each input / output pin of the LSI 1 and the internal logic circuit 2 (BS registers) 5-1 to 5-n, and these BS registers 5-1 to 5-1.
And a boundary scan control circuit (TAP; Test Access Port) 4 for controlling the operation of 5-n.

The boundary scan control circuit 4 includes test data TDI, IN TEST (LSI internal test).
Input terminals for a mode control signal TMS and a test clock TCK for switching between EX TEST (board wiring test) and EX TEST are provided, and an output terminal for outputting test result data TDO is further provided.

FIG. 2 is a circuit diagram showing a configuration example of the pulse generation circuits 30 and 31, and FIG. 3 is a time chart thereof. The pulse generation circuits 30 and 31 shown in FIG. 2 are ANDs to which the pulse generation target signal a and the pulse generation control signal e are input.
A gate 310 inputs the output of the AND gate 310 and outputs the input signal b to the AND gate 313. The polarity of the output signal of the gate 311 and the AND gate 310 is inverted, and the input signal c to the AND gate 313 is output. It is composed of an odd number of NOR gates 312 and an AND gate 313 which outputs a logical product signal d of signals b and c.

Here, the NOR gates 312 are cascaded by a sufficient number so that the total delay time can obtain a desired pulse width.

Therefore, in the pulse generating circuits 30 and 31 having such a configuration, the pulse generation control signal e is "1" as shown in FIG. The target signal a is “1” as shown in FIG.
When the output signal b of FIG.
As shown in (2), it rises to "1" with a slight delay. on the other hand,
The output signal c at the final stage of the NOR gate 312 is shown in FIG.
As shown in FIG. 5, the output falls to “0” with a delay of the total delay time of the NOR gate 312. Then, these signals b,
The output signal of the AND gate 313 having c as an input is shown in FIG.
As shown in (4), one pulse signal has a width corresponding to the total delay time of the NOR gate 312.

Therefore, if the pulse generation target signal a is input from the BS register 5-1, that is, the BS register 5-
If "1" is set to 1, the pulse generation circuit 30 can generate a pulse signal having a predetermined pulse width under the condition that the pulse generation control signal e becomes "1".

Similarly, if "1" is set in the BS register 5-2, the pulse generation circuit 31 can generate a pulse signal having a predetermined pulse width under the condition that the pulse generation control signal e becomes "1". it can.

In this case, if the AND gate 310 is a negative logic AND gate, a pulse signal having a predetermined pulse width is generated under the condition that both the pulse generation target signal a and the pulse generation control signal e are "0". be able to.

FIG. 4 is an internal configuration diagram of the BS registers 5-1 to 5-n, which is composed of selectors 50 and 53 and edge-trigger type flip-flops (FF) 51 and 52, and is located on the From Last Cell side. When sequentially shifting the diagnostic data TDI input from, the shift control signal SDR is switched to active (“1”), the diagnostic data TDI is transmitted to the FF 51 via the selector 50, and the shift clock signal CDR is used. Latched.

When the test data TDI is sequentially shifted toward the BS register 5-n, the output data of the FF 51 is the BS of the next stage by the shift clock signal CDR.
It is output to the register. And the diagnostic data TD
Diagnostic data TDI to all BS registers that require I
Is completed, a shift set completion signal UDR indicating this is generated, and the output data of the FF 51 is latched by the FF 52 at the subsequent stage.

The diagnostic data latched in the FF 52 is selected by the selector 53 and input to the internal logic circuit 2 and the like only in the internal test in which the mode signal MODE is "1".

When the internal test is not carried out, the mode signal MODE becomes "0" and the input terminals 10-1 to 10-i.
The input signal from is selected by the selector 53 and input to the internal logic circuit 2 and the like.

In this case, the mode signal MODE, the shift control signal SDR, the shift clock signal CDR signal, and the shift set completion signal UDR are output signals from the boundary scan control circuit 4.

FIG. 5 is a schematic configuration diagram of the boundary scan control circuit 4. Since this circuit is specified by IEEE1149.1, detailed description will be omitted, but the identification information register 40, the instruction register 41, and the bypass register 4 are omitted.
2, controller 43, decoder 44, output circuit 45,
An AND gate 46 is provided, and the signals required in the present embodiment are the decoder 44 and the instruction stored in the instruction register 41.
Internal test (INT
AND signal 4 of signal 47 indicating EST) and shift set completion signal UDR which is an output signal of controller 43
8

This signal 48 is the pulse generation circuit 3 of FIG.
The pulse generation control signal e is input to 0 and 31.

Next, the operation when the boundary scan internal test is performed on the test target LSI configured as described above will be described.

First, in the single diagnosis of the LSI 1, the BS registers 5-1 to 5-n are connected to the input / output terminals 10-1 to 10-1 of the LSI 1.
The selectors 50 and 53 are controlled so that the signal between 10-i and the internal logic circuit 2 is in the through state. That is, the shift control signal SDR signal and the mode signal MO of FIG.
The DE signal is controlled inactive. This state is I
In accordance with the EEE1149.1 regulations, the mode control signal TM
S is "1" and the test clock TCK is 5 consecutively
It can be realized by pulse input or by activating the reset signal TRST.

In this state, the LSI 1 uses the combinational circuit 8 as a unit, and the input point flip-flop group (FF group) 7a1.
Necessary diagnostic data is set in each of 7 to 7ak, the built-in logical operation is performed, the result is latched in the output point FF group 7b, the value of the FF 7b is scanned out, and compared with the expected value. By performing the above, the diagnosis is made for each divided combinational circuit 8.

At this time, each time the clock pulse TCK sets data in the input point FF groups 7a1 to 7ak in 1-bit units, and also in the output point FF group 7b, the combination circuit 8 is provided.
It is applied every time the output result of is latched.

By the way, if such LSI single unit diagnostic data is directly applied to the internal test of the LSI 1 on the substrate, the clock pulse becomes O every time the clock pulse is applied.
It is necessary to pass the three states of FF-ON-OFF.
However, since the states of the other input / output terminals need to be kept the same during the three states of the clock, as shown in FIG.
It is necessary to repeat the operation of shift scan-in to 5-i three times.

That is, for example, when data, which changes from "1"-"0"-"1", is given to the input point FF group 7a1 as a clock signal, the other input point FF groups 7a2-7a.
In k, the same data must be retained.
Therefore, when viewed from the other input point FF groups 7a2 to 7ak,
Wasted test time is spent, and as a result, the test time is lengthened.

Therefore, in the present invention, at the time of an internal test, the BS control circuit 4 is provided in the BS registers 5-1 and 5-2 corresponding to the pulse signal required in the internal logic circuit 2 to be tested.
Set the diagnostic data of "1" through. Then, when the diagnostic data is set in all of the other BS registers 5-3 to 5-n, the BS control circuit 4 generates the pulse generation control signal e to trigger the pulse generation circuits 30 and 31.

As a result, the pulse generation circuits 30, 31 are
A pulse signal having a predetermined pulse width is output from the input terminal and applied to the corresponding input point groups FF7a1 to 7ak of the internal logic circuit 2.

Therefore, as shown in FIG. 6, the BS register 5-corresponding to the internal logic circuit 2 which requires the pulse signal.
It is only necessary to set the diagnostic data of 1 "in 1 and 5-2 by one shift scan operation, the input time of diagnostic data is shortened to 1/3 of the conventional time, and the LSI can be used within a practical time.
The circuit 2 under test 1 can be diagnosed on the board.

In this case, since the pulse signals output from the pulse generating circuits 30 and 31 are transmitted only inside the LSI 1 to be tested, the distortion of the waveform shape is small and the delay time of the flip-flops constituting the diagnostic cell is small. The specifications can be fully satisfied.

Although the internal test on the substrate of the LSI has been described in the present embodiment, the invention is not limited to the LSI and can be similarly applied to the diagnosis of various circuits mounted on the substrate.

Further, in FIG. 1, since the required pulse signals are two types, the number of pulse generation circuits is two.
It is not limited to this.

In the pulse signal having the predetermined pulse width, both the pulse generation target signal a and the pulse generation control signal e are "0".
You may make it generate | occur | produce on the condition of becoming.

[0048]

As described above, according to the present invention, a diagnostic cell corresponding to a pulse signal required by the internal logic circuit is provided inside the circuit to be tested, and the diagnostic cell and other internal circuits are provided. A boundary scan control circuit that generates a control signal indicating that the setting of the diagnostic data necessary for the diagnostic cell corresponding to the logic circuit is completed, and "1" or "" at the subsequent stage of the diagnostic cell corresponding to the pulse signal. A pulse generation circuit that outputs a pulse signal having a predetermined pulse width under the condition that the 0 "diagnostic data is latched and the control signal is generated is provided, and the pulse signal output from this pulse generation circuit is stored in the corresponding internal logic circuit. Since the circuit inside the test target circuit is tested by applying it to the necessary parts, the LSI etc. can be used within a practical time by using the unit diagnostic data of the test target circuit. There is an effect that the circuit under test can be diagnosed in a state of being mounted on a substrate.

[Brief description of drawings]

FIG. 1 is a block diagram showing a main part configuration of an LSI to be tested using a boundary scan internal test method of the present invention.

FIG. 2 is a circuit diagram showing an example of a pulse generation circuit.

FIG. 3 is a time chart of input / output signals of the pulse generation circuit of FIG.

FIG. 4 is a configuration diagram of a BS register.

FIG. 5 is a schematic configuration diagram of a boundary scan control circuit.

FIG. 6 is an explanatory diagram showing an application form of diagnostic data.

[Explanation of symbols]

1 ... LSI, 2 ... Internal logic circuit, 3 ... Pulse generation circuit section, 4 ... Boundary scan control circuit, 5-1 to 5-n
... BS register (diagnostic cell), 30, 31 ... pulse generation circuit.

Claims (1)

[Claims] 1. A diagnostic cell corresponding to a pulse signal required in the internal logic circuit is provided inside the circuit to be tested, and the diagnostic cell corresponding to this diagnostic cell and other internal logic circuits is required. A boundary scan control circuit that generates a control signal indicating that the setting of the diagnostic data is completed, and a diagnostic cell corresponding to the pulse signal, in the subsequent stage,
Provided is a pulse generation circuit which outputs a pulse signal of a predetermined pulse width under the condition that the control data is latched with the diagnostic data of "1" or "0", and corresponds to the pulse signal output from this pulse generation circuit. Boundary scan internal test method characterized by applying the necessary part of the internal logic circuit to test the inside of the circuit under test.