JPH06300821A - Lsi having controller incorporated - Google Patents

Abstract

PURPOSE:To enable execution of an INTEST instruction without using an external circuit, in LSI having a TAP (test access port) controller incorporated. CONSTITUTION:This LSI has a boundary scan register 9 which comprises a plurality of boundary cells 3 to 8 and can execute an INTEST instruction of an internal circuit 2 and a TAP controller 10 which outputs various control signals outside by a decoder, a flip-flop, etc., and realizes a plurality of states including a run-test/idle state. The TAP controller 10 is equipped with a state detecting circuit which detects that the run-test/idle state is present and with a clock generating circuit which outputs a prescribed number of pulses at the time of the run-test/idle state on the basis of an output of the state detecting circuit, a test clock input and a reset signal. At the time of this run-test/idle state, a run-clock signal 12 is delivered from the TAP controller 10 to the boundary cell 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an LS incorporating a controller.
Regarding I, especially an LSI with a built-in controller for the test access port for performing the test of the internal circuit
Regarding

[0002]

2. Description of the Related Art Conventionally, for an LSI incorporating such a test access port controller (hereinafter referred to as a TAP controller), the IEEE standard as an international standard regarding a device interface is recommended (recommendation number:
IEEE 1149.1). This Recommendation is a "Standard for Test Access Port (TAP) & Boundary Scan Architecture". In particular,
The boundary scan method is used for testing a board on which a digital IC is mounted, and is executed by a boundary scan test instruction consisting of an essential instruction and an optional instruction. The essential instructions include an extest (EXTEST) instruction for testing a circuit from the boundary scan register to a required external point.
In addition, for the optional instruction, an in-test (INT) for testing the logic of the internal circuit from the boundary scan register
EST) command. Below is the INTES of these
Limited to T commands.

FIG. 6 is a block diagram of an LSI having a built-in TAP controller showing an example of such a conventional technique. As shown in FIG. 6, a conventional LSI 1a with a built-in controller includes an internal circuit 2 including a logic circuit, a boundary cell 3a connected to an input terminal T1, and a boundary cell 4, connected to input terminals T2 and T3. 5 and boundary cells 6 to 8 respectively connected to the output terminals T4 to T6 in a chain form, and a boundary scan register 9a,
In testing the internal circuit 2, a test clock input TCK as a clock signal and a test mode selection input TMS as a control signal are input, and a TAP controller 10a for controlling the boundary scan register 9a is provided. Further, outside the input terminal T1, a selection circuit 58 for switching between the normal system clock 11 and the INTEST clock 59 based on a selection signal 60 is provided. Further, an external clock generation circuit (not shown) for transmitting the INTEST clock 59 a predetermined number of times is also required.

In this LSI 1a, the boundary scan register 9a includes an internal circuit 2 and input terminals T1 to T.
3 and output terminals T4 to T6, and boundary cells 3a, 4 to 8 as shift register cells having parallel input / output are connected in a chain between the test data input TDI and the test data output TDO. Are arranged. Moreover, the boundary of this shift register
The scan register 9a outputs the value of each input signal and each output signal as serial data or inputs as serial data. The board is tested by the input and output of the boundary scan register 9a.

Here, the INTEST instruction is L on the board.
The SI1a test is performed by the boundary cells 4 connected to the input terminals T2 and T3 other than the system clock input terminal T1.
Test data is input to the internal circuit 2 via 5, while a certain number of clocks are input from the system clock input terminal T1 to operate the internal circuit 2 in one step. At the same time, the output result from the internal circuit 2 is output to the output terminals T4 to T6.
Are taken into the boundary cells 6 to 8 connected to. The data respectively taken in the boundary cells 3a to 8 are shifted and sequentially output from the test data output TDO. Note that the INTEST instruction is completed when the internal circuit 2 completes all steps. However, in the above-mentioned IEEE 1149.1, the input of the system clock 11 at the time of executing the INTEST instruction is input to the TAP controller 1
0a is in the run test / idle state.

Therefore, to enable the LSI 1a to execute the INTEST instruction, the system clock 11 other than when the INTEST instruction is executed and the INTEST clock 59 which is generated only when the TAP controller 10a is in the run test / idle state. These two clocks 1
It is necessary to arrange a selection circuit 58 for inputting a selection signal 60 for selecting 1, 59 on the board and supply a clock signal to the system clock input terminal T1 of the LSI 1a.

FIG. 7 is a circuit diagram of the TAP controller in FIG. As shown in FIG. 7, this TAP controller has a test mode selection input TM as a control signal.
Decoder 13 for inputting and decoding S and data A to D, rising edge output DFFs 15 to 18 for inputting decoding outputs NA to ND, rising edge output DFFs 24 to 27 for reset, and test reset Input TRST Inversion input and inversion DFF
Inverter 14 for supplying the reset input of 24-27 and inverter 23 for inverting the test clock input TCK, and NAND gates 19-22 for taking the combinational logic of outputs A-D and A-inversion-D inversion of DFFs 15-18.
And 28 and 30, and AND gates 29 and 31 having the same combinational logic. As for output signals, the DFFs 24 and 25 output reset inversion signals and enable signals, and the DFFs 26 and 27 output shift IR signals and shift DR signals. Furthermore, N
The AND gates 28 and 30 output the clock IR signal and the clock DR signal, and the AND gates 29 and 31 output the update IR signal and the update DR signal, respectively. The outputs NA to ND of the decoder 13 are input A
.About.D and the test mode selection input TMS, but the logical formulas thereof are omitted here for convenience of explanation.

Such a TAP controller is controlled by a test clock input TCK and a test mode select input TMS and has 16 internal states. Each internal state is DF
It is distinguished as 4-bit data held in F15-18. The run test / idle state described above is one of the 16 internal states.

[0009]

The conventional LSI with a built-in controller described above has a drawback that an external selection circuit is required to execute the INTEST instruction. That is, the system clock used when the INTEST instruction is not executed and the INT generated only when the TAP controller is in the run test / idle state.
The EST clock must be switched using the selection signal. Moreover, since this selection circuit is externally attached,
The number of board components and wiring increase.

A conventional LSI with a built-in controller
However, there is a drawback in that an external clock generation circuit for generating the INTEST clock a predetermined number of times is required only when the TAP controller is in the run test / idle state.

An object of the present invention is to provide INTES without using such an external selection circuit and an external clock generation circuit.
An object of the present invention is to provide an LSI with a built-in controller that enables execution of T instructions.

[0012]

An LSI with a built-in controller according to the present invention comprises a plurality of boundary cells and uses a boundary scan register capable of executing an in-test instruction of an internal circuit, a decoder, a flip-flop and the like. Test that outputs various control signals to the outside and realizes multiple states including run test / idle state
And a controller for access port,
In the test / idle state, the test access
Boundary scan from the port controller
It is configured to send a run clock signal to a boundary cell that inputs the system clock of the register.

Further, the TAP controller detects the state of the run test / idle state, and the run test / idle state based on an output of the state detection circuit, a test clock input and a reset signal. And a clock generation circuit that outputs a predetermined number of pulses at this time.

[0014]

Embodiments of the present invention will now be described with reference to the drawings. FIG. 1 is a block diagram of an LSI with a built-in controller showing an embodiment of the present invention. As shown in FIG. 1, the LSI 1 of this embodiment includes an internal circuit 2 including a logic circuit, a boundary scan register 9 in which a plurality of boundary cells 3 to 8 are connected in a chain, and a boundary scan register. It has a TAP controller 10 for performing a logic test of the internal circuit 2 via a register 9. Also, the boundary scan register 9 has an input terminal T1.
From the TAP controller 10 to the system clock 11 and the internal circuit 2 from the
, The boundary cell 3 has a multiplexer function. The other boundary cells 4 to 8 are the same as those of the conventional example shown in FIG. Furthermore, T of this embodiment
The AP controller 10 includes a decoder, a flip-flop, etc., and outputs various control signals to the outside (not shown) to realize a plurality of states including a run test / idle state. Especially in the run test / idle state,
The TAP controller 10 outputs the run clock signal 12 to the boundary cell 3 to which the system clock 11 of the boundary scan register 9 is input.

In this way, the TAP controller 10 inside the LSI creates the run clock signal 12, thereby eliminating the need for an external circuit, an external test clock, or the like.

FIG. 2 is a circuit diagram of the TAP controller in FIG. As shown in FIG. 2, T in the present embodiment
The AP controller is the conventional TAP shown in FIG.
Similar to the controller, the decoder 13 and the DFFs 15 to 18
And DFFs 24 to 27, inverters 14 and 23, NAND gates 19 to 22, 28, 30 and AND gate 2.
9 and 31. In this embodiment, in addition to these, DFF
A state detection circuit 33 that monitors the outputs of 15 to 18 to detect the run test / idle state, a detection output 34 of the state detection circuit 33, a test reset input inversion signal TRST inversion, and a test clock input. And a clock generation circuit 50 that outputs a predetermined number of pulses as the run clock signal 12 in the run test / idle state based on the inversion signal TCK inversion.

The clock generation circuit 50 constitutes two flip-flop (FF) circuit sections. The first FF circuit unit includes an inverter 35, an OR gate 37, a NAND
It is composed of gates 36 and 38, AND gate 39, and NOR gates 40 and 41.
The detection output 34 indicating the test / idle state, the TCK inverted signal, the reset signal 49 and the reset inverted signal 48 for the run clock signal 12 are input,
Only when the TAP controller is in the run test / idle state, the system clock for supplying to the boundary cell 3 connected to the system clock terminal T1 is output as the run clock signal 12 only once. The second FF circuit section includes an inverter 35 and an AND gate 42.
, NOR gates 43 and 44, OR gate 45, N
TRS which is composed of AND gates 46 and 47 and is inputted as a set signal for initializing the TAP controller
The T inversion signal, the detection output 34 indicating that the TAP controller is in the run test / idle state, and the TCK inversion signal are input, and a reset signal 49 and a reset inversion signal 48 for resetting the first FF circuit unit are input. Output. It should be noted that although the respective gates configuring these FF circuit units have been described as independent elements, the present invention is not limited to this and may be configured by a composite gate.

FIG. 3 is an operation timing chart of the TAP controller shown in FIG. As shown in FIG. 3, 4-bit data in each state of the TAP controller 10 is the values of the A inverted signal, the B inverted signal, the C signal, and the D signal which are the outputs of the DFFs 15 to 18, respectively from the lower order. First, when the TAP controller 10 enters the run test / idle state by the test mode selection input TMS as a control signal, the run clock signal 12 rises at the first fall of the TCK signal. Next, TCK
The rising edge of the signal causes the run clock signal 12 to fall. Run clock signal 12 under any other conditions
Is fixed to "0" and does not change. That is, the TAP controller 10 in this embodiment outputs the clock signal only once in the run test / idle state as the run clock signal 12.

As described above, in this embodiment, the run clock signal 12 generated by the TAP controller 10 is INT.
Outputs to the boundary cell 3 connected to the system clock terminal T1 when the EST instruction is executed, and the run clock signal 12 is output from the boundary cell 3 when the INTEST instruction is executed.
Is output to the internal circuit 2, the execution of the INTEST instruction can be realized without using an external selection circuit and without using an external INTEST clock or a selection signal.

FIG. 4 is a circuit diagram of a main part of a TAP controller in an LSI for explaining another embodiment of the present invention. As shown in FIG. 4, in this embodiment, the configuration of the clock generation circuit 50 in the TAP controller 10 is changed as compared with the above-described one embodiment. That is, the clock generation circuit 50 of the TAP controller 10 in this embodiment is provided with a third FF circuit section including an AND gate 51, NOR gates 52 and 53, an OR gate 54, and NAND gates 55 and 56. This enables the run
The clock signal 12 can be generated from 1 pulse to 2 pulses.

FIG. 5 is an operation timing chart of the main part of the TAP controller shown in FIG. As shown in FIG. 5, in this embodiment, the run clock signal 12 is generated twice when the TAP controller 10 is in the run test / idle state.

By adding the FF circuit section, more pulses can be generated.

[0023]

As described above, the present invention provides a TAP that realizes a plurality of states including a run test / idle state.
The TEST instruction can be executed by sending a run clock signal from the TAP controller to a boundary cell that has a controller and inputs the system clock in the run test / idle state. There is an effect that an additional selection circuit and the like can be made unnecessary, and wiring and the like can be made economical.

[Brief description of drawings]

FIG. 1 is a block diagram of an L having a built-in controller according to an embodiment of the present invention.
It is a block diagram of SI.

FIG. 2 is a circuit diagram of the TAP controller in FIG.

FIG. 3 is an operation timing chart of the TAP controller shown in FIG.

FIG. 4 is a circuit diagram of a main part of a TAP controller in an LSI for explaining another embodiment of the present invention.

5 is an operation timing chart of a main part of the TAP controller shown in FIG.

FIG. 6 is a block diagram of an LSI with a built-in controller, showing a conventional example.

FIG. 7 is a circuit diagram of the TAP controller in FIG.

[Explanation of symbols]

 1 LSI with built-in controller 2 Internal circuit 3 to 8 Boundary cell 9 Boundary scan register 10 TAP controller 11 System clock 12 Run clock signal 13 Decoder 15 to 18, 24 to 27 DFF 33 State detection circuit 50 Clock generation circuit

Claims (3)

[Claims] 1. A boundary scan register composed of a plurality of boundary cells capable of executing an in-test instruction of an internal circuit, a decoder, a flip-flop and the like are used to output various control signals to the outside and run Test that realizes multiple states including test / idle state
And a controller for access port,
In the test / idle state, the test access
Boundary scan from the port controller
An LSI with a built-in controller that sends a run clock signal to a boundary cell that inputs the system clock of a register. 2. The test access port controller includes a state detection circuit for detecting that the run test / idle state is present, and the run detection circuit based on the output of the state detection circuit, a test clock input, and a reset signal. The LSI with a built-in controller according to claim 1, further comprising a clock generation circuit that outputs a predetermined number of pulses in a test / idle state. 3. The LSI with a built-in controller according to claim 1, wherein the boundary cell for inputting the system clock of the boundary scan register has a multiplexer function.