JPH10307167A - Testing device for logic integrated circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To reduce an overhead and facilitate testing by constituting a scan pass circuit supplying clock pulse series for scanning to a clock input terminal of F/F with a switching circuit and performing data scanning operation. SOLUTION: A testing device (LSI tester) supplies an operation mode input pin SMC with a logic '1' level signal in the case a logic integrated circuit 8 is set at a test operation mode. At this moment, selector circuits 1 and 2 connect a clock input pin CLK1 to clock input terminals of F/F 7 to 3. Then, a scan pass circuit is constituted capable of observing test data with a data output pin SOT by supplying the CLK1 with a clock pulse series for scanning from the testing device to operate the F/F 7 to 3 and shifting the data from data input pin SIN to the F/F 7 to 3. By this, testing is easily done in the state an overhead delaying the test and an area overhead are reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large scale logic integrated circuit, and more particularly to a test apparatus using a scan path of the large scale logic integrated circuit.

[0002]

2. Description of the Related Art Since a sequential circuit inside a large-scale logic integrated circuit is more difficult to test than a combinational circuit, a logical design incorporating various test facilitation designs has been conventionally performed. Among them, a scan path circuit that can directly apply or observe data from an external terminal to an F / F (flip-flop) in a sequential circuit is widely used.

When designing a scan path for a large-scale integrated circuit operable with a plurality of clocks having different phases (ie, a multi-phase clock), a method of adding an additional circuit for integrating the scan clocks into one is usually used. Has been adopted.

If additional circuits cannot be added due to delay constraints, area constraints, or the like, a clock having the largest number of F / Fs to be operated out of a plurality of clocks or a clock having an F / F that is difficult to detect a failure is operated. Therefore, restrictions such as designing a scan path for facilitating test are imposed.

Japanese Patent Application Laid-Open No. 6-66897 describes a logic integrated circuit capable of testing all clock signals without a problem of clock skew in a scan path capable of handling a multi-phase clock. The logic circuit tests a logic integrated circuit having a multi-phase clock by combining a dedicated test clock and a latch circuit in addition to a clock used in a normal logic operation in a scan test.

[0006]

When a logic integrated circuit designed with a multi-phase clock is tested by using a scan path, in order to easily adjust a clock skew and to guarantee a hold, as described above, a dedicated circuit is used. A method has been proposed in which an additional circuit is added to cope with this. According to this method,
There is a problem that the design burden on the delay overhead and the area overhead of the dedicated additional circuit is large, and it is difficult to adopt a logic circuit that requires high-speed operation.

SUMMARY OF THE INVENTION An object of the present invention is to provide a test apparatus for a logic integrated circuit which can easily perform a test with reduced delay overhead and area overhead.

[0008]

According to the present invention, there is provided a test apparatus for testing a logic integrated circuit having first and second flip-flops (5 and 4). First and second clock input pins (CLK1 and CLK2), provided in the logic integrated circuit, and in a normal operation mode, the first and second clock input pins are connected to the first and second flip-flops And a clock input pin switching circuit (1 and SMC) for connecting the first clock input pin to the clock input terminals of the first and second flip-flops in a test operation mode. ,
In a normal operation mode, first and second clock pulses having phases different from each other are supplied to the first and second clock input pins, respectively. In a test operation mode, a scan clock signal is supplied to the first clock input pin. Test means for supplying a clock pulse train, provided in the logic integrated circuit;
A scan path circuit that causes the first and second flip-flops to perform a data scanning operation with the scan clock pulse train supplied to the clock input terminals of the first and second flip-flops in a test operation mode. (SIN to SOT) are obtained.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a diagram for explaining a test apparatus for a logic integrated circuit according to one embodiment of the present invention. This test apparatus includes first and second F / Fs (flip-flops) 5
And the logic integrated circuit 8 having the other F / Fs 3, 7, and 6 is tested. The logic integrated circuit 8
Typically, it is a large scale integrated circuit (LSI).

This test apparatus includes first, second, and third clock input pins CL provided on a logic integrated circuit 8.
K1, CLK2 and CLK3, an operation mode input pin SMC, a data input pin SIN, and a data output pin SMC.
OT, selector circuits 1 and 2, and the logic integrated circuit 8
And a test machine (not shown) used in combination with This tester is typically an LSI tester.

The tester supplies a logic "0" level signal to an operation mode input pin SMC when the logic integrated circuit 8 is in the normal operation mode, and outputs a logic "0" signal when the logic integrated circuit 8 is in the test operation mode. A "1" level signal is supplied to the operation mode input pin SMC.

The first clock input pin CLK1 is connected to a clock input terminal of the first F / F 5 by a signal line.

The selector circuit 1 has an operation mode input pin S
In the normal operation mode in which the MC is supplied with the logic "0" level signal, the second clock input pin CLK2 is connected to the clock input terminal of the second F / F4 and the clock input terminal of the F / F3. In the test operation mode in which the operation mode input pin SMC is supplied with a logic "1" level signal, the first clock input pin CLK1 is connected to the second F / F
4 and a clock input terminal of F / F3.

The selector circuit 2 has an operation mode input pin S
In the normal operation mode in which the MC is supplied with the logic "0" level signal, the third clock input pin CLK3 is set to the F level.
/ F7 and 6 in the test operation mode in which the operation mode input pin SMC is supplied with a logic "1" level signal, the first clock input pin CL
K1 is connected to the clock input terminals of the F / Fs 7 and 6.

When the tester puts the logic integrated circuit 8 into the normal operation mode, the tester supplies the logic "0" level signal to the operation mode input pin SMC as described above, and outputs the first, second, and second signals. 3 clock input pins CLK1, CL
First, second, and third clock pulses (described later) having different phases from each other are supplied to K2 and CLK3, respectively.

When the tester puts the logic integrated circuit 8 into the test operation mode, the tester supplies the logic "1" level signal to the operation mode input pin SMC as described above.
A scan clock pulse train (described later) is supplied to the first clock input pin CLK1.

Data input pin SIN, connection between data input pin SIN and F / F7, connection between F / F7 and 6, connection between F / F6 and 5, F / F5 and 4, the connection between F / Fs 4 and 3, and the F / F
3 and the data output pin SOT, and the data output pin SOT are connected to the F / F7 to F / F7 in the test operation mode.
A scan path circuit that causes the F / Fs 7 to 3 to perform a data scan operation with the scan clock pulse train supplied to the clock input terminal 3 is provided.

In this structure, when the logic integrated circuit 8 enters the test operation mode, the first clock input pin CLK1
All the F /
F7-3 operate, and the data input pin SIN
To F / F7, F / F6, F / F5, F / F4, F / F
3, a scan path circuit is provided which can shift the data and observe the data cystted at the data output pin SOT.

Next, the operation of the above-described test machine will be described with reference to FIG. 2 in addition to FIG.

The tester performs a first test cycle (FIG. 2).
In the first cycle, a logic "1" level signal is supplied to the operation mode input pin SMC in the test operation mode, and the scan clock as shown in the drawing is applied to the first clock input pin CLK1. A pulse train is supplied, whereby a scan clock pulse train is supplied to clock input terminals of the F / Fs 7 to 3, and the scan path is set to set data (ie, scan-in) to the F / Fs 7 to 3 with the scan clock pulse train. It has a first test function for controlling the circuit.

In a second test cycle (a cycle indicated as normal operation in FIG. 2) following the first test cycle, the tester further outputs a logic "0" level signal to the operation mode input pin SMC. To set the first clock input pin CLK1 in the normal operation mode.
Supplies a first clock pulse having a shorter pulse width than the duration of the second test cycle, thereby providing F /
This first clock pulse is supplied to the clock input terminal of F5, and then, during the second test cycle, a second test cycle is applied to the second clock input pin CLK2 following the first clock pulse. And a second clock pulse having a pulse width shorter than the period of the second clock signal is supplied to the clock input terminals of the F / Fs 4 and 3.
Finally, within the second test cycle, following the second clock pulse, the third clock input pin CLK3 has a shorter pulse width than the duration of the second test cycle. It has a second test function of supplying a third clock pulse, and thereby supplying this third clock pulse to the clock input terminals of the F / Fs 7 and 6.

In this case, in the second test cycle,
First, second, and third clock pulses of the first, second, and third clock pulses
The timing of application to the third clock input pins CLK1, CLK2, and CLK3 is determined by a test program (PR) that controls the test machine as shown in the lower part of FIG.
OG) must be specified in detail. For example, the first clock input pin CLK1 in the second test cycle
The application timing of the first clock pulse to the
The timing at which the signal is changed to “1” at s and returned to “0” at 20 ns is defined in the tester program. Further, the application timing of the second clock pulse to the second clock input pin CLK2 in the second test cycle is changed to “1” in 30 ns and “0” in 40 ns.
The timing to return to the test is defined in the tester program. The application timing of the third clock pulse to the third clock input pin CLK3 in the second test cycle is changed to “1” in 50 ns to 60 ns
The timing for returning to “0” is defined in the tester program. A multi-phase clock test can be realized by considering the skew between tester pins when defining this timing.

The tester further outputs a logic "1" to the operation mode input pin SMC in a third test cycle (the cycle indicated as the last scan operation in FIG. 2) following the above-mentioned second test cycle. A first clock input pin CL is supplied by supplying a level signal to the test operation mode.
A scan clock pulse train as shown is supplied to K1, thereby supplying a scan clock pulse train to the clock input terminals of the F / Fs 7 to 3, and scanning out the data of the F / Fs 7 to 3 with the scan clock pulse train. A third test function is provided for controlling the scan path circuit as much as possible. As described above, the test using the scan path is realized by sequentially setting the data values of the F / Fs 7 to 3 by setting the SCM to the test operation mode with the logic "1" level signal.

[0025] The tester is capable of performing the above-described first, second, and third tests.
Are sequentially repeated until a failure in the logic integrated circuit 8 is found.

As described above, when the normal operation mode is set, an LSI test having a multi-phase clock can be performed by defining the timing of applying three different clock pulses in consideration of the skew between pins of the tester. Become.

Next, another operation of the above-described test machine will be described with reference to FIG. 3 in addition to FIG. This other operation is the same as the operation of FIG. 2 except for the following points.

That is, in the second test cycle subsequent to the first test cycle (the cycle initially indicated as normal operation in FIG. 3), the tester applies a logic "L" to the operation mode input pin SMC. A first clock pulse having a pulse width shorter than the period of the second test cycle is supplied to the first clock input pin CLK1 in the normal operation mode by supplying a 0 "level signal, whereby the F / F 5 The first clock pulse is supplied to the clock input terminal, and the operation is also performed in a third test cycle subsequent to the second test cycle (the cycle indicated as the second normal operation in FIG. 3). A logic "0" level signal is supplied to the mode input pin SMC to set the second clock input pin CL to the normal operation mode.
K2 is supplied with a second clock pulse having a shorter pulse width than the duration of the third test cycle, whereby this second clock pulse is supplied to the clock input terminals of the F / Fs 4 and 3, and finally Also in the fourth test cycle following the third test cycle (the cycle indicated as the last normal operation in FIG. 3), a pulse shorter than the period of the fourth test cycle is applied to the third clock input pin CLK3. It has a second test function of supplying a third clock pulse having a width, and thereby supplying this third clock pulse to the clock input terminals of the F / Fs 7 and 6.

The first, second, and third clock input pins CLK1, CLK1, of the first, second, and third clock pulses in the second, third, and fourth test cycles described above.
The timing of application to CLK2 and CLK3 is shown in FIG.
As shown in the lower part of the figure, the timing for changing the value to "1" in 10 ns and returning to "0" in 20 ns may be defined in the tester program (PROG). This is because the application of each clock pulse is performed in another test cycle, so that the application timing of the clock pulse can be distinguished in the test cycle. For this reason, there is an advantage that the skew adjustment in the tester becomes unnecessary. In addition, in the case of FIG. 2, the clock pulse application order is fixed to the order specified first, whereas in the case of FIG. 3, the clock pulse application order is arbitrary, so that a clock pulse advantageous for failure detection is applied. It becomes possible.

The tester further outputs a logic "1" to the operation mode input pin SMC in the fifth test cycle (the cycle indicated as the last scan operation in FIG. 3) following the fourth test cycle described above. A first clock input pin CL is supplied by supplying a level signal to the test operation mode.
A scan clock pulse train as shown is supplied to K1, thereby supplying a scan clock pulse train to the clock input terminals of the F / Fs 7 to 3, and scanning out the data of the F / Fs 7 to 3 with the scan clock pulse train. A third test function is provided for controlling the scan path circuit as much as possible.

Next, still another operation of the above-described test machine will be described with reference to FIG. 4 in addition to FIG. This further operation is the same as the operation of FIG. 3 except for the following points.

That is, in the second test cycle following the first test cycle (the cycle initially indicated as a normal operation in FIG. 4), the tester also applies the logic "L" to the operation mode input pin SMC. A first clock pulse having a pulse width shorter than the period of the second test cycle is supplied to the first clock input pin CLK1 in the normal operation mode by supplying a 0 "level signal, whereby the F / F 5 The first clock pulse is supplied to the clock input terminal. Then, in the third test cycle (the cycle indicated as the second normal operation in FIG. 4) subsequent to the second test cycle, the operation is performed. A logic "0" level signal is supplied to the mode input pin SMC to set the second clock input pin CL to the normal operation mode.
K2 is supplied with a second clock pulse having a pulse width equal to the duration of the third test cycle, whereby F2
This second clock pulse is supplied to the clock input terminals of / F4 and / F4, and finally a fourth test cycle following the third test cycle (a cycle finally indicated in FIG. 4 as a normal operation). Also supplies a third clock pulse having a pulse width equal to the period of the fourth test cycle to the third clock input pin CLK3,
This has a second test function of supplying the third clock pulse to the clock input terminals of the F / Fs 7 and 6.

As described above, the second and third clock input pins CL in the third and fourth test cycles are used.
The application of the second and third clock pulses to K2 and CLK3 is similar to the application of the logic "1" level signal to the operation mode input pin SMC in the first and fifth test cycles. By performing the test over the fourth test cycle period, the clock pulse specified in the test program (PROG) of the tester can be used as a clock pulse shown in FIG.
As shown below, as only the first clock pulse to the first clock input pin CLK1 in the second test cycle, the clock pulses to CLK2 and CLK3 are treated in the same manner as ordinary signals, so that these clocks can be used. There is an advantage that it is not necessary to define the pulse application timing, and the test program can be shared with the program at the time of the scan test of the single clock pulse.

As described above, according to the present invention, a logic integrated circuit having a multi-phase clock can be easily tested by considering the clock application method and timing.

[0035]

As described above, according to the present invention, a test apparatus for a logic integrated circuit which can easily perform a test with reduced delay overhead and area overhead is obtained.

[Brief description of the drawings]

FIG. 1 is a diagram for explaining a test apparatus for a logic integrated circuit according to an embodiment of the present invention.

FIG. 2 is a timing chart for explaining the operation of a tester in a test apparatus for a logic integrated circuit according to an embodiment of the present invention.

FIG. 3 is a timing chart for explaining another operation of the tester in the test apparatus for a logic integrated circuit according to one embodiment of the present invention.

FIG. 4 is a timing chart for explaining still another operation of the tester in the test apparatus for a logic integrated circuit according to one embodiment of the present invention.

[Explanation of symbols]

 Reference Signs List 1 selector circuit 2 selector circuit 3 to 7 F / F (flip-flop) 8 logic integrated circuit CLK1 clock input pin CLK2 clock input pin CLK3 clock input pin SMC operation mode input pin SIN data input pin SOT data output pin

Claims (4)

[Claims] 1. A test apparatus for testing a logic integrated circuit having first and second flip-flops (5 and 4), comprising: a first and a second clock input pin (CLK1) provided in the logic integrated circuit. And CLK2) provided in the logic integrated circuit, and in the normal operation mode, connecting the first and second clock input pins to clock input terminals of the first and second flip-flops, respectively. A clock input pin switching circuit (1 and SMC) for connecting the first clock input pin to a clock input terminal of the first and second flip-flops in a test operation mode; And first and second clock pulses having different phases from each other are supplied to the second clock input pin, respectively. Test means for supplying a scan clock pulse train to a first clock input pin; and said test means being provided in the logic integrated circuit and being supplied to the clock input terminals of the first and second flip-flops in a test operation mode. A scan path circuit (SIN) that causes the first and second flip-flops to perform a data scan operation with a scan clock pulse train.
To SOT), a test apparatus for a logic integrated circuit. 2. The test means supplies the scan clock pulse train to the first clock input pin as the test operation mode in a first test cycle, thereby providing the first and second flip-flops. A first test for supplying the scan clock pulse train to the clock input terminal and controlling the scan path circuit to scan data into the first and second flip-flops with the scan clock pulse train. Means, and in the second test cycle subsequent to the first test cycle, as the normal operation mode, the first clock input pin having a pulse width shorter than a period of the second test cycle at the first clock input pin. Of the first flip-flop. Supplying the first clock pulse to the clock input terminal of the clock and the second test input to the second clock input pin following the first clock pulse during the second test cycle. Providing said second clock pulse having a pulse width shorter than the duration of a cycle;
Thereby, the second clock pulse for supplying the second clock pulse to the clock input terminal of the second flip-flop is provided.
And in a third test cycle following the second test cycle, the scan clock pulse train is supplied to the first clock input pin as the test operation mode, whereby the first and the second And supplying the scan clock pulse train to the clock input terminal of the second flip-flop and controlling the scan path circuit to scan out the data of the first and second flip-flops with the scan clock pulse train. 3. The method according to claim 1, further comprising: third test means, wherein the sequential operation of the first, second, and third test means is repeated until a failure in the logic integrated circuit is found. A test apparatus for a logic integrated circuit according to claim 1. 3. The test means supplies the scan clock pulse train to the first clock input pin as the test operation mode in a first test cycle, whereby the first and second flip-flops are provided. A first test for supplying the scan clock pulse train to the clock input terminal and controlling the scan path circuit to scan data into the first and second flip-flops with the scan clock pulse train. Means, and in the second test cycle subsequent to the first test cycle, as the normal operation mode, the first clock input pin having a pulse width shorter than a period of the second test cycle at the first clock input pin. Of the first flip-flop. The first clock pulse is supplied to the clock input terminal of the second clock cycle, and the third test cycle following the second test cycle is also set to the normal operation mode so that the third clock cycle is applied to the second clock input pin. A second test means for supplying the second clock pulse having a pulse width shorter than the duration of the test cycle, thereby supplying the second clock pulse to the clock input terminal of the second flip-flop. In a fourth test cycle following the third test cycle, the scan clock pulse train is supplied to the first clock input pin as the test operation mode, whereby the first and second flip-flops are provided. When the scan clock pulse train is supplied to the clock input terminal of the And third test means for controlling the scan path circuit to scan out the data of the first and second flip-flops with the scan clock pulse train. The first, the second, and 2. The test apparatus for a logic integrated circuit according to claim 1, wherein the sequential operation of the third test means is repeated until a failure in the logic integrated circuit is found. 4. The test means supplies the scan clock pulse train to the first clock input pin as the test operation mode in a first test cycle, thereby providing the first and second flip-flops. A first test for supplying the scan clock pulse train to the clock input terminal and controlling the scan path circuit to scan data into the first and second flip-flops with the scan clock pulse train. Means, and in the second test cycle subsequent to the first test cycle, as the normal operation mode, the first clock input pin having a pulse width shorter than a period of the second test cycle at the first clock input pin. Of the first flip-flop. The first clock pulse is supplied to the clock input terminal of the second clock cycle, and the third test cycle subsequent to the second test cycle is set to the normal operation mode, and the third clock cycle is applied to the second clock input pin. A second test means for supplying the second clock pulse having a pulse width equal to the duration of the test cycle, thereby supplying the second clock pulse to the clock input terminal of the second flip-flop; In a fourth test cycle following the third test cycle, the scan clock pulse train is supplied to the first clock input pin as the test operation mode, whereby the first and second flip-flops are supplied. Supplying the scan clock pulse train to the clock input terminal of And third test means for controlling the scan path circuit to scan out the data of the first and second flip-flops with the scan clock pulse train, wherein the first, second, and 2. The test apparatus for a logic integrated circuit according to claim 1, wherein the sequential operation of the third test means is repeated until a failure in the logic integrated circuit is found.