JPH06148293A - Test circuit for logical circuit - Google Patents

Abstract

PURPOSE:To more easily specify the max. operation frequency (delay time) and max. delay route of the logical circuit of a circuit to be tested without using a special testing device. CONSTITUTION:The input signals Y1-Yi to a circuit 20 to be tested at the time of testing are stored in flip-flops 11. These signals are inputted to the circuit 20 to be tested in synchronous relation to a start clock signal CKS by start gate circuits 13. Thereafter, the output signals W1-Wj from the circuit 20 to be tested are stored in flip-flops 12 on an output side in synchronous relation to an end clock signal CKE. The start clock signal CKS and the end clock signal CKE are generated in a clock control circuit 15. On the basis of the time from the start clock signal CKS to the end clock signal CKE, the delay time of the circuit 20 to be tested can be specified.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a logic circuit test circuit capable of more easily specifying a maximum operating frequency (delay time) and a maximum delay path of a logic circuit of a circuit under test.

[0002]

2. Description of the Related Art Conventionally, the maximum operating frequency of a logic circuit of a circuit under test has been specified by a simulation or an actual circuit test. This maximum operating frequency depends on the operation delay time of the circuit under test, and is the highest frequency at which normal operation can be performed. For example, when the circuit under test is a synchronous logic circuit operating according to a predetermined clock signal, the maximum operating frequency is the maximum frequency of the clock signal at which the circuit under test can operate normally.

In the simulation and the actual circuit test, which are carried out to specify the maximum operating frequency of the logic circuit of the circuit under test as described above, a test pattern vector consisting of a large number of test patterns is to be tested. The circuit under test is input while being executed at various operating speeds, and it is determined whether or not the execution result is as expected. Therefore, such a test requires not only a large number of test patterns to be executed but also a similar test repeatedly at various frequencies, which requires a lot of time and labor. There's a problem. Further, in the test, much effort is required to obtain a normal execution result in advance. Further, in order to compare such a normal execution result with the test result of the circuit under test, a special test device is needed.

Therefore, conventionally, various techniques relating to the logic circuit delay time of the circuit under test, which can reduce such labor and time, have been disclosed.

For example, in Japanese Patent Laid-Open No. 2-41572, a synthesis rule of a functional block stored in a synthesis rule base is input with a hardware description language at a register transfer level or a specification of a synchronous logic circuit given by a functional block diagram as an input. There is disclosed a technique related to a logic circuit synthesizing method including a logic circuit synthesizing unit that synthesizes a detailed logic circuit according to the above and outputs a netlist and a synthesis rule list applied to each functional block. The Japanese Unexamined Patent Publication No. 2-41572 has a delay analysis unit that performs delay analysis using the netlist as an input and outputs an error path list when there is a maximum delay error. Further, when there is a maximum delay error by the delay analysis of the delay analysis unit, the synthesis rule list and the error path list are input to extract a critical functional block on the error path, A critical block extraction unit for instructing the logic circuit synthesis unit to perform synthesis again is provided. According to the Japanese Patent Laid-Open No. 2-41572, it is possible to configure a logic circuit in which the number of gates and the maximum delay time are reduced.

Further, Japanese Patent Application Laid-Open No. 2-105232 discloses a technique relating to analysis of logic operation in a logic circuit after completion of gate level logic design. The Japanese Patent Laid-Open No. 2-1
In 05232, the connection relation of each element in the logic circuit and the information of the minimum delay time and the maximum delay time which are indicators of the operating speed of each element are constructed as a data structure in the storage area on the electronic computer. I have to. A logic simulation means for simultaneously performing a logic simulation with the minimum delay time and a logic simulation with the maximum delay time based on test vector information applied to the logic circuit is provided. Further, it has a typical value calculating means for calculating a typical value of each element in the logic circuit from the two logic simulations. From the typical value obtained from the typical value calculating means, the logical operation of each element in the logic circuit and the temporal operation thereof are analyzed. According to the technique disclosed in Japanese Patent Laid-Open No. 105232/1990, it is possible to clearly handle the output state transition of each logic element and detect a malfunctioning portion due to a timing shift. Furthermore, transition states, R, F
It is possible to provide a method of verifying the operation of a logic circuit that does not require an unclear operation definition of the logic element with respect to

Further, Japanese Patent Application Laid-Open No. 3-75875 discloses a technique of performing simulation with a 0 delay or a unit delay by using an input pattern in a delay simulator of a logic circuit. JP-A-3-
In 75875, based on the simulation result,
The activated path is detected, and the critical path having the maximum delay and the minimum delay is obtained based on the element delay on the activated path and the wiring delay between the elements. According to the Japanese Patent Laid-Open No. 3-75875, it is possible to find the critical path delay of the maximum delay and the minimum delay with a shorter processing time and a smaller memory capacity.

Further, in Japanese Patent Laid-Open No. 3-286376, means for automatically generating a test vector for logic simulation from circuit data describing connection information between respective elements of a logic circuit, and each of the test vectors are flown. Prior to the above, there is provided means for bringing all the signal lines of the logic circuit into an indefinite state. Further, there are provided means for executing a simulation of the logic circuit using the test vector, and means for analyzing a simulation result to obtain a maximum delay. According to the Japanese Patent Laid-Open No. 3-286376, it is possible to detect the true maximum delay and maximum delay path more efficiently than ever before.

On the other hand, conventionally, in order to facilitate the test of the operation of the integrated circuit, a test method called a scan path method using, for example, a boundary scan register is often used. This is to use a scan path register such as the boundary scan register for inputting or outputting a circuit under test such as a user circuit, setting a logical state of a net in the circuit, or reading the logical state. .

The scan path register is connected to a portion for setting the logical state and reading the logical state as described above. Further, a large number of scan path registers connected in this way are configured as one long shift register by switching the multiplexer provided therein when setting the logical state thereof. Therefore, the logical state of each scan path register can be set by inputting a serial data pattern to the shift register.

On the other hand, when reading out the logical state of each of the scan path registers, the multiplexer inside the switch is switched to constitute one long shift register. The logical states stored in the shift register are serially shifted. As a result, the logical states of the individual scan path registers can be sequentially read from the outside.

FIG. 8 is a circuit diagram of a part of an integrated circuit incorporating a conventional scan path register.

In FIG. 8, a total of three flip-flops incorporated in the integrated circuit, that is, a total of three scan path registers indicated by reference numerals F1 to F3 in FIG. 8 and a predetermined logic circuit. And the combinational circuit 20 of FIG. In the scan path test method, the logic circuit is thus divided into the sequential circuit and the combinational circuit for testing.

The combinational circuit is such that when its input is determined, its output is immediately determined. The output at this time is determined by the combination of the gates,
It can be expressed by a predetermined logical expression. Therefore, the combinational circuit can be tested relatively easily using its logic equation. On the other hand, in the sequential circuit, since the flip-flops are connected to each other or the flip-flop and the combination circuit are connected in a complicated manner, the output state cannot be expressed by a simple logical expression. Therefore, testing such a sequential circuit is very difficult.

Therefore, in the scan path test method, a predetermined multiplexer is added to the input parts of all the flip-flops in the circuit to be tested, and the multiplexer is switched between the "normal mode" and the "test mode". Test by. Normally, this multiplexer is put in the normal mode. On the other hand, during testing,
By switching to the test mode, all flip-flops become one shift register as described above. In this way, by switching the selectors, as shown in FIG.
All flip-flops (reference numerals F1 to F3 in FIG. 8)
Can be divided into one shift register in which is connected.

First, during the normal operation, the output signal W1
To W3 are input from the combinational circuit 20 to the scan path registers F1 to F3. Further, during the normal operation, signals Y1 to Y1 are output from the scan path registers F1 to F3.
Y3 is input to the combination circuit 20 again. on the other hand,
In the test mode, the scan path registers F1 to F3 of the logic circuit in the integrated circuit are connected to each other to form a shift register structure.

Note that such a scan path register F
1 to F3 are multiplexers 32 as shown in FIG.
And a typical bistable flip-flop 34. The multiplexer 32 connects the shift input SI to the input D of the flip-flop 34 when the test mode selection signal S1 is "1" (test mode). On the other hand, when the test mode selection signal S1 becomes "0", the multiplexer 32 connects the data input D1, that is, one of the signals W1 to W3 to the input D of the flip-flop 34.

The test of the logic circuit incorporated in the integrated circuit shown in FIGS. 8 and 9 can be performed as follows.

Specifically, first, in order to test the combinational circuit 20, the test mode selection signal S1 is set to "1".
(Test mode) is set, and a predetermined test pattern is serially input from the shift input SDI. As a result, the test pattern input from the scan path registers F1 to F3 is set to the combinational circuit 20.

After that, the test mode selection signal S1 is set to "0" to set the test normal operation mode, and after the logic state of the circuit is stabilized, the clock signals CK are input to change the signals W1 to W3. Campus register F
Write in 1 to F3. Then, the test mode selection signal S1 is set to "1" again to return to the test mode, and the scan path registers F1 to F1 are output from the shift output SDO.
The contents of 3 are sequentially read.

[0021]

However, the above-mentioned JP-A-2-41572, JP-A-2-105232, JP-A-3-75875, and JP-A-3-28637.
6 is related to the simulation of the logic circuit, and the delay time and the like are calculated by the simulation. Therefore, all of them use a special test device. For example,
In Japanese Patent Laid-Open No. 2-41572, there is provided a delay analysis unit for inputting a netlist for delay analysis and outputting an error path list when there is a maximum delay error.

The present invention has been made to solve the above-mentioned conventional problems, and the maximum operating frequency (delay time) and the maximum delay path of the logic circuit of the circuit under test can be achieved without using a special test device or the like. It is an object of the present invention to provide a logic circuit test circuit that can more easily specify a logic circuit.

[0023]

The present invention provides an input side flip-flop for storing and holding a test input signal TI, and an input side flip-flop for storing and holding the test input signal TI.
A start gate circuit that is input to the circuit under test in synchronization with the start clock signal CKS, and a test output signal TO from the circuit under test are synchronized with the end clock signal CKE after inputting in synchronization with the start clock signal CKS. The above-described object is achieved by providing an output side flip-flop for storing and holding, and a clock control circuit for outputting the end clock signal CKE after a predetermined test set time after outputting the start clock signal CKS. It is a thing.

Also, in the logic circuit test circuit, the input side flip-flop and the output side flip-flop are a single flip-flop in which a multiplexer is connected to the input, and thus the same problem is solved. In addition to achieving the above, the number of elements used is further reduced.

Further, in the logic circuit test circuit, the single flip-flop uses a scan path register, thereby achieving the above-mentioned object, reducing the number of elements used, and reducing the number of elements already used. It is easier to apply to those using campus registers.

[0026]

[Function] Conventionally, the maximum operating frequency (delay time) of a logic circuit
As described above, the maximum delay path was performed by using various special test devices during the simulation. In the present invention, the logic circuit test circuit for specifying the maximum operating frequency and the maximum delay path is temporarily or permanently incorporated into the logic circuit itself of the circuit under test, which is not the conventional method. It is based on different points of interest. Therefore, no special test equipment is required.

FIG. 1 is a block diagram showing the gist of the present invention.

In FIG. 1, the circuit under test 20 is i
It has book input signal lines Y1 to Yi. The circuit under test 20 has j output signal lines W1 to Wj. In such a circuit under test 20, the delay time is from the input of a predetermined signal pattern to the input signal lines Y1 to Yi until the logical state of the output signal lines W1 to Wj becomes a steady state. It's time. Further, the operating frequency at which such a delay time is secured becomes the maximum operating frequency. Further, of the output signal lines W1 to Wj, the one whose logical state is the last is the steady state is the maximum delay path.

In FIG. 1, the input signal lines Y1 ...
Yi has an input side flip-flop 11 and
The start gate circuit 13 is connected. That is, in FIG. 1, the total of the input side flip-flops 11 and the start gate circuits 13 is i. An output side flip-flop 12 is connected to each of the output signal lines W1 to Wj.
Therefore, the total number of the output side flip-flops 12 is
It is j.

In FIG. 1, the clock control circuit 15 includes a start clock signal CKS input to all the input side flip-flops 11 and an end clock signal CKE input to all the output side flip-flops 12. And generate. The clock control circuit 15
Outputs the start clock signal CKS at the start of a test by a predetermined operation by a test operator, for example. Further, the clock control circuit 15 outputs the end clock signal CKE after a predetermined test setting time after outputting the start clock signal CKS. The predetermined test set time is set by a test operator or the like, and corresponds to the delay time of the circuit under test.

In the logic circuit test circuit of the present invention as described above, when the maximum operating frequency, the delay time and the maximum delay path of the circuit under test 20 are obtained, for example, the following procedure is performed.

First, first, the data patterns TI1 to TIi to be set at the start of the test are set to the input signal lines Y1 to Yi of the circuit under test 20 in the i-th input side flip-flops 11 in total. This may be sequentially set in each of these input side flip-flops 11. Alternatively, these input side flip-flops 11 may be configured like a shift register, and the above-mentioned data patterns may be serially set.

In this way, the data patterns TI1 to TI
When i is set, the test of the clock control circuit 15 is started by a predetermined operation. When the test is started, the clock control circuit 15 first outputs the start clock signal CKS. The start clock signal CKS is input to all the start gate circuits 13. When the start clock signal CKS is input, the start gate circuit 13 outputs the ones set in the input side flip-flop 11 to the corresponding input signal lines Y1 to Yi. The outputs to the input signal lines Y1 to Yi are simultaneously performed in an instant according to the start clock signal CKS.

As described above, when data is input to the input signal lines Y1 to Yi, the circuit under test 20 performs its predetermined operation. The result of this operation is output to the output signal lines W1 to Wj at any time.

After the start clock signal CKS is output, the end clock signal CKE is output from the clock control circuit 15 after the predetermined test setting time. When the end clock signal CKE is output, all the output side flip-flops 12 take in the logic states of the corresponding output signal lines W1 to Wj. Therefore,
The output states of the output signal lines W1 to Wj after the predetermined test setting time from the start clock signal CKS are stored in all the output side flip-flops 12.

Therefore, by comparing the stored contents of the output side flip-flop 12 stored in accordance with the end clock signal CKE with those in the case of normal operation, the circuit under test 2 is tested within the predetermined test set time.
It is possible to test whether 0 worked properly.
Further, by performing such a test a plurality of times with different predetermined test set times, it is possible to obtain the maximum operating frequency, the delay time, the maximum delay path, and the like.

As the input side flip-flop 11, a general bistable flip-flop can be used. Further, as the output side flip-flop 12, for example, a general T-type flip-flop or a D-type flip-flop having a clock input CK can be used. The output side flip-flop 12 needs to have at least a clock input CK which becomes a storage timing of the data.

The start gate circuit 13 may be constructed by using various logic gates such as an exclusive NOR gate as in the embodiment described later. Alternatively, for example, the start gate circuit 13 may be a T-type flip-flop, a D-type flip-flop, or the like, which includes at least a clock input CK serving as a storage timing thereof. When such a flip-flop is used as the start gate circuit 13, the start clock signal CKS is input to its clock input CK. When the start clock signal CKS is input to the clock input CK of the flip-flop used as the start gate circuit 13, the output of the input side flip-flop 11 is stored and the input timing of this start clock signal CKS is stored. Then, the output of the input side flip-flop 11 is output to the circuit under test 20.

Various kinds of flip-flops can be used as the input-side flip-flop 11 and the output-side flip-flop 12, and further, a certain input-side flip-flop 11 and a certain output-side flip-flop 12,
It may be a single flip-flop. By using a single flip-flop in this way, as in the embodiment described later, the number of elements used can be reduced.

Further, such a single flip-flop may be one that uses the scan path register as described above with reference to FIGS. 8 and 9, for example.
For example, the present invention may be applied in a scan path register as in the embodiment described later. This makes it possible to more easily apply the present invention to a device that already has a scanpath register.

[0041]

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 2 is a circuit diagram of an integrated circuit having a logic circuit test circuit to which the present invention is applied.

In this embodiment shown in FIG. 2, the logic circuit is composed of a combination circuit 20 and a total of three scan path registers 30. The present invention is particularly applied to these scan path registers 30.
Further, these scan path registers 30 are further provided with a selection signal S2 as compared with the conventional ones described with reference to FIG. 8 and FIG.

FIG. 3 is a circuit diagram of the scan path register used in this embodiment.

In FIG. 3, one of the scan path registers 30 shown in FIG. 2 is shown. As shown in FIG. 3, the scan path register 30 mainly includes a multiplexer 32, a flip-flop 34, an exclusive NOR 36, and another multiplexer 38.

The scan path register 30 of the present embodiment shown in FIG. 3 is different from the scan path register 30 shown in FIGS. 8 and 9 in that the exclusive NOR 3 is different.
6 and the multiplexer 38. The exclusive NOR 36 and the multiplexer 38 constitute the start gate circuit 13 as shown in FIG. 1 of the present invention.
Further, in this embodiment, the input side flip-flop 11 and the output side flip-flop 12 of FIG. 1 are a single flip-flop 34.

The operation of this embodiment will be described below with reference to the time charts of FIGS.

FIG. 4 is a time chart during normal operation.

In FIG. 4, at time t ₀ , the selection signals S1 and S2 are both "0".
As a result, the multiplexer 32 connects the data input D1 to which the output signal lines W1 to W3 are connected to the data input D of the flip-flop 34.
The multiplexer 38 also connects the output of the flip-flop 34 to Q3 to which the input signal lines Y1 to Y3 are connected. As a result, the time in FIG.
At the rising of the clock signal CLK at each of t ₁ to t ₈ , the data input D 1, that is, the output signal lines W 1 to W
The logic state of 3 is stored and is output as Q3.

FIG. 5 is a time chart at the start of the test of this embodiment.

At time t ₀ in FIG. 5, the selection signal S1 becomes "1" and the selection signal S2 becomes "0", so that a total of three scan path registers 30 function as shift registers. Come to do. Thereafter, at time t ₁ ~ t _8, the clock signal CL
As K is sequentially input, the shift data input SD
Test data patterns are sequentially input from I. Further, accordingly, the output Q3 of each scan path register 30 changes according to the data sequentially input to the shift data input SI of each scan path register 30. The operation as such a shift register is
The process is repeated until the test data patterns for all the scan path registers 30 are set.

FIG. 6 is a time chart at the start of test path formation in this embodiment.

When desired data is set in all of the scan path registers 30 while sequentially shifting the test data pattern as described above, at time t _{3 in} FIG. 6, the selection signal S1 becomes "0". And the selection signal S
2 becomes "1". This forms a test path.

FIG. 7 is a time chart showing the operation during the test in this embodiment.

In FIG. 7, at time t ₀ , the selection signal S1 becomes "0" and the selection signal S2 becomes "1" as described above, so that the maximum operating frequency (delay time) and the maximum delay are obtained. A test path for determining the route is formed. When the test path is formed in this way, in FIG. 3, the multiplexer 38 outputs the output Q2 of the exclusive NOR 36 as the output Q3. Since the clock signal CLK at the input of the exclusive NOR 36 is "1", the same logic state as the output Q1 of the flip-flop 34 is output as the output Q2. It is also output as output Q3.

[0056] After the test path thus formed, at time t ₁ in FIG. 7, when the clock signal CLK is "0", the exclusive NOR36 is
The output Q2 is output by inverting the logic state of the output Q1. Therefore, the output Q3 is inverted at the falling edge of the clock signal CLK at this time to a logic state opposite to its previous logic state at this time.

As described above, the fall of the clock signal CLK corresponds to the input of the start clock signal CKS of the present invention. That is, in the present embodiment, the flip-flop 3 is triggered by the fall of the clock signal CLK.
The logic state opposite to that stored and held at 4 is input to the circuit under test (combination circuit) 20. Therefore, at the start of such a test, the flip-flop 34 performs an operation corresponding to the input-side flip-flop of the present invention. The flip-flop 34 stores a logic state opposite to the signal input to the circuit under test at the time of test start.

At the time t ₁ , the clock signal C is output from all the three scan path registers 30 in total.
When a desired logic state is input to the circuit under test 20 in synchronization with the fall of LK, the circuit under test 20 operates according to these inputs, and the result is the output signals W1 to W1.
It is output as W3.

The period of time after the falling of the clock signal CLK until the logic states of the output signals W1 to W3 of the circuit under test 20 stabilize is the delay time of the circuit under test. Further, the one whose logical state is stable at the end becomes the maximum delay path. For example, at time t ₂ of FIG. 7, the logic state of the output signal W1~W3 is stabilized, the logic state of a total of three of the scan path registers 30 each input D1 is stable. That is, in the time chart of FIG. 7, the period from the time t ₁ to the time t ₂ is the delay time of the circuit under test 20 of FIG.

As shown in FIG. 7, after the time t ₂ when the logic states of the output signals W1 to W3 are stable,
At time t _3, when the clock signal CLK rises, the output signal thus has the logic state stable W1~W3
Are taken into the respective flip-flops 34 of the scan path register 30. Since the logic states of the scan path registers 30 thus fetched are after the logic states of the output signals W1 to W3 have been stabilized, as described above, the logic states expected after the normal operation. Is the same as

On the other hand, when the clock signal CLK rises before the time t _{2 at} which the respective logical states of the output signals W1 to W3 are stable, the respective output signals W1 to W3 whose logical states are not stable are generated. Will be taken into the flip-flop 34 of the corresponding scan path register 30. In this case, each of the flip-flops 34 of the scan path register 30 generally has a different logic state from what is expected as a logic state when the circuit under test 20 normally completes operation. It has been taken in as the output signals W1 to W3.

As described above, after the clock signal CLK rises, the selection signal S1 is set to "1", and
The selection signal S2 is set to "0", and
As described above, the three scan path registers 30 in total are operated as shift registers, and the logical states fetched by the flip-flops 34 of the scan path registers 30 are sequentially read in a serial format. By comparing the logical state of the flip-flop 34 thus read in serial form with that expected when the circuit under test 20 completes a normal operation, the output signal W1 of the combinational circuit 20 is compared. ~ W
It is possible to determine whether or not the clock signal CLK has risen after the respective logic states of 3 have been stabilized.

For example, in the first test, when it is determined that the clock signal CLK has risen after the logical states of the output signals W1 to W3 have stabilized, the time t of FIG. Repeat the test while shortening the time from ₁ to time t ₃ in sequence. This is repeated until it is determined that the clock signal CLK has risen before the output signals W1 to W3 stabilize. As a result, the maximum operating frequency (delay time) of the circuit under test 20 and the maximum delay path can be specified. On the other hand, in the first test, when it is determined that the clock signal CLK has risen before the logical states of the output signals W1 to W3 are stabilized, the time t _{1 of} FIG. Repeat the retest while gradually extending the time from to the time t ₃ . This is repeated until it is determined that the clock signal CLK has risen after the respective logic states of the output signals W1 to W3 have stabilized. Thereby, the maximum operating frequency (delay time) and the maximum delay path of the circuit under test 20 can be specified.

When the time from the time t ₁ to the time t _{3 in} the time chart of FIG. 7, that is, the time during which the clock signal CLK is “0” is τ, the time τ is , Which corresponds to the predetermined test set time of the present invention. Further, the maximum operating frequency f can be expressed by the following equation by the time τ.

F = 1 / (2τ) (Hz) (1)

As described above, according to this embodiment, the logic state opposite to that stored and held in each of the flip-flops 34 in the plurality of scan path registers 30 is set to the clock signal CLK. It is possible to input data to the circuit under test 20 all at once in synchronization with the falling edge of. The plurality of flip-flops 34
In addition, a desired test data pattern can be input from the shift data input SDI from outside the integrated circuit while operating the plurality of scan path registers 30 as shift registers.

In addition, after being input to the circuit under test 20 in synchronism with the falling edge of the clock signal CLK, the flip-flops 34 in the plurality of scan path registers 30 are respectively supplied. It is possible to capture the output signals W1 to W3 from the circuit under test 20 in synchronization with the rising of the clock signal CLK. In this way, the data fetched in each of the flip-flops 34 can be sequentially read in serial form from the shift data output SDO by operating the plurality of scan path registers 30 again as shift registers.

The delay time of the circuit under test 20 is calculated by comparing the circuit read out after the test in this way with the circuit expected under the normal operation of the circuit under test 20. It is possible to determine the relationship with the time from the falling edge to the rising edge of the clock signal CLK.
Therefore, according to this embodiment, the maximum operating frequency (delay time) and the maximum delay path of the circuit under test 20 can be specified.

In this embodiment, the input side flip-flop of the present invention and the output side flip-flop of the present invention are the single flip-flop 34. Therefore, in this embodiment, the number of elements can be reduced and the degree of integration can be improved. Further, in this embodiment, the single flip-flop 34 is in the scan path register 30 as described above. Therefore, even in the conventional logic circuit as described above with reference to FIG. 7 and FIG.
Each of F3 to F3 can be easily replaced with the scan path register 30 of the present embodiment, and the present invention can be applied more easily.

[0070]

As described above, according to the present invention, the maximum operating frequency (delay time) and the maximum delay path of the logic circuit of the circuit under test can be more easily specified without using a special test device or the like. be able to. By incorporating the logic circuit test circuit of the present invention, the maximum operating frequency (delay time) and the maximum delay path can be specified as described above by, for example, a simulation or an actual circuit test. When performing such simulations and actual circuit tests, the functions of conventional simulation equipment and conventional test equipment used for actual circuit testing can be used, and special test equipment is not required. It is possible to perform the test more easily.

[Brief description of drawings]

FIG. 1 is a block diagram showing the gist of the present invention.

FIG. 2 is a circuit diagram of an integrated circuit of an embodiment to which the present invention is applied.

FIG. 3 is a circuit diagram of a scan path register used in the above embodiment.

FIG. 4 is a time chart showing an operation at the time of normal operation of the embodiment.

FIG. 5 is a time chart showing the operation at the time of inputting or outputting the test data of the above-mentioned embodiment.

FIG. 6 is a time chart showing the operation at the start of test path formation in the above embodiment.

FIG. 7 is a time chart showing the operation during the delay time test of the embodiment.

FIG. 8 is a circuit diagram of a logic circuit of an integrated circuit using a conventional scan path register.

FIG. 9 is a circuit diagram of the conventional scan path register.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 11 ... Input side flip-flop 12 ... Output side flip-flop 13 ... Start gate circuit 15 ... Clock control circuit 20 ... Circuit under test (combination circuit etc.) 30, F1-F3 ... Scan path register 32, 38 ... Multiplexer 34 ... Flip-flop 36 ... Exclusive NOR CKS ... Start clock signal CKE ... End clock signal CLK ... Clock signal SDI ... Shift data input SDO ... Shift data output W1-W3-Wj ... Output of circuit under test or combination circuit Y1-Y3-Yi ... Test Input of circuit or combinational circuit

Claims (3)

[Claims] 1. An input side flip-flop that stores and holds a test input signal TI, and an input side flip-flop that is stored and held by the input side flip-flop are input to a circuit under test in synchronization with a start clock signal CKS. A start gate circuit, an output side flip-flop for storing and holding a test output signal TO from the circuit under test in synchronization with an end clock signal CKE after inputting in synchronization with the start clock signal CKS, and the start clock signal CKS And a clock control circuit which outputs the end clock signal CKE after a predetermined test setting time from the output of the logic circuit test circuit. 2. The logic circuit test according to claim 1, wherein the input side flip-flop and the output side flip-flop are a single flip-flop having a multiplexer connected to its input. circuit. 3. The logic circuit test circuit according to claim 2, wherein the single flip-flop uses a scan path register.