JPH06213972A - Boundary scan cell circuit, boundary scan test circuit and their using method - Google Patents

Abstract

PURPOSE:To shorten test time in a 0/1 stack-at fault using a boundary scan test circuit. CONSTITUTION:In a boundary scan cell circuit 100a for input, one of a signal from a logical input terminal 101 and an exclusive logical sum produced in an arithmometer 112 is selected and output with a third selector 111 according to a control signal Scb, and this output is latched with a first flip flop 104. With the arithmometer 112, the exclusive OR of the output from the first flip flop 104 and the signal from the logical input terminal 101 is calculated. The exclusive OR signal is scanned out of a scan output terminal 108. Shift operation number in scanning out the test results is reduced and the test time is shortened. Also in a circuit for output, the scan-in of a reversal logic is omitted and the test time is shortened by automatically producing a reversal logic of the test data.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary lease cancel circuit provided corresponding to input / output pins of an integrated circuit,
The present invention relates to a boundary scan test circuit and a boundary scan test method for testing a connection state of a wiring under test connected between input / output pins of a plurality of integrated circuits.

[0002]

2. Description of the Related Art In recent years, a boundary scan test has been developed as an important method as a method for designing a test on a board (printed circuit board, etc.).
49.1 standardizes the access method. The structure of the boundary lease cancel circuit conforming to IEEE1149.1 and the structure of the boundary scan test circuit for performing the wiring test between the parts on the board using this boundary lease cancel circuit will be described below with reference to FIGS. It will be described based on 16.

FIG. 13 shows a structure of a boundary scan test circuit 200 using a boundary lease cancel circuit. A plurality of integrated circuits 210 on the printed circuit board,
220, 230, ... Are arranged, and each integrated circuit 21
0, 220, 230 have internal logics 212, 222,
, TAP controller (not shown) for controlling the operation of the devices in the integrated circuit, and each integrated circuit 21.
A large number of connection terminals 215, 225, 235 for exchanging signals between 0, 220 and 230, and this connection terminal 215.
(225, 235) and internal logic 212 (222, 23)
The same number of boundary lease cancel circuits 100, ... As the number of connection terminals provided between the main unit and the second unit are arranged as main devices. In the boundary scan test circuit 200, the tested wiring Wts, which is a signal line, is attached between the connection terminals 215, 225, 235 of the integrated circuits 210, 220, 230, respectively, and the boundary lease cancellation is performed. Depending on the signal state of the circuit 100, the disconnection of the wiring under test Wts connected to the connection terminal is tested. Further, the boundary lease cancel circuits 100 in the same integrated circuit and in each integrated circuit are connected in series, and the scan path 150 in which the scan signal Sscan flows is formed across all the integrated circuits. That is, at the time of the stuck-at fault test of the wiring under test Wts, a test logic signal (test data) is input to each boundary cancel circuit via the scan path 150 (hereinafter, referred to as scan-in), or The logic signal (test result) input to the boundary cancel circuit via the test wiring is output via the scan path (hereinafter referred to as scan out). In the figure, TDO is a scan output terminal for outputting the scan signal Sscan output from the integrated circuits 210 and 220, TDI is a scan input terminal for inputting the scan signal Scan, TCK is a clock signal input terminal, TMS is an input terminal for a test mode selection signal, and TRST is an input terminal for a reset signal.

Next, FIG. 14 shows a structure of a conventional boundary lease cancel circuit 100 conforming to IEEE1149.1. As shown in the figure, the boundary lease cancel circuit 100 includes first and second selectors 102 and 103 for selecting and outputting one of two inputs by control signals Sca and Scc, respectively, and a clock signal. S
Two first and second flip-flops 104 and 105 that operate in synchronization with cd and Sce, and a logical value 1 with the same driving capability
A buffer 107 that outputs / 0 is provided. Further, a logic output terminal 101 that receives a logic signal from the outside of the boundary lease cancel circuit 100, a scan input terminal 106 that receives a scan signal Sscan from the scan path 150, and signals Sca, Scc, Scd, and Sce are input, respectively. Control terminals 110a, 110c, 110d, 1
10 e, a scan output terminal 108 for outputting the scan signal Sscan to the scan path 150, and a logic output terminal 109 for outputting a logic signal to the outside of the boundary lease cancel circuit 100.

One input of the first selector 102 is the logic signal Slg from the logic input terminal 101, and the other input is the scan signal Sscan from the scan input terminal 106.
Is. The output of the first selector 102 is input to the first flip-flop 104, and the first flip-flop 1
The output of 04 is input to the second flip-flop 105. On the other hand, one input of the second selector 103 is the logic signal Slg from the logic input terminal 101, and the other input is the output of the second flip-flop 105. further,
The output of the second selector 103 is input to the buffer 107, and the output of the buffer 107 is output to the outside of the boundary lease cancel circuit 100 via the logic output terminal 109. The boundary cancellation circuit 100 may be arranged on the input side or the output side, but basically both have the same configuration.

Next, FIG. 15 shows a connection state when the boundary lease cancel circuit 100 of the integrated circuit 210 is used for output and the boundary lease cancel circuit 100 of the integrated circuit 220 is used for input. As shown in the figure,
In the integrated circuit 210, the logic input terminal 101 of the boundary cancel circuit 100 is connected to the internal logic 212, and the logic output terminal 109 is connected to the connection terminal 215 (output pin) of the integrated circuit 210. In the integrated circuit 220, the boundary lease cancel circuit 10
The logic input terminal 101 of 0 is the connection terminal 2 of the integrated circuit 220.
25 (input pin), and the logic output terminal 109 is connected to the internal logic 222.

In the boundary lease cancel circuit 100 of the integrated circuit 210, when the first selector 102 selects the scan signal Sscan according to the control signal Sca, each boundary cancel circuit in the first integrated circuit 210. All the first flip-flops 104 of 100 are in a serially connected state, the scan signal Sscan is output from the scan output terminal TDO shown in FIG.
6 and is output via the scan output terminal 108.

The operation when the 0 stuck-at fault test of the wiring Wts is performed by using the boundary scan test circuit 200 configured as described above will be described.

In advance, a logical value "1" is input to the second flip-flop 105 of the boundary lease cancel circuit 100 of the integrated circuit 210 by the SAMPLE / PRELOAD command.
Remember. Next, by executing the EXTEST instruction, the control signal Scc becomes "1", and the logical value "1" is output from the connection terminal 215 which is an output pin. FIG.
[Fig. 6] is a state transition diagram of a TAP controller defined by IEEE1149.1. In the figure, when the TAP controller is in the Capture-DR state, the control signal Sca becomes “0”, and the test result passing through the wiring Wts to the first flip-flop 104 of the input boundary lease cancel circuit 100 of the integrated circuit 220 is shown. The logical value is latched. Next, when the TAP controller is in the Shift-DR state, the control signal Sca becomes "1" and the scan path 150 is in the communication state, and at the same time, the logical value latched in the first flip-flop 104 is scanned out. The 0 stuck-at fault of the wiring Wts can be detected by comparing the logical value string of the test result with the input test data (logical value “1”) of all the scanned out serial data. Similarly, in order to test the stuck-at "1" fault, a logical value "0" is output from the output boundary lease cancel circuit 100, and the test result input to the input boundary lease cancel circuit 100 is sent to the scan path 150. Scan out.

That is, if the logical value input to the input boundary lease cancel circuit 100 through the tested wiring Wts is the logical value output from the output boundary lease cancel circuit 100 itself, the tested wiring Wts The connection is good. On the other hand, when the logical value "0" is input even though the logical value "1" is output, a 0 stuck-at fault occurs, and when the logical value "1" is input even when the logical value "0" is output. Is a stuck-at-1 fault.

[0011]

By the way, generally, in order to test the 0/1 stuck-at fault of the wiring, the test data consisting of a certain logical value sequence and the test data consisting of its inverted logical value are required. is there. That is, first "0",
When inputting test data “0”, “0”, “1”, ... To the wiring under test from the output boundary lease cancel circuit, next, “1”, “1”, “1”,
It is necessary to input test data "0", ... To the output boundary lease cancel circuit. Further, in the input boundary scan cancel circuit, it is necessary to receive the logic signal passed through each wiring under test and output the test result for the test data and the test result for the inverted logic to the scan path. Therefore, when the total number of wirings under test between integrated circuits is N, a shift operation of 4N cycles in total is required to test the 0/1 stuck-at fault, and the number of input / output pins, that is, the number of wirings under test increases. Therefore, there was a problem that the test time increased dramatically.

On the other hand, for example, US Patent Publication USP5084874
As disclosed in Japanese Patent Publication No. 2003-242242, the structure of the boundary cancel circuit is a multiplexer that selects any one of the input logic and the input scan signal, and the signal that is input from this multiplexer is held for a certain period of time.
There is one in which two flip-flops are connected in series and the inverted output of the rear flip-flop is fed back to the multiplexer. However, in the one disclosed in the publication, the signal to the logic output terminal is always output through the multiplexer and the two flip-flops, so that when the inverted logic is output to the logic output terminal. A capture cycle is needed. Therefore, the control of the multiplexer is different for the boundary cancellation for the input and the output, which makes the test circuit complicated and
Moreover, such a configuration has a problem that it is difficult to reduce the test time.

The present invention has been made in view of the above problems, and the output boundary lease cancel circuit scans the initial test data inversion logic by providing a means for internally generating the test data inversion logic. By omitting the cycle to be in, in the input boundary scan cancel circuit, by providing means for generating an exclusive OR of the logical output which is the test result and the previous logical output,
The purpose is to reduce the number of cycles for scanning out the test result for the test data, thereby shortening the test time.

[0014]

In order to achieve the above object, the means taken by the invention of claim 1 is, as shown in FIG. 11, as a boundary lease cancel circuit, a logic signal input from the outside is used. A logic input terminal for receiving, a scan input terminal for receiving a scan signal input from the outside, a scan output terminal for outputting a scan signal to the outside, and a logic signal input via the logic input terminal as an input, An input logic storage means for storing and outputting a logic signal for a fixed time, a logic signal output from the input logic storage means for a predetermined time and a current logic signal input via the logic input terminal As an input, an exclusive OR generating means for generating an exclusive OR of the previous logical signal and the current logical signal, a scan signal input through the scan input terminal, and A scan which receives an exclusive OR signal generated by the other logical OR generating means, selects an input scan signal and an exclusive OR according to a control signal, and outputs it to the outside through the scan output terminal. The selection means is provided.

According to a second aspect of the present invention, in the invention of the first aspect, the logic signal from the logic input terminal and the scan signal from the scan input terminal are input.
An input selection means is provided for selecting either the logic signal or the scan signal according to the control signal and outputting the selected logic signal to the exclusive OR generation means. Then, the scan selection means,
The input side is connected to the output side of the input selection means and the output side of the exclusive OR generating means, the input logic storage means is connected to the output side of the scan selection means, and the output side is connected to the scan output terminal. According to the clock signal
It is composed of an input logic holding flip-flop that outputs an input logic signal or an exclusive OR signal. Further, the scan output terminal is connected to the non-inverting output terminal of the input holding flip-flop.

According to a third aspect of the present invention, as shown in FIG. 12, the boundary cancel circuit includes a logic output terminal for outputting a logic signal and a scan input terminal for receiving a scan signal input from the outside. A scan output terminal for outputting a scan signal to the outside, and an input scan storage means for storing the scan signal input through the scan input terminal for a certain period of time and then outputting the scan signal.
An output of the input scan storage means is input, an inverted signal generation means for generating an inverted signal of the input scan signal, an input side is connected to the scan input terminal and the inverted signal generation means, and an output side is connected to the input scan storage means. hand,
Input selection means for alternately selecting and outputting an input scan signal and its inverted signal in accordance with a control signal, and an alternating signal of the input scan signal selected by the input selection means and its inverted signal is held for a certain period of time. And an alternate signal output means for outputting to the outside through the logic output terminal. And
The scan output terminal is connected to a signal line between the scan input terminal and the input selection means.

According to a fourth aspect of the invention, in the invention of the third aspect, the input scan storage means, the inversion signal generation means and the alternate signal output means are non-inversion of the input signal according to the clock signal. It is composed of an input scan holding flip-flop that outputs a signal and an inverted signal from each of two output terminals. Then, the logic output terminal
The input scan holding flip-flop is connected to the output terminal of the non-inverted signal, and the input side is connected to the scan input terminal and the input scan holding flip-flop output terminal of the inversion signal, and the output side is connected to the input side. The configuration is such that it is connected to the input terminal of the scan holding flip-flop.

According to a fifth aspect of the present invention, the boundary lease cancel circuit according to the first or second aspect of the present invention has the same logic output terminal as that of the third aspect of the present invention, and input scan storage means. The inverted signal generating means and the output logic selecting means are provided.

According to a sixth aspect of the present invention, there is provided a plurality of means having an internal logic, an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside. Of the integrated circuit, and a wiring attachment portion provided between the input pin of any one of the plurality of integrated circuits and the output pin of the other integrated circuit to which a wiring to be tested for testing the connection / disconnection state is attached, An input boundary lease cancel circuit provided between the input pin of the integrated circuit and the internal logic; an output boundary lease cancel circuit provided between the output pin of each integrated circuit and the internal logic; A boundary scan test circuit provided with a scan path in which each boundary cancel circuit is connected in series is assumed. Further, the input boundary lease cancel circuit is configured in the same manner as the boundary lease cancel circuit of the invention of claim 1.

According to a seventh aspect of the present invention, the input boundary lease cancel circuit in the sixth aspect of the invention is configured in the same manner as the boundary lease cancel circuit of the second aspect.

The means of implementing the invention of claim 8 has a plurality of means having an internal logic and an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside. An integrated circuit, and a wiring mounting portion provided between an input pin of any one of the plurality of integrated circuits and an output pin of another integrated circuit to which a wiring to be tested for testing the connection / disconnection state is mounted, An input boundary lease cancel circuit provided between the input pin of the integrated circuit and the internal logic; an output boundary lease cancel circuit provided between the output pin of each integrated circuit and the internal logic; A boundary scan test circuit provided with a scan path in which each boundary cancel circuit is connected in series is assumed. The output boundary lease cancel circuit is configured in the same manner as the boundary lease cancel circuit according to the third aspect of the invention.

According to a ninth aspect of the present invention, the output boundary lease cancel circuit in the eighth aspect is configured in the same manner as the boundary lease cancel circuit in the fourth aspect.

According to a tenth aspect of the invention, in the invention of the sixth or seventh aspect, the output boundary cell circuit is arranged in the integrated circuit in which the input boundary cell circuit is arranged. The output boundary lease cancel circuit is configured in the same manner as the boundary lease cancel circuit according to the third aspect of the present invention.

According to the invention of claim 11, in the invention of claim 8 or 9, the input boundary cell circuit is arranged in the integrated circuit in which the output boundary cell circuit is arranged. The input boundary lease cancel circuit is configured in the same manner as the boundary lease cancel circuit according to the first aspect of the present invention.

According to a twelfth aspect of the present invention, means provided has a plurality of input pins for inputting a logic signal to the internal logic from the outside and an output pin for outputting a logic signal from the inside logic to the outside. Of the integrated circuit, and a wiring attachment portion provided between the input pin of any one of the plurality of integrated circuits and the output pin of the other integrated circuit to which a wiring to be tested for testing the connection / disconnection state is attached, An input boundary lease cancel circuit provided between the input pin of the integrated circuit and the internal logic; an output boundary lease cancel circuit provided between the output pin of each integrated circuit and the internal logic; A boundary scan test circuit provided with a scan path in which each boundary cancel circuit is connected in series is assumed. A logic input terminal configured to input a logic signal to the input boundary lease cancel circuit and the output boundary lease cancel circuit, a scan input terminal for receiving a scan signal from the scan path, and the scan A scan output terminal for outputting a scan signal to the campus, an input logic storage means for receiving a logic signal input through the logic input terminal as an input, and storing and outputting the logic signal for a predetermined time; An exclusive OR of the previous logic signal and the current logic signal is generated by inputting the logic signal output from the logic storage means before a certain time and the current logic signal input via the logic input terminal. Exclusive OR generating means, a scan signal input through the scan input terminal, and an exclusive theory generated by the exclusive OR generating means. A scan selection unit that receives a sum signal as an input, selects an input scan signal and an exclusive OR according to a control signal and outputs the selected scan signal to the scan output terminal, a logic output terminal that outputs a logic signal, and the scan input The scan signal input from the terminal to the boundary lease cancel circuit is input,
Input scan storage means for storing the input scan signal for a certain period of time and outputting the input scan signal; inversion signal generation means for receiving the output of the input scan storage means as an input and generating an inversion signal of the input scan signal; An input selection unit that is connected to a terminal and an inverted signal generation unit and has an output side connected to the input scan storage unit, and that alternately selects an input scan signal and its inverted signal according to a control signal; The configuration is such that an alternate signal output means that outputs an alternate signal of the selected input scan signal and its inverted signal after holding the alternate signal for a certain period of time is provided.

According to a thirteenth aspect of the present invention, there is provided a plurality of means having an internal logic, an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside. Integrated circuit, an input boundary provided between the input pin of each integrated circuit and the internal logic, and a lease cancel circuit, and an output boundary provided between the output pin of each integrated circuit and the internal logic. As a boundary scan test method using a boundary scan test circuit including a lease cancel circuit and a scan path in which each boundary cancel circuit is connected in series, at least one integrated circuit of the above plurality of integrated circuits is used. Connect the wiring under test between the output pin and the input pin of another integrated circuit, and apply the logic signal that is inverted alternately to the output pin side. The output boundary lease cancel circuit of the circuit sequentially outputs at a constant time interval, and after storing the logical signal input to the input boundary lease cancel circuit of the integrated circuit on the input pin side for a fixed time, The exclusive OR of the current logic signal and the previous logic signal input through the input pin is generated, and the input scan signal and the exclusive OR which are input to the boundary lease cancel circuit are selected and This is a method of scanning out to the campus.

According to a fourteenth aspect of the present invention, there is provided a plurality of means having an internal logic, an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside. Integrated circuit, an input boundary provided between the input pin of each integrated circuit and the internal logic, and a lease cancel circuit, and an output boundary provided between the output pin of each integrated circuit and the internal logic. As a boundary scan test method using a boundary scan test circuit including a lease cancel circuit and a scan path in which each boundary cancel circuit is connected in series, at least one integrated circuit of the above plurality of integrated circuits is used. Connect the wiring under test between the output pin and the input pin of another integrated circuit, and output boundary of the integrated circuit on the output pin side. The scan signal input from the scan path to the cancel circuit is scanned in and stored for a certain period of time, an inverted signal of the stored scan signal is generated, and the next input to the output boundary lease cancel circuit is input. In this method, the scan signal and the inverted previous scan signal are alternately selected and input to the wiring under test.

[0028]

With the above construction, according to the first aspect of the present invention, when the current logic signal value input through the logic input terminal is the same as the previously input logic signal value, the exclusive OR generating means is used. The generated exclusive OR is "0", and when the current logical signal value is different from the previous logical signal value, the exclusive OR is "1". Therefore, in the test of the 0/1 stuck-at fault of the wiring in which the logic signal which is alternately inverted when the wiring is normal is input to the logic input terminal through the wiring, the exclusive OR generation means generates the exclusive OR. If the logical OR is "1", it is possible to determine that the connection state of the wiring is good, and if the exclusive OR is "0", it is possible to determine that the connection state of the wiring is bad. Since this exclusive OR is scanned out to the scan path, both the test result for the initial test data and the test result for the inversion logic of the initial test data are scanned when testing the 0/1 stuck-at fault. It is not necessary to scan out, and it is sufficient to scan out only the exclusive OR of both test results. Therefore, the number of shift operations for scanning out the test result is reduced.

According to the second aspect of the present invention, when the input selection means selects the logic signal from the logic input terminal side, the flip-flop is latched for a certain time in accordance with the clock signal, and the exclusive logic is applied. It is input to the sum generation means. Then, the exclusive OR generating means compares the new logical signal with the new logical signal, and the same operation as in the first aspect of the invention produces an exclusive OR for identifying the stuck-at fault of the wiring. On the other hand, when the scan signal is selected by the input selection unit, the scan signal is output from the scan output terminal via the scan selection unit and the flip-flop. Therefore, the input of the scan signal to the boundary lease cancel circuit and the output of the scan signal from the boundary lease cancel circuit are performed in synchronization with the clock signal, and a smooth wiring 0/1 stuck-at fault test is performed. Can be used for.

In the third aspect of the invention, the input scan signal and its inverted signal are alternately selected by the input selection means. Then, the alternating signal output means alternately outputs the input scan signal and its inverted signal from the boundary cancel circuit. Therefore, if the boundary lease cancel circuit is placed on the output side of the test data and certain test data is given from the scan input pin to the boundary lease cancel circuit, its inversion logic is automatically generated inside the boundary lease cancel circuit. Then, the test data and the inverted logic are alternately output from the logic output terminal. Therefore, the shift operation required for scanning in the inverted logic of certain test data becomes unnecessary.

On the other hand, the output of the inversion signal generation means is fed back to the input selection means, but since the scan output terminal is connected to the signal line between the input selection means and the scan input terminal, the inversion signal is passed through the scan path. The output to the scan path does not interfere with the inverted signal. Therefore, since the test data once input to the scan path is saved, the test data can be reused and the shift operation required for scanning the test data can be reduced.

According to the invention of claim 4, in the invention of claim 3, the single input scan holding flip-flop functions as the input scan storage means, the inverted signal generation means and the alternate signal output means, which is simple. In the configuration, the inverted logic of the test data is generated and the test data and the alternate signal of the inverted logic are output.

According to the invention of claim 5, the function of generating an inverted signal of the test data and alternately outputting the test data and the inverted logic thereof in one boundary cancel circuit, and scanning out the test result. Since the function of reducing the number of cycles is provided, it is possible to switch the function according to the arrangement location while sharing the configuration of the boundary lease cancel circuit. That is,
The cost can be reduced by sharing the structure of the boundary lease cancel circuit.

According to the sixth aspect of the present invention, when the 0/1 stuck-at fault of the wiring under test attached to the wiring mounting portion is tested,
In the boundary lease cancel circuit connected to the input pin side of the integrated circuit of the boundary scan test circuit, the logic signal input from each boundary lease cancel circuit through the wiring under test and the previously input logical signal The exclusive OR is output to the scan path. Then, it is detected whether or not there is a failure in the wiring under test connected to the boundary lease cancel only by this exclusive OR. Therefore, if the number of wirings to be tested is N, the number of shift operations for scanning out the test result is N cycles, the number of shift operations for scanning out the test result is reduced, and the test time is reduced. It will be shortened.

According to the invention of claim 7, in addition to the operation of the invention of claim 6, in the input boundary lease cancel circuit, the storage of the logic signal inputted last time and the scan path of the exclusive OR are carried out by the flip-flop. Since a scan-out to and from is performed, a simple configuration will suffice.

According to the invention of claim 8, when the 0/1 stuck-at fault of the wiring to be tested attached to the wiring mounting portion is tested,
In the boundary lease cancel circuit connected to the output pin side of the integrated circuit of the boundary scan test circuit, when test data is input to each boundary lease cancel circuit from the scan path, it is inverted in each boundary lease cancel circuit. Logic is automatically generated, and the test data signal and its inverted logic signal are alternately output to the wiring under test. Therefore, when testing the 0/1 stuck-at fault, the shift operation for scanning in the inversion logic of the test data into each boundary cancel circuit is not necessary. That is, assuming that the number of wirings under test is N,
The number of shift operations required for scan-in of test data is N cycles, which shortens the test time.

According to a ninth aspect of the present invention, in the above-mentioned eighth aspect, in each boundary cancel circuit, a single input scan holding flip-flop has an input scan storage means, an inverted signal generation means, and an alternate signal output means. Therefore, the inverted logic of the test data is generated and the alternate signal of the test data and its inverted logic is output with a simple configuration.

According to the tenth or eleventh aspect of the invention, in the input boundary lease cancel circuit, the above-mentioned sixth aspect is adopted.
Alternatively, the operation of the invention of claim 7 is obtained, and the operation of the invention of claim 8 or 9 is obtained in the output boundary lease cancel circuit. Therefore, it is possible to reduce the number of shift operations for scan-in of test data and scan-out of test results. That is, when the number of wirings to be tested is N, the test data is scanned in and the test result is scanned out in a total of 2N cycles of the shift operation, and the test time is significantly shortened.

According to the twelfth aspect of the present invention, while the structure of the boundary lease cancel circuit in the integrated circuit is made common, the function is switched and used as the input or output boundary lease cancel circuit according to the arrangement location. Thus, it is possible to reduce the number of shift operations for scan-in of test data and scan-out of test results. Therefore, the cost can be reduced by sharing the configuration of all the boundary lease cancel circuits.

According to the thirteenth aspect of the present invention, 0 of the wiring under test is
When testing a / 1 stuck-at fault, each of the input boundary-cancelling circuits inputs a logic signal that is alternately inverted to the wiring under test, and scans two logic outputs obtained for each logic signal. Failure is detected by scanning out only one test result without scanning out to the campus. Therefore, the test time is shortened.

According to the fourteenth aspect of the present invention, 0 of the wiring under test is
When testing a stuck-at-1 fault, each output boundary lease cancel circuit outputs the logic signal of the test data and its inverted logic signal to the wiring under test simply by scanning the test data from the scan path. It
Therefore, the test time is shortened because the shift operation for scanning in the inversion logic of the test data is unnecessary.

[0042]

Embodiments of the present invention will be described below with reference to the drawings.

(First Embodiment) The boundary lease cancel circuit of the first embodiment will be described below with reference to FIGS. In each of the following embodiments, the overall device layout of the boundary scan test circuit is as shown in FIG.
The structure of the boundary scan test circuit 200 is basically the same as that of the conventional boundary scan test circuit 200 shown in FIG.

FIG. 1 shows the structure of the boundary lease cancel circuit 100a of the boundary lease cancel circuit 100 according to the first embodiment. In the boundary lease cancel circuit 100a, the first selector 102, the second selector 103, the first flip-flop 104, the second selector
Configurations of main devices such as the flip-flop 105 and the buffer 107, a logic input terminal 101, and a scan input terminal 10
6, the scan output terminal 108, the logic output terminal 109, and the control terminals 110a, 110c, 110d, and 110e are the same as those of the conventional boundary lease cancel circuit 100 (see FIG. 14) described above.

Here, as a feature of the present invention, between the first selector 102 and the first flip-flop 104,
A third selector 111 as a scan selecting means and an arithmetic unit 112 as an exclusive OR generating means are interposed. Then, the arithmetic unit 112 has a non-inverted output of the first flip-flop 104 as an input logic storage means,
The output of the first selector 102 is input. The third selector 111 has the output of the first selector 102 and the arithmetic unit 1
The output of 12 is input, and either of the two inputs is selected and output according to the control signal Scb input from the terminal 110b. Further, the first flip-flop 104 uses the output of the third selector 111 as an input to the terminal D,
The input is held according to the clock signal Scd to the terminal CK, and then output from the terminal Q. The arithmetic unit 112 receives the output of the first selector 102 and the non-inverted output of the first flip-flop 104, and calculates and outputs the exclusive OR of the two. The second flip-flop 105 has a first flip-flop.
The non-inverted output of the flip-flop 104 is input to the terminal D, and the input is held and then output from the terminal Q according to the clock signal Sce to the terminal CK. The second selector 103 receives the non-inverted output of the second flip-flop 105 and the logic signal Slg from the logic input terminal 101,
One of the inputs is selected and output according to the control signal Scc. The output of the second selector 103 is the buffer 10
7 and is output to the outside (for example, the internal logic 212 in FIG. 13) via the logic output terminal 109. Further, the scan output terminal 108 is connected to the non-inverted output side of the first flip-flop 104, and the exclusive OR signal or the like output from the arithmetic unit 112 is supplied to the scan path via the scan output terminal 108. Scanned out to 150. In the figure, the numbers "0" and "1" attached to the inputs of the respective selectors 102, 103 and 111 indicate the values of the control signals for selecting the inputs.

Next, the operation of the boundary lease cancel circuit 100a configured as described above will be described with reference to FIGS. FIG. 2 is a state transition diagram of the TAP controller. 3A to 3C are diagrams for explaining the operation when the three boundary lease cancel circuits 100a are arranged on the output pin side of the integrated circuit.

First, the first Capture-DR shown in FIG.
In the state, since the control signals Sca and Scb are both “0”, as shown in FIG.
The logical signal Slg from the above is latched in the first flip-flop 104 at the rising edge of the clock signal Scd. At this time, the control signal Scc is "1" and the clock signal Sce is "0".

Next, in the second Capture-DR state, when the control signal Scb is set to "1" and then the clock signal Scd is applied, as shown in FIG. 3B, the first flip-flop 104 is latched in advance. The exclusive OR of the logical value that has been set and the value of the logical signal Slg input from the logical input terminal 101 is latched again in the first flip-flop 104. As a result, the first and second Capture-D
If the values of the logical signal Slg to be latched in the R state are logical inversions of each other, the logical value "1" is always latched by the first flip-flop 104. That is, the logic signal Slg input to each boundary cancel circuit 100a.
However, in the first Capture-DR state shown in FIG. 3A, they are “0”, “0”, and “1” in order from the top, and FIG.
In the second Capture-DR state shown in FIG. 3, assuming that the states are “1”, “1”, and “0” in order from the top, the first flip-flop 1 of each boundary cancel circuit 100a.
In 04, an exclusive OR “1” of two logical values,
"1" and "1" are latched.

Next, in the Shift-DR state, the control signal Sca
Becomes “1” and the scan signal Sscan is input to the first flip-flop 104, the first flip-flop 1
04 functions as a shift register. In this state, as shown in FIG. 3C, the logical value finally latched by the first flip-flop 104 is output as the scan signal Sscan.

Further, in the Update-DR state shown in FIG.
When the clock signal Sce is given, the output of the first flip-flop 104 is latched by the second flip-flop 105. Furthermore, by setting the control signal Scc to "1", the non-inverted output of the second flip-flop 105 can be output from the buffer 107 regardless of the value of the logical signal Slg from the logical input terminal 101. .

As described above, according to the boundary lease cancel circuit 100a according to the above embodiment, the Capture-DR
If the logical value latched in the state is the same as the logical value that was latched immediately before, the logical value "0" is latched in the flip-flop 104 as a result, and the logical value "1" is latched in the inverted logic. This means that the number of shift operations for scan-out can be reduced in the boundary cancel circuit, in which a signal that is logically inverted in nature should be latched in some kind of test. That is, for example, in the 0/1 stuck-at fault test of the wiring between the integrated circuits, the boundary data cancel circuit arranged on the input pin side of the integrated circuit inputs the test data and its inverted logic signal to the wiring. Then, 2 from the wiring for these two types of inputs
It is not necessary to scan out each type of output, and if only the exclusive OR signal is scanned out, the presence or absence of a 0/1 stuck-at fault in the wiring can be detected. Therefore, the test time can be significantly shortened by reducing the number of shift operations required for scan out. That is, if the number of wirings to be tested is N, the scan-out of the test result can be completed by the shift operation of N cycles. Therefore, as the integration degree of the integrated circuit increases, the scan-in of the boundary-cancellation circuit becomes more difficult. It is possible to significantly reduce the number of shift operations required for.

Further, with this configuration, an arbitrary logical value can be output from the buffer 107, and a 1-bit exclusive OR of the logical value latched the first time and the logical value latched the second time is output. Is possible.

The present invention is not necessarily limited to the structure of the boundary lease cancel circuit 100a shown in FIG. For example, the second flip-flop 105 does not necessarily have to be arranged. Also, the first selector 1
It is not necessary to select the scan input and the logic input from the logic terminal in 02 and input them to the arithmetic unit 112.
Only lg needs to be input to the first flip-flop. In that case, the scan signal Sscan can be output from the scan output terminal 108 via another path. Further, although the first flip-flop 104 is arranged as the scan input storage means, another member having a temporary storage function may be arranged. However, by adopting the circuit configuration as shown in FIG. 1, the logic signal Slg is input, the exclusive OR signal is scanned out, and the other boundary cancellation of the input scan signal Sscan is performed with a simple configuration. The output to the circuit can be synchronized.

(Second Embodiment) Next, a boundary lease cancel circuit 100b according to a second embodiment will be described with reference to FIGS.

FIG. 4 shows the structure of the boundary lease cancel circuit 100b according to the second embodiment. As shown in the figure, the boundary lease cancel circuit 1 according to the second embodiment.
00b is similar to the first embodiment, the first, second and third selectors 102, 103 and 111, the first and second flip-flops 104 and 105, the buffer 107, and the terminals 101, 106 and 108. , 109, 110a to 110e
It has and. However, in the second embodiment, the third selector 111 is provided between the first flip-flop 104 and the second flip-flop 105, and the exclusive OR generating means is not provided.

That is, the first selector 102 outputs the logic signal Slg from the logic input terminal 101 and the scan signal Sscan.
Are used as inputs, and one of the inputs is selected and output according to the control signal Sca. The first flip-flop 104 is
The output of the first selector 102 is input to the terminal D, and this input is held and then output according to the clock signal Scd to the terminal CK. The third selector 111 receives the non-inverted output of the first flip-flop 104 and the inverted output Soi of the second flip-flop 105 as input, selects one of them according to the control signal Scb, and outputs it. The second flip-flop 105 uses the output of the third selector 111 as an input to the terminal D and holds this input. Second selector 103
Receives the non-inverted output Son of the second flip-flop 105 and the logic signal Slg from the logic input terminal 101, and selects and outputs one of the inputs according to the control signal Scc. The buffer 107 receives the output of the second selector 103 as an input, and outputs this input to the outside (to the tested wiring Wts in FIG. 13 in this embodiment) via the logic output terminal 109.

Hereinafter, the operation of the boundary lease cancel circuit 100b configured as described above will be described with reference to FIGS. FIG. 5 is a state transition diagram, and FIGS. 6A to 6C are diagrams for explaining the operation when the three boundary lease cancel circuits 100b are used for output.

First, in the Shift-DR state shown in FIG.
The control signal Sca becomes “1”, and the scan signal Sscan is sent to the first flip-flop 104 as shown in FIG.
Is input, and the first flip-flop 104 functions as a shift register. In this state, an arbitrary logical value is input to the first flip-flop 104 as the scan signal Sscan. For example, as shown in the figure, the first flip-flop 1 of each boundary cancel circuit 100b is
In 04, logical values “0”, “0”, “1” are arranged in order from the top.
Is latched.

Next, in the first Update-DR state, the control signal Scb becomes "0" and the clock signal Sce is given, and as shown in FIG. 6B, the logical value of the first flip-flop 104 becomes Since the control signal Scc is loaded into the second flip-flop 105 and becomes “1”, the scan signal Ssc becomes independent of the signal from the logic input terminal 101.
An arbitrary logical value input as an can be output from the buffer 107. For example, as shown in the figure,
The first flip-flop 104 and the second flip-flop 105 of each boundary cancel circuit 100b latch "0", "0", "1" in order from the top.

Next, in the second Update-DR state,
When the control signal Scb becomes “1” and the clock signal Sce is given, the inverted value of the logical value stored in the second flip-flop 105 until immediately before is newly loaded and the buffer 1
It is output from 07. For example, as shown in FIG. 6C, the first flip-flop 104 of each boundary cancellation circuit 100b has logical values "0", "0",
When “1” is latched, the second flip-flop 105 has its inverted logical value “1”,
"1" and "0" are latched.

In the boundary lease cancel circuit 100b according to the second embodiment, the inverted logical value of the logical value loaded in the first Update-DR state is immediately output to the buffer 10.
It is possible to output from 7. This means that in some tests, a signal that has been logically inverted twice in a row is
In the boundary lease cancel circuit output from 07, the scan-in shift operation can be shortened. That is, for example, in the 0/1 stuck-at fault test of the wiring between the integrated circuits, it is not necessary to scan in the inversion logic of the test data in the boundary lease cancel circuit arranged on the output pin side of the integrated circuit. The test time can be significantly reduced by the number of shift operations for this scan-in. That is, if the number of wirings to be tested is N, the scan-in of the test data can be completed by the shift operation of N cycles. It is possible to significantly reduce the number of shift operations required for.

(Third Embodiment) Next, a third embodiment of the boundary scan test circuit will be described with reference to FIGS. 7 and 8.

FIG. 7 is a scan test circuit in which the boundary lease cancel circuit 100a having the structure described in the first embodiment is arranged on the input side, and the boundary lease cancel circuit 100b described in the second embodiment is arranged on the output side. Two
00 configuration is shown. In the figure, in order to make the understanding particularly easy, two integrated circuits 210 and 220 and each integrated circuit 2 are shown.
10 to the integrated circuit 220 for outputting a signal to the connection terminal 215 of the easily connected portion and the wiring under test Wts between them.
And shows only.

In the figure, the boundary lease cancel circuit 100b having the structure described in the second embodiment is connected to the connection terminal 215 which is an output pin of the integrated circuit 210. That is, the boundary lease cancel circuit 100b includes the first and second selectors 102 and 103.
, The first and second flip-flops 104 and 105, and the non-inverted output of the first flip-flop 104 and the inverted output of the second flip-flop 104 as inputs, and either of the two inputs is selected according to the control signal. And a third selector 111 for outputting. On the other hand, the boundary lease cancel circuit 100a having the structure shown in the first embodiment is arranged at the connection terminal 215 which is an input pin of the integrated circuit 220. That is, the boundary lease cancel circuit 100a includes the first and second selectors 102 and 10
3, first and second flip-flops 104 and 105,
Output of first selector 102 and first flip-flop 1
04 is an input, and an arithmetic unit 112 that calculates and outputs an exclusive OR of the two inputs, and an output of the arithmetic unit 112 and an output of the first selector 102 are input, and two of them are output according to a control signal. The third which selects one of the inputs and outputs it
And a selector 111. Although not shown,
It goes without saying that the TAP controllers 213 and 223 and the boundary lease cancel circuits 100a and 100b are connected by signal lines.

Next, the operation of each of the boundary lease cancel circuits 100a and 100b will be described with reference to FIG. First, in the Shift-DR state shown in FIG. 8A, by using the scan path 150, test data such as “0”, “0”, “,” is input to the first flip-flop 104 of the output boundary lease cancel circuit 100b. 1 "is scanned in from the scan path.

Next, in the Update-DR state shown in FIG. 8B, after transferring the test data "0", "0", "1" from the first flip-flop 104 to the second flip-flop 105, Test data “0”, “0”, “1” is input to the wiring under test Wts.

Then, the Capture-DR shown in FIG.
In this state, the test data “0”, “0”, “1” input from the wiring under test Wts is latched in the first flip-flop 104 of the input boundary lease cancel circuit 100a.

Next, in the Update-DR state shown in FIG. 8D, the inverted output Soi is fed back without newly scanning the test data into the second flip-flop 105 of the output side scan cell 100b. , The inversion logic of the previous test data, that is, "1", "1", "0" is output to each tested wiring Wts.

Further, in the Capture-DR state shown in FIG. 8E, in the input-side boundary lease cancel circuit 100a, the test results "0", "0", "1" previously inputted from the wiring under test Wts are inputted. And the exclusive OR of the test results “1”, “1”, and “0” input this time is latched in the first flip-flop 104. Therefore, if there is no 0/1 stuck-at fault in the wiring under test Wts, the logical values "1", "1", "1" are latched in all the first flip-flops 104.

Further, in the Shift-DR state shown in FIG. 8 (f), the exclusive OR values "1", "1", "1" latched by the first flip-flop 104 of the input side scan cell circuit 100a. Is serially scanned out using the scan path 150. By comparing the scanned out exclusive OR values "1", "1", "1" with the expected values "1", "1", "1", the 0/1 degeneracy of the wiring under test Wt is reduced. The presence or absence of a failure can be determined.

In the third embodiment, the wiring under test Wts is 0.
When testing a / 1 stuck-at fault, the output boundary lease cancel circuit 100b does not require a shift operation for scanning in the inversion logic of the test data. In addition, the input boundary lease cancel circuit 100a does not need to scan out the two test results for the test data having the patterns inverted from each other, but only performs the shift operation to scan out the exclusive OR value of the two. This will significantly reduce the test time. That is, when the number of wirings to be tested is N, the shift operation required for scan-in of test data and scan-out of test results is completed in 2N cycles, which is significantly larger than the conventional 4N cycle. The number of shift operations is reduced. This means that the higher the degree of integration of the integrated circuit, the shorter the test time will be.

(Embodiment 4) Next, one integrated circuit 240
Two types of boundary lease cancel circuit 100
Example 4 which is an example in which a and 100b are provided will be described.

FIG. 9 shows the configuration of an integrated circuit 240 according to the fourth embodiment, and the internal logic 2 is provided inside the integrated circuit 240.
42 and a TAP controller 243 are provided, and the internal logic 242 and the connection terminal 2 serving as an input pin are provided.
The boundary lease cancel circuit 100a having the structure described in the first embodiment is provided between the internal logic 242 and the connection terminal 245, and the structure described in the second embodiment between the internal logic 242 and the connection terminal 245 serving as an output pin. The boundary lease cancel circuit 100b having the above is interposed.

That is, in the fourth embodiment, the above-mentioned third embodiment is used.
The same effect can be surely obtained in the same integrated circuit.

(Fifth Embodiment) Next, a fifth embodiment, which is an example in which the boundary lease cancel circuit has two functions, will be described with reference to FIG.

In the boundary lease cancel circuit 100c shown in FIG. 10, the terminals 101, 106, 108,
109, the first selector 102, and the first and second flip-flops 104 and 105 are arranged.
And the same as the second embodiment. Here, in the fifth embodiment, an arithmetic unit 112, which is an exclusive OR generating means having the same configuration as that of the first embodiment, is arranged, and a scan having the same function as the third selector 111 in the first embodiment. A selector 111a, which is a selection unit, is arranged and
First flip-flop 104 and second flip-flop 1
05 to the third selector 1 in the second embodiment.
11 (see FIG. 4) is provided with a selector 111b which is an input selecting means having the same function. The control terminals Sca, Scb1, Scb2, Scc,
Scd and Sce are provided. That is, when the boundary lease cancel circuit 100c is connected to the input pin of the integrated circuit, the control signal Scb2 is fixed to "0" so that the selector 111b passes only the output of the first flip-flop 104. To do. Then, the control signal Scb
The selector 111a is activated by switching 1 and the second
The signal to be stored in the flip-flop and the signal to be scanned out are selected. When the boundary lease cancel circuit 100c is connected to the output pin, the control signal Scb1 is fixed to "0" and the selector 11
1a functions to pass only the output of the first selector 102. The selector 111b is operated by switching the control signal Scb2 to alternately output the test data and its inverted logic.

Therefore, in the fifth embodiment, all the boundary lease cancel circuits 100c have a common structure, and the functions thereof are switched according to the place where they are arranged. It can always be demonstrated, and it can be expected to reduce costs by mass production.

[0078]

As described above, according to the invention of claim 1, as the structure of the boundary cancel circuit,
An input logic storage means for storing and outputting a logic signal from the logic input terminal for a fixed time, and an exclusive OR generating means for generating an exclusive OR of the logic signal before this fixed time and the current logic signal The scan selection means for selecting and outputting the input scan signal and the exclusive OR according to the control signal is provided. Therefore, when the 0/1 stuck-at fault is tested, the test result for the initial test data It is not necessary to scan out both the test result and the test result for the inversion logic of the initial test data, and it is sufficient to scan out only the exclusive OR of both test results. By reducing the number, the test time can be shortened.

According to the invention of claim 2, in the invention of claim 1, the input selection for selecting either the logic signal or the scan signal according to the control signal and outputting it to the exclusive OR generating means. Means is provided to connect the input side of the scan selection means to the output side of the input selection means and the output side of the exclusive OR generating means, while the input side of the input logic storage means is connected to the output side of the scan selection means Since the flip-flop is connected to the scan output terminal, the function of the flip-flop operated by the clock can be utilized to achieve the effect of the invention of claim 1 with a simple configuration.

According to the third aspect of the present invention, as the structure of the boundary lease cancel circuit, the input scan storage means for storing the input scan signal for a predetermined time and then outputting the input scan signal,
Inversion signal generation means for generating an inversion signal of the input scan signal, input selection means for alternately selecting the input scan signal and its inversion signal according to the control signal, and an alternating signal of the input scan signal and its inversion signal Is provided after being held for a certain period of time and output, and the scan output terminal is connected to the signal line between the scan input terminal and the input selecting means. The test data and the inversion logic are alternately output from the output terminal, and the shift operation for scanning in the inversion logic of the test data is not necessary, so that the test time can be shortened.

According to the invention of claim 4, in the invention of claim 3, the single flip-flop is made to function as the input scan storage means, the inverted signal generation means and the alternate signal output means, so that it is simple. Claim 3 in the configuration
The effect of can be exhibited.

According to the invention of claim 5, a function of outputting the test data and its inversion logic according to the configuration of the invention of claim 2 in one boundary cancel circuit.
Since the function of reducing the number of shift operations for scanning out the test data according to the configuration of the invention of claim 1 is provided,
While sharing the structure of the boundary lease cancel circuit, its function can be switched according to the location.
Therefore, it is possible to reduce the cost due to the mass production effect.

According to the invention of claim 6, the mounting portion of the wiring under test connected between the output pin and the input pin of each integrated circuit, and the input boundary lease cancel connected to the input pin of each integrated circuit. As a configuration of a boundary scan test circuit including a circuit, an output boundary lease cancel circuit connected to the output pin of each integrated circuit, and a scan path connecting each boundary lease cancel circuit in series Input logic storage means for storing and outputting a logic signal from the logic input terminal for a fixed time to the boundary cancellation circuit, and an exclusive OR of the logic signal before this fixed time and the current logic signal is generated. Since the exclusive OR generating means and the scan selecting means for selecting and outputting the input scan signal and the exclusive OR according to the control signal are provided, When testing a 0/1 stuck-at fault of the wiring under test attached to the wiring attachment part, the exclusive logic between the logic signal input through the wiring under test and the logic signal previously input from each boundary cancel circuit. It is only necessary to scan out the sum, so that the test time can be shortened by reducing the number of shift operations for scan-out of the test result.

According to the invention of claim 7, in the invention of claim 6, the input selection for selecting either the logic signal or the scan signal according to the control signal and outputting it to the exclusive OR generating means. Means is provided to connect the input side of the scan selection means to the output side of the input selection means and the output side of the exclusive OR generating means, while the input side of the input logic storage means is connected to the output side of the scan selection means Since the flip-flop is connected to the scan output terminal, the function of the flip-flop operated by the clock can be utilized to achieve the effect of the invention of claim 6 with a simple configuration.

According to the invention of claim 8, the mounting portion of the wiring under test connected between the output pin and the input pin of each integrated circuit and the input boundary lease cancel connected to the input pin of each integrated circuit. As a configuration of a boundary scan test circuit including a circuit, an output boundary lease cancel circuit connected to the output pin of each integrated circuit, and a scan path connecting each boundary lease cancel circuit in series, An input scan storage means for storing the input scan signal for a certain period of time and then outputting it to the boundary cancel circuit, an inverted signal generation means for generating an inverted signal of the input scan signal, and an input scan signal according to the control signal. Input selection means for alternately selecting and the inverted signal thereof, and after holding the alternating signal of the input scan signal and its inverted signal for a certain period of time Provided an alternating signal output means for force,
Since the scan output terminal is connected to the signal line between the scan input terminal and the input selection means, the number of shift operations for scanning in the test data at the time of the 0/1 stuck-at fault of the wiring under test is tested. The test time can be shortened due to the reduction.

According to a ninth aspect of the present invention, in the above eighth aspect, each boundary lease cancel circuit includes a single input scan holding flip-flop, an input scan storage means, an inversion signal generation means, and an alternate signal. Since it is made to function as the output means, the effect of the invention of claim 8 can be exhibited with a simple configuration.

According to the invention of claim 10, the above-mentioned claim 6
Alternatively, in the invention of claim 7, the output boundary cell circuit is arranged in an integrated circuit in which the input boundary cell circuit is arranged, and the input scan signal is supplied to the output boundary lease cancel circuit for a predetermined time. Input scan storage means for outputting after storing for a while, inverted signal generation means for generating an inverted signal of the input scan signal, and according to a control signal,
An input selection unit that alternately selects an input scan signal and its inverted signal and an alternate signal output unit that outputs the alternate signal of the input scan signal and its inverted signal after holding it for a certain period of time are provided, and scan output terminals are scanned. Since it is configured to be connected to the signal line between the input terminal and the input selection means, in addition to the effect of the invention of claim 6 or 7, the test data is added when the 0/1 stuck-at fault of the wiring under test is tested. The test time can be shortened by reducing the number of shift operations for scan-in.

According to the invention of claim 11, the above-mentioned claim 8
Alternatively, the input boundary cell circuit is provided in an integrated circuit in which the output boundary cell circuit is provided, and the input boundary boundary cancel circuit is provided with a logic signal from a logic input terminal for a predetermined time. Input logic storing means for storing and outputting during the period, exclusive OR generating means for generating exclusive OR of the logical signal before this fixed time and the current logical signal, and the input scan according to the control signal. Since the scan selection means for selecting and outputting the signal and the exclusive OR is provided, in addition to the effect of the invention of claim 8 or 9, the test wiring is tested for 0/1 stuck-at faults. The test time can be shortened by reducing the number of shift operations for scanning out the test result from the input boundary cancel circuit to the scan path.

According to the twelfth aspect of the invention, the mounting portion of the wiring under test connected between the output pin and the input pin of each integrated circuit and the input boundary lease cancel connected to the input pin of each integrated circuit. As a configuration of a boundary scan test circuit including a circuit, an output boundary lease cancel circuit connected to the output pin of each integrated circuit, and a scan path connecting each boundary lease cancel circuit in series, In the boundary lease cancellation circuit,
Since the function of outputting the test data and the inverted logic thereof according to the configuration of the invention of claim 2 and the function of omitting the shift operation for scanning out the test data according to the configuration of the invention of claim 1 are provided, the integrated circuit is provided. Scan-in of test data and scan of test result by switching the function as a boundary lease cancel circuit for input or output according to the location while making the structure of the boundary lease cancel circuit inside For out, the test time can be shortened by reducing the number of shift operations.

According to the thirteenth aspect of the present invention, a boundary scan cancel circuit is connected to the input / output pins of a plurality of integrated circuits, and a scan path is formed which connects the boundary lease cancel circuits in series. As a boundary scan test method using a darry scan test circuit, connect the wiring under test between the output pin of one integrated circuit and the input pin of the other integrated circuit, and invert the logic signal that is alternately inverted on the output pin side. After sequentially outputting from the output boundary lease cancel circuit at fixed time intervals and storing the logical signal input to the input boundary lease cancel circuit on the input pin side for a fixed time, this logical signal and the previous Generate an exclusive OR with the logic signal and select the input scan signal and the exclusive OR to scan out to the scan path. Since, it is possible to shorten the test time by reducing the shift operation number of the scan-out test results.

According to the fourteenth aspect of the present invention, a boundary scan cancel circuit is connected to the input / output pins of a plurality of integrated circuits, and a scan path is formed which connects the boundary lease cancel circuits in series. As a boundary scan test method using the darry scan test circuit, connect the wiring under test between the output pin and the input pin of the integrated circuit and input from the scan path to the output boundary lease cancel circuit of the integrated circuit on the output pin side. The scan signal to be scanned in is stored for a certain period of time, the inverted signal of the stored scan signal is generated, and the next input scan signal and the inverted previous scan signal are alternately selected. Since it is input to the wiring under test, the shift operation for scanning in the inversion logic of the test data is unnecessary. And in, it is possible to shorten the test time.

[Brief description of drawings]

FIG. 1 is an electric circuit diagram showing a configuration of a boundary lease cancel circuit according to a first embodiment.

FIG. 2 is a state transition diagram showing a change in control state and a change in control signal in each control mode in a 0/1 stuck-at fault test using the boundary lease cancel circuit of the first embodiment.

FIG. 3 is an explanatory diagram showing a flow of test results in each control state in each control mode in the 0/1 stuck-at fault test using the boundary lease cancel circuit of the first embodiment.

FIG. 4 is an electric circuit diagram showing a configuration of a boundary lease cancel circuit according to a second embodiment.

FIG. 5 is a state transition diagram showing a change in control mode during each control mode and a change in control signal in a 0/1 stuck-at fault test using the boundary lease cancel circuit of the second embodiment.

FIG. 6 is an explanatory diagram showing the flow of test data in each control mode in each control mode in the 0/1 stuck-at fault test using the boundary lease cancel circuit of the second embodiment.

FIG. 7 is an electric circuit diagram showing a configuration of a boundary scan test circuit according to a third embodiment.

FIG. 8 is an explanatory diagram showing changes in control signals during each control mode and a flow of test data and test results in a 0/1 stuck-at fault test using the boundary scan test circuit of the third embodiment.

FIG. 9 is an electric circuit diagram showing a configuration of a boundary scan test circuit according to a fourth embodiment.

FIG. 10 is an electric circuit diagram showing a configuration of a boundary lease cancel circuit according to a fifth embodiment.

FIG. 11 is a block diagram showing the configuration of the invention of claim 1;

FIG. 12 is a block diagram showing the configuration of the invention of claim 3;

FIG. 13 is a block diagram showing a configuration of a conventional general boundary scan test circuit.

FIG. 14 is an electric circuit diagram showing a configuration of a conventional boundary lease cancel circuit.

FIG. 15 is an electric circuit diagram showing a connection relationship between a conventional output boundary lease cancel circuit and an output boundary lease cancel circuit.

FIG. 16 is a state transition diagram showing a change in control mode in a conventional 0/1 stuck-at fault test.

[Explanation of symbols]

100 Boundary Cancel Circuit 101 Logic Input Terminal 102 First Selector 103 Second Selector 104 First Flip-Flop (Input Logic Storage Means) 105 Second Flip-Flop (Input Scan Storage Means, Inversion Signal Generation Means, Alternate Signal Output Means) 106 scan input terminal 107 buffer 108 scan output terminal 109 logic output terminal 110 control terminal 111 third selector (selecting means) 112 arithmetic unit (exclusive OR generating means) 150 scan path 200 boundary scan test circuit 210, 220, ... Integrated circuit 212, 222, ... Internal logic 213, 223, ... TAP controller 215, 225, ... Connection terminal (input pin or output pin) Wts Wiring under test

Claims (14)

[Claims] 1. A logic input terminal for receiving a logic signal input from the outside, a scan input terminal for receiving a scan signal input from the outside, a scan output terminal for outputting a scan signal to the outside, and the logic input. Input logic storage means for inputting a logic signal input through a terminal and storing and outputting the logic signal for a fixed time; logic signal output from the input logic storage means before a fixed time and the logic input An exclusive OR generating means for generating an exclusive OR of the previous logical signal and the current logical signal by inputting the current logical signal input via the terminal, and the input via the scan input terminal. The scan signal and the exclusive OR signal generated by the exclusive OR generating means are input, and the input scan signal and the exclusive OR are selected according to the control signal, Boundary scan circuit, characterized in that a scan selection means for outputting to the outside through the scan output terminal. 2. The boundary cancel circuit according to claim 1, wherein the logic signal from the logic input terminal and the scan signal from the scan input terminal are input, and a logic signal and a scan signal are input according to a control signal. The scan selection means is provided with an input selection means for selecting one of them and outputting it to the exclusive OR generation means. The scan selection means has an input side connected to an output side of the input selection means and an output side of the exclusive OR generation means. The input logic storage means has an input side connected to the output side of the scan selection means and an output side connected to the scan output terminal, and holds an input logic signal which outputs an input logic signal or an exclusive OR signal according to a clock signal. And a scan output terminal connected to a non-inverting output terminal of the input holding flip-flop. Boundary-Scan circuit. 3. A logic output terminal for outputting a logic signal, a scan input terminal for receiving a scan signal input from the outside, a scan output terminal for outputting a scan signal to the outside, and a scan input terminal via the scan input terminal. Input scan storage means for storing an input scan signal for a certain period of time and then outputting the same; inversion signal generation means for receiving the output of the input scan storage means as an input and generating an inverted signal of the input scan signal; Input selection means, which is connected to the scan input terminal and the inverted signal generation means and whose output side is connected to the input scan storage means, and which alternately selects and outputs the input scan signal and its inverted signal according to the control signal; After holding the alternating signal of the input scan signal selected by the input selection means and its inverted signal for a certain period of time, through the logic output terminal Boundary cancel circuit, characterized in that the scan output terminal is connected to a signal line between the scan input terminal and the input selection means. 4. The boundary scan circuit according to claim 3, wherein the input scan storage means, the inverted signal generation means, and the alternate signal output means output a non-inverted signal and an inverted signal of the input signal according to a clock signal. Of the input scan holding flip-flops, each of which is output from two output terminals. The logic output terminal is connected to the output terminal of the non-inverted signal of the input scan holding flip-flop. A boundary lease cancel circuit characterized in that the input side is connected to the scan input terminal and the output terminal of the inverted signal of the input scan holding flip-flop and the output side is connected to the input terminal of the input scan holding flip-flop. . 5. The boundary lease cancel circuit according to claim 1, wherein a logical output terminal for outputting a logical signal and a scan signal input from the scan input terminal to the boundary lease cancel circuit are input, An input scan storage means for storing and outputting a scan signal for a certain period of time; an inversion signal generation means for receiving an output of the input scan storage means and generating an inversion signal of the input scan signal; And an output logic selecting means which receives the output and the output of the inverted signal generating means as input, selects an input scan signal and an inverted signal of the input scan signal according to the control signal, and outputs the selected signal to the outside through the logic output terminal. A boundary lease cancel circuit characterized by being provided. 6. A plurality of integrated circuits having an internal logic and an input pin for inputting a logic signal to the internal logic from the outside, and an output pin for outputting a logic signal from the internal logic to the outside, and the plurality of integrated circuits. Between the input pin of one of the integrated circuits and the output pin of the other integrated circuit, a wiring mounting portion to which a wiring to be tested for testing the connection / disconnection state is mounted, the input pin of each integrated circuit, and the internal logic An input boundary lease cancel circuit interposed between the
In a boundary scan test circuit having an output boundary lease cancel circuit provided between the output pin of each integrated circuit and the internal logic, and a scan path connecting the boundary lease cancel circuits in series, The input boundary lease cancel circuit includes a logic input terminal connected to the input pin, a scan input terminal for receiving a scan signal from the scan path, and a scan output terminal for outputting a scan signal to the scan path. And an input logic storage means for receiving a logic signal input through the logic input terminal as an input, storing the logic signal for a predetermined time and outputting the logic signal, and a logic output from the input logic storage means before a predetermined time. The signal and the current logic signal input via the logic input terminal are input, and the previous logic signal and the current logic An exclusive-OR generating means for generating an exclusive-OR with a signal, and a scan signal input through the scan input terminal and an exclusive-OR signal generated by the exclusive-OR generating means as inputs, Boundary scan test circuit is provided with scan selection means for selecting an input scan signal and an exclusive OR according to a control signal and outputting the result to a scan path via the scan output terminal. . 7. The boundary scan test circuit according to claim 6, wherein the logic signal from the logic input terminal and the scan signal from the scan input terminal are input, and a logic signal and a scan signal are input according to a control signal. The scan selection means is provided with an input selection means for selecting one of them and outputting it to the exclusive OR generation means, wherein the input side of the scan selection means is connected to the output side of the input selection means and the output side of the exclusive OR generation means. The input logic storage means has an input side connected to the output side of the scan selection means and an output side connected to the scan output terminal, and holds an input logic signal which outputs an input logic signal or an exclusive OR signal according to a clock signal. And a scan output terminal connected to a non-inverting output terminal of the input holding flip-flop. Boundary scan test circuit to be. 8. A plurality of integrated circuits having internal logic, an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside, and the plurality of integrated circuits. Between the input pin of any one of the integrated circuits and the output pin of the other integrated circuit, a wiring attachment part to which a wiring to be tested for testing the connection / disconnection state is attached, the input pin of each integrated circuit and the internal logic An input boundary lease cancel circuit interposed between the
In a boundary scan test circuit including an output boundary lease cancel circuit provided between the output pin of each integrated circuit and the internal logic, and a scan path connecting the boundary lease cancel circuits in series, The output boundary lease cancel circuit includes a logic output terminal connected to an output pin, a scan output terminal for outputting a scan signal to the scan path, and a scan input terminal for receiving a scan signal from the scan path. And an input scan storage means for receiving a scan signal input through the scan input terminal, storing the input scan signal for a certain period of time, and then outputting the input scan signal, and inputting an output of the input scan storage means for input scan. Inversion signal generating means for generating an inversion signal of the signal, and the input side is the scan input terminal And an input selecting means connected to the input signal storing means and an output side thereof connected to the input scan storing means, and alternately selecting the input scan signal and its inverted signal according to the control signal, and the input selecting means. An alternate signal output means for outputting an alternate signal of the input scan signal and its inverted signal after holding it for a certain period of time is provided, and the scan output terminal is a signal between the scan input terminal and the input selection means. Boundary scan test circuit characterized by being connected to a wire. 9. The boundary scan test circuit according to claim 8, wherein the input scan storage means, the inverted signal generation means and the alternate signal output means output a non-inverted signal and an inverted signal of the input signal according to a clock signal. Of the input scan holding flip-flop for outputting from the two output terminals, the logic output terminal is connected to the output terminal of the non-inverted signal of the input scan holding flip-flop, and the input selecting means is A boundary scan test circuit, wherein an input side is connected to the scan input terminal and an output terminal of an inversion signal of an input scan holding flip-flop, and an output side is connected to an input terminal of the input scan holding flip-flop. 10. The boundary scan test circuit according to claim 6 or 7, wherein an output boundary cell circuit is arranged in the integrated circuit in which the input boundary cell circuit is arranged, The output boundary lease cancel circuit includes a logic output terminal connected to an output pin, a scan input terminal for receiving a scan signal from the scan path, and a scan output terminal for outputting a scan signal to the scan path. An input scan signal that receives a scan signal input through the scan input terminal, stores the input scan signal for a certain period of time, and then outputs the input scan signal; Signal generating means for generating an inverted signal of the scan input terminal and the inverted signal generating means on the input side. And an input side connected to the input scan storage means, which is connected to the output side, and which alternately selects an input scan signal and its inverted signal according to a control signal; and an input scan signal selected by the input selection means. An alternate signal output means for outputting the alternate signal with the inverted signal after holding for a certain period of time is provided, and the scan output terminal is connected to a signal line between the scan input terminal and the input selection means. A boundary scan test circuit characterized in that 11. The boundary scan test circuit according to claim 8 or 9, wherein an input boundary cell circuit is arranged in an integrated circuit in which the output boundary cell circuit is arranged, The input boundary scan circuit includes a logic input terminal connected to the input pin, a scan input terminal for receiving a scan signal from the scan path, and a scan output terminal for outputting a scan signal to the scan path. An input logic storage means for receiving a logic signal input through the logic input terminal, storing the logic signal for a fixed time and outputting the logic signal, and a logic signal output from the input logic storage means before the fixed time And the current logic signal input via the logic input terminal, and the exclusive OR of the previous logic signal and the current logic signal The exclusive-OR generating means for generating, the scan signal input through the scan input terminal, and the exclusive-OR signal generated by the exclusive-OR generating means are input, and the input scan is performed according to the control signal. A boundary scan test circuit, further comprising: a scan selection unit that selects a signal and an exclusive OR and outputs the selected signal to a scan path via the scan output terminal. 12. A plurality of integrated circuits having internal logic, an input pin for inputting a logic signal from the outside to the internal logic, and an output pin for outputting a logic signal from the internal logic to the outside, and the plurality of integrated circuits. Between the input pin of any one of the integrated circuits and the output pin of the other integrated circuit, a wiring attachment part to which a wiring to be tested for testing the connection / disconnection state is attached, the input pin of each integrated circuit and the internal logic The input boundary lease cancel circuit, the output boundary lease cancel circuit interposed between the output pin of each integrated circuit and the internal logic, and the boundary lease cancel circuit are connected in series. In a boundary scan test circuit including a scan path to be connected, the boundary scan cancel circuit for input and the boundary scan test for output The logic circuit includes a logic input terminal configured to input a logic signal, a scan input terminal for receiving a scan signal from the scan path, a scan output terminal for outputting a scan signal to the scan path, An input logic storage means for receiving a logic signal input through the logic input terminal as an input, storing the logic signal for a predetermined time and outputting the logic signal, and a logic signal output from the input logic storage means before the predetermined time and An exclusive OR generating means for generating an exclusive OR of the previous logical signal and the current logical signal by inputting the current logical signal input through the logical input terminal, and the scan input terminal. Input scan signal and the exclusive OR signal generated by the exclusive OR generating means are input, and the input scan signal and the exclusive OR signal are input according to the control signal. Scan selection means for selecting and outputting to the scan output terminal, a logic output terminal for outputting a logic signal, and a logic output terminal configured to be capable of outputting a logic signal for outputting a scan signal to the scan path, An input scan storage means for inputting a scan signal input to the boundary cancel circuit from the scan input terminal, storing the input scan signal for a fixed time, and outputting the input scan signal; and an input for the output of the input scan storage means, An inverted signal generation means for generating an inverted signal of the input scan signal, an input side connected to the scan input terminal and the inverted signal generation means and an output side connected to the input scan storage means, and an input scan signal according to a control signal. Input selection means for alternately selecting the input signal and its inverted signal, and the input scan selected by the input selection means. An alternate signal output means for outputting an alternate signal of the input signal and its inverted signal after holding it for a certain period of time, and the scan output terminal is connected to a signal line between the scan selecting means and the input selecting means. Boundary scan test circuit characterized by being 13. A plurality of integrated circuits each having an internal logic and an input pin for inputting a logic signal to the internal logic from the outside, and an output pin for outputting a logic signal from the internal logic to the outside, and each integrated circuit. An input boundary lease cancel circuit provided between the input pin and the internal logic,
A boundary scan test circuit including an output boundary lease cancel circuit provided between an output pin of each integrated circuit and internal logic and a scan path connecting each boundary lease cancel circuit in series is used. A boundary scan test method, comprising connecting a wiring under test between an output pin of at least one integrated circuit of the plurality of integrated circuits and an input pin of another integrated circuit, The output boundary lease cancel circuit of the integrated circuit on the output pin side successively outputs at a fixed time interval, and the logical signal input to the input boundary lease cancel circuit of the integrated circuit on the input pin side is stored for a fixed time. After this, the exclusive OR of the current logic signal and the previous logic signal input via the above input pin is generated, and Boundary scan test method characterized by scanning out the scan path select input scan signal inputted to the lease cancellation circuit and the exclusive OR. 14. A plurality of integrated circuits each having an internal logic and an input pin for inputting a logic signal to the internal logic from the outside, and an output pin for outputting a logic signal from the internal logic to the outside, and each integrated circuit. An input boundary lease cancel circuit provided between the input pin and the internal logic,
A boundary scan test circuit including an output boundary lease cancel circuit provided between an output pin of each integrated circuit and internal logic and a scan path connecting each boundary lease cancel circuit in series is used. A boundary scan test method, wherein a wiring to be tested is connected between an output pin of at least one integrated circuit of the plurality of integrated circuits and an input pin of another integrated circuit, and the output of the integrated circuit on the output pin side is connected. The scan signal input from the scan path to the boundary scan cancel circuit for scanning is scanned in and stored for a certain period of time, an inverted signal of the stored scan signal is generated, and input to the output boundary scan cancel circuit. Selected next scan signal and inverted previous scan signal are alternately selected and input to the wiring under test. A boundary scan test method characterized by: