KR100694315B1 - At-speed interconnect test controller for system on chip using multiple system clock and having heterogeneous cores - Google Patents

Abstract

The present invention relates to a link delay failure test controller capable of performing a link delay failure test between heterogeneous cores in a system on chip. The present invention includes a tap control unit for outputting a plurality of signals for inter-core connection line test according to the IEEE 1149.1 standard; When the delay test of the connection line starts, the first enable signal that outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock in the subsequent state and 0 otherwise, Capture_DR from the time when the Update_DR state starts An enable signal generator configured to generate a second enable signal that outputs 1 until the end of the state and 0 otherwise; Receives a system clock and a first enable signal, and outputs 0 in an initial state, and then outputs 1 at the first rising edge of the system clock after the first enable signal outputs 1 and the first enable signal. A first control signal generator configured to generate a Late_Update_DR signal that returns to an initial state when a signal is output 0; Receives a system clock and a first enable signal, outputs a 1 at an initial state, outputs a 0 on the first rising edge of the system clock after the first enable signal outputs a 1, and then on a rising edge. Including a second control signal generating unit for generating a sck_DR signal outputting 1, when the connection delay delay test is executed, within the Capture_DR state of the tap controller, the rising edge and the capture of the rising edge of the Late_Update_DR signal is generated It provides a connection line delay failure test controller, characterized in that the rising edge of the sck_DR signal occurs within one system clock.

IEEE 1149.1, P1500, Connector, Delay Fault, Tap Controller, Update, Capture, Multiple System Clock

Description

AT-SPEED INTERCONNECT TEST CONTROLLER FOR SYSTEM ON CHIP USING MULTIPLE SYSTEM CLOCK AND HAVING HETEROGENEOUS CORES}

1 is a block diagram illustrating a chip having one core designed for IEEE 1149.1 boundary scan.

2 is a finite state diagram of a tap controller used for testing a system on chip.

3 is a diagram illustrating the structure of a standard boundary scan cell.

4 is a block diagram illustrating a chip having one core designed as a boundary scan by P1500.

5 is a waveform diagram illustrating a waveform of a signal in a conventional connection line failure test.

6 is a block diagram showing a boundary scan cell structure used in a conventional early capture.

7 is a waveform diagram showing the waveform of a signal applied to a conventional early capture method.

8 is a waveform diagram showing a simulation result of a conventional rate update method.

FIG. 9 is a circuit diagram of a conventional Early Capture Control Register (ECCR) and Early Capture Latch (ECL) applied to a chip of 1149.1 boundary scan.

10 is a block diagram illustrating an example of a connection line delay failure test controller according to the present invention.

11 is a waveform diagram illustrating a waveform of a signal generated by a connection delay test controller according to the present invention.

12 is a waveform diagram illustrating waveforms of first and second enable signals generated by an enable signal generator of the present invention.

13 is a finite state diagram of the first control signal generator of the present invention.

14 is a finite state diagram of the second control signal generator of the present invention.

15 is a diagram illustrating a wrapper interface port controller.

16 is a block diagram of a connection line delay failure test controller according to the present invention that can be applied to a system on chip having multiple system clocks.

17 is a diagram illustrating an example of a system on a chip having heterogeneous cores to which a connection line delay failure test controller according to the present invention is applied.

18 and 19 are waveform diagrams illustrating simulation results of a connection line delay failure test performed in the system on chip illustrated in FIG. 17.

* Explanation of symbols for main parts of drawings *

100: connection line delay failure test controller 110: enable signal generation unit

120: first control signal generator 130: second control signal generator

140: tap control unit 150: first multiplexer

160: second multiplexer

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a link delay failure test controller applied to a System on Chip (SoC) having multiple system clocks and having a heterogeneous core. More specifically, a plurality of system clocks are used and an eye-triple- Test static and delay failures between the interconnects between these heterogeneous cores in a system-on-chip containing different types of cores that conform to the standards of the Institute of Electrical and Electronics Engineers (IEEE) 1149.1, IEEE P1500. The present invention relates to a connection delay test controller for system-on-chip comprising a heterogeneous core using multiple system clocks.

Recently, as the system-on-chip design technology that implements the system as a single chip has been developed to the nanometer level, the size of the system-on-chip has become smaller and the complexity has increased greatly, and the system speed for operating the system-on-chip has been increased. Gradually became faster. As a result, the increased complexity and higher system speeds make system-on-chip testing more difficult. In particular, a major bottleneck in system-on-chip design arises during the test and verification process, and therefore, an efficient system-on-chip test technique is urgently needed.

Because system-on-chip can contain many different cores, the number of interconnects that interconnect these cores also increases. When performing the connected test of the internal cores, there was no problem in the operation of the system if only the signal transmission was properly performed regardless of the speed, so that the stuck at fault, the open net fault and the shorted net It was sufficient to test for static failures. However, in the high speed operating system on chip, which is being developed recently, delay failure testing at the connection line is necessary because signal delay may cause the entire system to malfunction. This delay failure test is an increase in system-on-chip using multiple system clocks so that the delay failure test can be appropriately performed for each clock used in the connection line.

The above-described connection test of the system on a chip with heterogeneous cores will be described in detail. For the test of the connection between the cores embedded in the system on a chip, the board test standard is used as a standard for board testing on all chips. A core adopting IEEE 1149.1, a standard proposed by the IEEE, or a core adopting IEEE P1500 (hereinafter referred to as P1500), which is proposed to test cores on a system on chip and is currently proposed as a standard, can be used. The P1500 uses commands, data, and bypass registers to perform partial functions of IEEE 1149.1 boundary scan and is directly supplied with control signals. As such, since the system on chip itself is one chip, IEEE 1149.1 is adopted, and since the heterogeneous cores adopting IEEE 1149.1 and P1500 can be embedded therein, these heterogeneous cores are embedded in one system on chip. You should be able to perform line test in your environment. Cores employing the IEEE 1149.1 and P1500 will be described in more detail with reference to the accompanying drawings.

The IEEE 1149.1 is widely used in a non-memory chip currently manufactured by a boundary scan design method selected as a standard. Figure 1 shows a chip with one core designed for IEEE 1149.1 boundary scan. As shown in FIG. 1, a chip having an IEEE 1149.1 boundary scan structure includes a test access port (TAP), a tap controller 12, a command, and various test data registers 13. ).

The tab 11 is an input / output port of a chip required for 1149.1 boundary scan, and includes a test data input (TDI), a test data output (TDO), a test clock (TCK), Test Mode Select (TMS) and Test Reset (TRST *) signals are input and output. The tap controller 12 outputs a signal for controlling the operation of the various registers 13 by using the signals input through the tap 11. Each input pin (not shown) of the chip 1 injects a signal into the core 15 within the chip through the associated boundary scan cell 14, and the signal generated from the core 15 is a boundary scan cell 14. )) To the outside of the chip.

In addition to the boundary scan registers, the test data registers include a bypass register and an idcode register, which can be added by the user for special purposes. The instruction register arranges corresponding registers among the test data registers between the test data input (TDI) and the test data output (TDO) paths according to the input instructions.

1149.1 Instructions used in boundary scan include the required instructions BYPASS, EXTEST, SAMPLE / PRELOAD and optional instructions CLAMP, INTEST, RUN. RUNBIST. The BYPASS command is a command that allows the data coming into the test data input (TDI) to be directly sent to the test data output (TDO) in one clock instead of through the boundary scan cell (14). It allows you to pass the chip and shorten the test time. EXEST is a command used to test the chip-to-chip connection.SAMPLE / PRELOAD is used to pull out the boundary scan cell to the outside or during normal operation. This command allows you to load a test pattern into a boundary scan cell.

FIG. 2 is a finite state diagram of the tap controller 12 of FIG. 1 used for testing the chip. The 16 states shown in FIG. 2 include a state in which a tap controller is initialized (Test-Logic-Reset), a standby state (Run-Test / Idle), a state related to a data register (Select-DR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, Update-DR) and status associated with instruction registers (Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2) -IR, Update-IR).

In FIG. 2, Select-DR-Scan, Exit1-DR, Pause-DR, and Exit2-DR are temporary states among the states related to the data register, and the injection force value of the core, that is, the value at the normal operation of the core, in the Capture-DR state. In this boundary scan cell, the test data values are shifted to the next connected boundary scan cells in the shift-DR state, and the test data values are output in parallel in the update-DR state.

The state related to the instruction register is the instruction register as the target, and the operation itself performs the same operation as the state related to the data. The state of the tap controller transitions according to the test mode selection (TMS) value when the test clock (TCK) rises, and outputs nine signals controlling the register according to each state. The nine control signals are detailed in Table 1 below.

signal Related register Explanation Valid status Shiftir Instruction register select signal Shift_IR state Clockir clock signal Capture_IR & Shift_IR Status UpdateIR clock signal Update_IR status Reset reset signal Test_Logic_Reset Status ShiftDR Data register select signal Shift_DR state ClockDR clock signal Capture_DR & Shift_DR Status UpdateDR clock signal Update_DR Status Select · select signal Command status Enable · TDO driver Shift_IR & Shift_DR Status

3 illustrates the structure of a standard boundary scan cell (14 in FIG. 1). If the data cells of the IEEE 1149.1 and P1500 are in the form of the standard cells of FIG. 3, the data transferred through the update latch on one core (operating the update latch on the rising edge of the Update_DR signal) 31 is transferred to the other core. In the method of receiving through the capture latch (Capture Latch: operates the capture latch on the rising edge of the Clock_DR signal) 32 to test the connection line between the cores.

Meanwhile, IEEE P1500 is a core level test wrapper proposed to test various cores in a structure suitable for testing system-on-chip embedded cores. The core test wrapper defined by the P1500 has the following features:

* A subset of the modes provided by IEEE 1149.1 boundary scan, supporting internal core testing, connector testing, and bypass modes.

Core test wrappers can be connected to the core's internal scan chain for use in SoC internal testing (supporting various Test Access Mechanisms (TAMs)).

There is no module that gives control signals, such as the tap controller for IEEE 1149.1 boundary scan.

4 shows a chip with one core designed for boundary scan by P1500. 4 is a structure of a P1500, which must be provided from the outside through various registers such as the P1500 instruction register and the core test data register, the TAM connection unit (TAM-IN, TAM-OUT), and a wrapper interface port (WIP). Various control signals are shown.

Signals input through the WIP are composed of six control signals as shown in FIG. WRCK is a test clock for the wrapper instruction register (WIR), the wrapper bypass register (WBY), and the wrapper boundary register (WBR), and the WRSTN is a wrapper reset signal. SelectWIR is a signal that selects whether an instruction register or test data register is placed between the wrapper serial input (WSI) and the wrapper serial output (WSO). do. CaptureWR, ShiftWR, and UpdateWR allow capture, shift, and update operations to occur in the selected register, respectively. The UpdateWR signal is a clock itself, but the CaptureWR and ShiftWR signals are select signals, which must be synchronized with the WRCK in the command and test data cells to enable capture and shift operations.

A process of performing a connection line test between cores through IEEE 1149.1 will be described in more detail with reference to FIGS. 2 to 3 as follows.

First, read and decode the EXTEST command, which is the command used to test the connection (Test-Logic-Reset ⇒ Run-Test-IDLE ⇒ Select-DR-Scan ⇒ Select-IR-Scan ⇒ Capture-IR ⇒ Shift-IR ⇒ … ⇒ Exit1-IR ⇒ Update-IR), the test pattern is read through the boundary scan register in series (Select-DR-Scan ⇒ Capture-DR ⇒ Shift-DR ⇒… ⇒ Exit1-DR). Then, the read test pattern is updated through the update latch, and the captured value is captured in the capture latch of the input boundary scan cell of the chip to be observed (Update-DR ⇒ Select-DR-Scan ⇒ Capture-DR), The captured value of the input boundary scan cell is output to the TDO through a boundary scan register (Capture-DR Shift Shift-DR ⇒... Exit1-DR). In this case, the connection line test between the cores may be performed by updating the test pattern (when the Update_DR signal is input in the Update-DR state) and capturing (when the Clock_DR signal is input in the Capture-DR state) during the EXTEST command.

The signal waveform at the time of such a connection test is shown in FIG. As shown in FIG. 5, a 2.5 test clock TCK is required from a time point t1 at which an update occurs in an update latch of an output boundary scan cell to a time point t2 at which a capture occurs in a capture latch of an input boundary scan cell. In other words, the capture latch of the input boundary scan cell operates when the rising edge of the Clock_DR signal 52 occurs after the update latch of the output boundary scan cell operates when the rising edge of the Update_DR signal 51 occurs. It takes up to 2.5 test clocks. This takes more clock than the Run-Test-Idle state in minimum time. If this test is performed, static failure test such as disconnection or short circuit can be performed regardless of the test clock. Therefore, it can be tested and diagnosed. However, delay failure test is more than 2.5 test clock because it is testing time delay. In this case, it is impossible to test the occurrence of delay itself. That is, the test for delay failure for normal operation of the system should take one system clock (SCK) from the update operation to the capture operation.

In order to solve the problem of such a delay failure test, conventionally proposed techniques include early capture (K. Lofstrom, "EARLY CAPTURE FOR BOUNDARY SCAN TIMING MEASUREMENTS", Proceedings of IEEE International Test Conference, pp. 417- 422, 1996) and Late Update method (S Park and T Kim, "A New IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS", Design, Automation and Test in Europe Conference, pp. 458-462, At-speed Boundary-scan Interconnect Testing (Jongchul Shin, Hyunjin Kim, and Sungho Kang, "AT-SPEED BOUNDARY-SCAN INTERCONNECT TESTING IN A BOARD WITH MULTIPLE SYSTEM CLOCKS," Design Automation and Test in Europe Conference, 1999.).

6 is a boundary scan cell structure used in conventional early capture. The latch indicated at 61 in FIG. 6 is an early capture latch that operates differently from other edge triggered latches around the level sensitive latch. The early capture latch 61 operates according to the value of the early capture clock 71 shown in FIG. In normal operation or normally, the early capture clock 71 has a value of 1 so that the injection force value passes, but after the falling edge of the TMS signal 72 after UpdateDR, the early capture clock 71 becomes 0 and becomes a Shift-DR state. The injection force value was held until the delay failure test was performed.

However, this method must change the structure of the boundary scan cell of the core or chip. That is, when compared to the structure of the standard boundary scan cell illustrated in FIG. 3, the boundary scan cell used in the early capture method should be changed to a structure in which a latch (61 of FIG. 6) for early capture is further added. Input lines must also be added. Therefore, in the chip or core having hundreds of pins, the structure of all boundary scan cells must be changed and additional input lines must be provided. In addition, this method uses a level-sensitive latch, so that the output signal of the chip must continue to pass through the latch during normal operation. Therefore, the processing speed is reduced. It is applicable only to the core of the 1149.1 boundary scan wrapper and can support multiple system clocks. There is no problem.

8 is a waveform diagram showing a simulation result of a conventional rate update method. Referring to FIG. 8, in the rate update, BS_Clk 81 is generated to perform a test clock (TCK) 82 instead. At this time, when the rising edge of the system clock (SYS_CLK) 83 is generated several times in the portion where one TCK rising edge should occur, when the test mode selection signal (TMS) 84 has the rising edge of SYS_CLK 83 It is recognized every time and the state of the tap controller is changed. Where there is a state change, there are several state changes. Not only is this approach completely incompatible with IEEE 1149.1, but it also requires test engineers to be familiar with the new TMS test patterns for delayed failure testing, and the complexity of the test is because the patterns vary with the test clock and system clock. There is this. The rate update is also applicable only to the core of the 1149.1 boundary scan wrapper and cannot support multiple system clocks.

FIG. 9 is a circuit diagram in which an early capture control register (ECCR) and an early capture latch (ECL), which are main circuits of At-speed Boundary-scan Interconnect Testing, are applied to a chip of 1149.1 boundary scan. . This method allows the early capture signal to be zero in ECCR after one system clock in which UpdateDR operation occurred, so that a delay failure test can be performed. Adding an ECCR to each chip generates an early capture signal that corresponds to the system clock on that connection, even with multiple system clocks. However, this method also has to change all input cells, and adds a command called ECCR_SETUP that sets up ECCR for delay failure test. Also, it is only applicable to chips or cores with IEEE 1149.1 boundary scan wrapper, and there is a problem that cannot be used for connection delay test between heterogeneous cores.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems of the prior art, and its object is to capture in an update operation during a delay test of a connection using a tap controller adopted as a standard for system on chip (IEEE 1149.1). By taking 1 system clock to capture operation, it is possible to test connection delay failure substantially. In particular, it is possible to test connection delay and connection delay between heterogeneous cores and to support multiple system clocks using multiple system clocks. To provide a connection delay test controller for system-on-chip comprising multiple system clocks and heterogeneous cores.

The present invention to achieve the above object,

A connection line delay failure test controller for testing a connection delay error between cores in a system on chip including a plurality of cores by using an externally input system clock, a test clock, and a test mode selection signal.

A tap controller configured to receive the test clock and a test mode selection signal and output a plurality of signals for inter-core connection line testing according to the IEEE 1149.1 standard;

The state of the tap control unit may be determined by receiving the test clock and a test mode selection signal, and outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock when the connection delay delay test starts. In other cases, the first enable signal that outputs 0 and the enable signal that generates a second enable signal that outputs 1 from the time when the Update_DR state starts to the time when the Capture_DR state ends, and outputs 0 in the other cases. Generation unit;

The system clock and the first enable signal are inputted, and 0 is output in an initial state, and then 1 is output at the first rising edge of the system clock after the first enable signal outputs 1, and the first enable signal is output. A first control signal generator configured to generate a Late_Update_DR signal that returns to an initial state when the enable signal is 0;

Receives the system clock and the first enable signal, outputs 1 in an initial state, outputs 0 at the first rising edge of the system clock after the first enable signal outputs 1, and then the rising edge. A second control signal generator configured to generate an sck_DR signal outputting 1 in the first order;

A first multiplexer for selectively outputting the Late_Update_DR signal when the second enable signal is 1 and an UpdateDR signal of the tap control unit when 0; And

Including a second multiplexer for selectively outputting the sck_DR signal when the first enable signal is 1, and the ClockDR signal of the tap control unit when 0,

When a connection line delay failure test is executed, in the Capture_DR state of the tap controller, a rising edge of the Late_Update_DR signal in which an update occurs and a rising edge of the sck_DR signal in which a capture occurs occurs within one system clock. A delay failure test controller is provided.

In one embodiment of the present invention, the tap control unit may be included in any core that conforms to IEEE 1149.1 of the plurality of cores, wherein the enable signal generator is a delay failure test for determining whether a connection line delay failure test is in progress. The determination signal may be input.

Preferably, the present invention further includes a wrapper interface port controller for receiving the test clock, the output signal of the tap control unit, and the output signals of the first and second multiplexers and converting the signal into a signal for testing a core according to IEEE P1500. Characterized in that.

In this case, the wrapper interface port controller may include: a ShiftWR signal combining a ShiftIR signal and a ShiftDR signal through an OR gate of the tap controller; An UpdateWR signal combining the UpdateIR signal of the tap control unit and the output signal of the first multiplex through an OR gate; A WRSTN and SelectWIR signal outputting the reset signal and the select signal of the tap control unit, respectively; A CaptureWR signal having a value of 1 in a Capture_IR state and a Capture_DR state by combining a ClockIR, ShiftIR, ShiftDR signal, and an output signal of the second multiplexer, and 0 in the rest of the tap control unit; And a WRCK signal obtained by multiplexing the test clock and the ClockDR signal when the tap controller is in the Capture_DR state.

In particular, the CaptureWR signal is a signal in which the rising edge occurs at the falling edge of the ShiftIR signal when the ClockIR signal of the tap control unit is 0, and the falling edge is generated after maintaining the value of '1' for one test clock. Alternatively, when the output signal of the second multiplexer is '0', the rising edge is generated at the falling edge of the ShiftDR signal, and the falling edge is generated after maintaining the value of '1' for one test clock.

The present invention can be employed in a system on chip using a plurality of system clocks. In the connection line delay failure test controller between cores having multiple system clocks according to the present invention,

A connection line delay failure test controller for testing a connection delay failure between cores in a system on chip including a plurality of cores by using n system clocks, test clocks, and test mode selection signals input from an external device,

A tap controller configured to receive the test clock and a test mode selection signal and output a plurality of signals for inter-core connection line testing according to the IEEE 1149.1 standard;

The state of the tap control unit may be determined by receiving the test clock and a test mode selection signal, and outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock when the connection delay delay test starts. In other cases, the first enable signal that outputs 0 and the enable signal that generates a second enable signal that outputs 1 from the time when the Update_DR state starts to the time when the Capture_DR state ends, and outputs 0 in the other cases. Generation unit;

The first enable signal and the n system clocks are input one by one, and a zero is output in an initial state, and then a one is output on a first rising edge of the received system clock after the first enable signal outputs one. And n first control signal generators generating Late_Update_DR signals according to respective system clocks returning to an initial state when the first enable signal is 0;

Receives the first enable signal and the n system clocks, respectively, and outputs 1 in an initial state, and then outputs 0 at the first rising edge of the received system clock after the first enable signal outputs 1; And n second control signal generators generating sck_DR signals according to respective system clocks that output 1 on the next rising edge;

N first multiplexers for selectively outputting a Late_Update_DR signal according to each system clock when the second enable signal is 1 and an UpdateDR signal of the tap controller by 0; And

If the first enable signal is 1, including the sck_DR signal according to each of the system clock, and if it is 0, n second multiplexers for selectively outputting the ClockDR signal of the tap control unit,

When the connection delay failure test is executed, the rising edge of the Late_Update_DR signal according to each system clock in which an update occurs and the rising edge of sck_DR signal according to each system clock in which a capture occurs within the Capture_DR state of the tap controller. Characterized in the system clock.

In addition, the present invention provides a system-on-chip equipped with the above-described link delay failure test controller. System on a chip according to the present invention includes a connection line delay failure test controller described above; And a plurality of heterogeneous cores receiving signals for connection line delay failures from the connection line delay failure test controller.

Hereinafter, a connection line delay failure test controller and a system on chip having the same will be described in detail with reference to the accompanying drawings.

10 is a block diagram illustrating an example of a connection line delay failure test controller according to the present invention. Referring to FIG. 10, a connection line delay failure test controller 100 according to the present invention may include a tap controller 140; An enable signal generator 110; A first control signal generator 120; A second control signal generator 130; First multiplexer 150; And a second multiplexer 160.

The tap control unit 140 receives a test clock and a test mode selection signal and outputs a plurality of signals for inter-core connection line testing according to the IEEE 1149.1 standard. Since the signal output from the tap controller 140 is described in detail in Table 1, description thereof will be omitted.

The enable signal generation unit 110 may receive the test clock and the test mode selection signal to determine the state of the tap control unit 140. When the connection delay delay test starts, the enable signal generator 110 starts the capture_DR state. In the subsequent state, 1 is outputted to the falling edge of the test clock, and in the other case, 1 is outputted from the time when the first enable signal cap_EN and Update_DR state starts to the time when Capture_DR state ends, and in the other case, Generates a second enable signal updr_EN that outputs zero.

The first enable signal cap_EN has a value of 0 and has a value of 1 from the Capture_DR state to the falling edge of the test clock in the subsequent state when the connection delay test is started. Only the Capture_DR state after the Update_DR state is enabled so that unnecessary operation does not occur in the Capture_DR state when the test pattern is input. The first enable signal cap_EN becomes an enable signal of the first control signal generator 120 and the second control signal generator 130, and the second multiplexer 160 causes the second control signal. The signal generated by the generation unit 130 becomes a selection signal for replacing the ClockDR signal of the tap control unit 140.

The second enable signal updr_EN has a value of 0 and has a value only from the Update_DR state to the Capture_DR state after the test pattern is input during the connection delay test. The second enable signal updr_EN becomes a selection signal for selecting the control signal generated by the first control signal generator instead of the UpdateDR signal of the tap controller 140 during the connection line delay failure test.

The first control signal generator 120 receives a system clock and a first enable signal, outputs 0 in an initial state, and then first rises an edge of the system clock after the first enable signal outputs 1. Outputs a 1 and generates a Late_Update_DR signal that returns to an initial state when the first enable signal is 0. In addition, the second control signal generator 130 receives a system clock and a first enable signal, outputs 1 in an initial state, and then first rises the system clock after the first enable signal outputs 1. Generate a sck_DR signal that outputs 0 on the edge and then 1 on the rising edge. The Late_Update_DR signal and the sck_DR signal are signals that replace the UpdateDR signal and the ClockDR signal of the tap controller 140 when the connection line delay failure test is performed.

In the present invention, a basic concept for generating an update and capture within a system clock is to generate a signal for update and capture in accordance with the system clock in the Capture_DR state of the tap controller 140. FIG. 11 illustrates waveforms of signals generated by the connection delay test controller according to the present invention. The late_update_DR signals generated by the first control signal generator 120 and the second control signal generator 130 are generated by the second control signal generator 130. The sck_DR signal is a signal that replaces the UpdateDR signal and the ClockDR signal of the tap controller 140 when the connection line delay failure test is performed.

Referring to FIGS. 10 and 11, the operation of each component is performed. The first control signal generator 120 and the second control signal generator 130 both perform a state transition when the system clock rises. As a finite state machine, until the first enable signal cap_EN (S13) generated by the enable signal generator is 1, the initial state is late, and the late_update_DR signal S14 outputs 0 and sck_DR (S15) Outputs 1 The value of the first enable signal cap_EN (S13) is continuously checked. If the value is 1, the value of late_update_DR (S14) is set to the rising edge of the first system clock (SCK) S12 that recognizes the value. It outputs 1 and the value of sck_DR (S15) goes down to 0 and then goes back to 1 at the rising edge of the next system clock (S12).

The first multiplexer 150 selectively outputs the Late_Update_DR signal when the second enable signal updr_EN is 1 and an UpdateDR signal of the tap controller by 0 when the second enable signal updr_EN is 1, and the second multiplexer 160 outputs the UpdateDR signal. When the first enable signal cap_EN is 1, the sck_DR signal is output, and when 0, the ClockDR signal of the tap controller is selectively output.

12 is a waveform diagram illustrating waveforms of the first and second enable signals generated by the enable signal generator 110. Referring to FIG. 12, since the second enable signal updr_EN S23 has a value of 1 from the Update_DR state, Update_DR of the subsequent tap controller is ignored and late-update-DR for the connection delay test is performed. You can see that it can be selected.

As described above, the first control signal generator 120 and the second control signal generator 130 are finite state machines whose state is shifted by a system clock. The first control signal generator 120 may have two states, and the second control signal generator 130 may have three states. 13 is a state transition diagram of the first control signal generator 120, and FIG. 14 is a state transition diagram of the second control signal generator 130. Both the first control signal generator 120 and the second control signal generator 130 check the value of the first enable signal cap_EN. When the first enable signal cap_EN becomes a valid value, the first control signal generator 120 and the second control signal generator 130 transition to the next state. . In this case, the first control signal generator 120 sets late_update_DR from 0 to 1 and the second control signal generator 130 changes sck_DR from 1 to 0. Then, the first control signal generator 120 remains in the LUPDR state until the first enable signal cap_EN becomes 0 and the second control signal generator 130 immediately after one system clock irrespective of the signal. While changing the state, change the sck_DR signal from 0 to 1. This takes 1 system clock from update to capture. At this time, the update latch operates only at Update_DR, so it does not matter even if the late_update_DR signal remains 1 until cap_EN becomes 0.

As described above, according to the connection line delay failure test controller of the present invention, when the connection delay delay test is performed, updateDR of the late_update_DR signal and the sck_DR signal generated by the first control signal generator and the second control signal generator, respectively, By using this in place of the signal and the ClockDR signal, updates and captures can occur within the Capture_DR state. This means that updates and captures can occur within one system clock to test for delayed failures on the wire.

In addition, the present invention includes the first and second control signal generators to generate new late_update_DR signal and sck_DR, thereby performing connection line delay failure test without modifying the internal structure of the tap controller applied to IEEE 1149.1.

The present invention may further include a wrapper interface port controller for converting a control signal output from the connection delay test controller shown in FIG. 10 into a control signal suitable for the P1500 core to be applied to a heterogeneous core along the P1500. FIG. 15 illustrates a wrapper interface port controller 500 that receives output signals from the tap controller 140 and the first and second multiplexers 150 and 160 of FIG. 10 and converts the output signals into control signals suitable for P1500 cores.

The control signal for the P1500 core generated by the wrapper interface port controller 500 is as follows. The ShiftWR signal is a signal obtained by combining the ShiftIR signal and the ShiftDR signal of the tap control unit through an OR gate. The UpdateWR signal is a signal obtained by combining an UpdateIR signal of the tap control unit and an output signal of the first multiplex through an OR gate. The WRSTN and SelectWIR signals are signals obtained by outputting the reset signal and the select signal of the tap control unit, respectively. The CaptureWR signal is a signal having a value of 1 in the Capture_IR state and the Capture_DR state by combining the ClockIR, ShiftIR and ShiftDR signals of the tap control unit and the output signals of the second multiplexer, and having a value of 0 in the rest. The WRCK signal is a signal obtained by multiplexing the test clock and the ClockDR signal when the tap control unit is in the Capture_DR state.

In particular, the CaptureWR signal is a signal in which the rising edge occurs at the falling edge of the ShiftIR signal when the ClockIR signal of the tap control unit is 0, and the falling edge is generated after maintaining the value of '1' for one test clock. Alternatively, when the output signal of the second multiplexer is '0', the rising edge is generated at the falling edge of the ShiftDR signal, and the falling edge is generated after maintaining the value of '1' for one test clock.

On the other hand, the present invention has a feature that can be easily applied in a system on a chip having multiple system clocks. 16 illustrates a lead delay failure test controller that may be applied to a system on chip with multiple system clocks. Referring to FIG. 16, a connection delay failure test controller applied to a system on chip having multiple system clocks receives the test clock and a test mode selection signal, and receives a plurality of signals for inter-core connection testing according to the IEEE 1149.1 standard. An output tap control unit; The state of the tap control unit may be determined by receiving the test clock and a test mode selection signal, and outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock when the connection delay delay test starts. In other cases, the first enable signal that outputs 0 and the enable signal that generates a second enable signal that outputs 1 from the time when the Update_DR state starts to the time when the Capture_DR state ends, and outputs 0 in the other cases. Generation unit; The first enable signal and the n system clocks are input one by one, and a zero is output in an initial state, and then a one is output on a first rising edge of the received system clock after the first enable signal outputs one. And n first control signal generators generating Late_Update_DR signals according to respective system clocks, which return to an initial state when the first enable signal is 0; Receives the first enable signal and the n system clocks, respectively, and outputs 1 in an initial state, and then outputs 0 at the first rising edge of the received system clock after the first enable signal outputs 1; And n second control signal generators generating sck_DR signals according to respective system clocks that output 1 on the next rising edge; N first multiplexers for selectively outputting a Late_Update_DR signal according to each system clock when the second enable signal is 1 and an UpdateDR signal of the tap controller by 0; And n second multiplexers for selectively outputting a sck_DR signal corresponding to each system clock when the first enable signal is 1 and a ClockDR signal of the tap controller by 0 when the first enable signal is 0.

Referring to FIG. 16, a connection delay test controller applied to a system on chip having multiple system clocks may include a first control for generating a late_update_DR signal and a sck_DR signal by a system clock in the connection delay test controller illustrated in FIG. 10. The signal generator and the second control signal generator may be added according to the number of system clocks. That is, the present invention separately includes the first and second control signal generators for generating the late_update_DR signal and the sck_DR to replace the UpdateDR signal and the ClockDR signal of the tap controller according to the system clock, so that the system clock used in the system-on-chip By increasing the first and second control signal generation unit according to the number, it can be easily applied to a system on chip having multiple system clocks.

17 shows an example of a system on chip with heterogeneous cores to which a link delay failure test controller according to the present invention is applied. The system-on-chip 700 shown in FIG. 17 includes one core 710 compliant with IEEE 1149.1 and two cores 720 and 730 compliant with P1500, and a connection delay test controller 740 for checking this. ). The connection line delay failure test controller 740 additionally includes a wrapper interface port controller 742 that generates a signal for controlling a core according to P1500 to the basic connection delay test controller 741 shown in FIG. 10. Take form. A signal output from the basic connection line delay failure test controller 741 shown in FIG. 10 is input to the core 710 according to IEEE 1149.1, and the wrapper interface port control unit is provided to two cores 720 and 730 that follow P1500. In step 742, the converted output signal is input and the connection delay test is performed. On the other hand, since one core 710 according to IEEE 1149.1 has a tap control part therein, the tap control part inside the core may be changed to the basic connection line delay failure test controller 711 shown in FIG. 10.

18 and 19 are waveform diagrams illustrating simulation results of a connection line delay failure test performed in the system on chip illustrated in FIG. 17. FIG. 18 is a verification simulation result when both connection lines use the same system clock, and FIG. 19 is a verification simulation result when different system clocks are used.

First, referring to FIG. 18, a test result from the TDO is reported that the value provided on the connection line of two cores 720 and 730 along the P1500 of FIG. 17 is properly transmitted to only one system clock. Able to know. At this time, it can be seen that the signal transfer takes one system clock from the application operation to the capture operation. The simulation waveform shows that the WRCK is multiplexed with ClockDR while the CaptureWR signal is set to 1 so that it captures only one system clock after an authorization operation.

Next, referring to FIG. 19, the connection between core 720 according to P1500 of FIG. 17 and core 710 according to IEEE 1149.1 is operated at system clock 1 and core 730 and IEEE following another P1500. The connection between the cores 710 following 1149.1 is the result of experimenting with the system clock 2. The simulation results show that the capture operation starts from the application operation in one system clock according to each system clock.

Through the above verification, it can be confirmed that the present invention properly performs a delay failure check test in a system on chip environment having multiple system clocks and heterogeneous cores.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution, modification, and within the scope not departing from the technical spirit of the present invention described in the claims. It will be apparent to those skilled in the art that changes are possible.

As described above, according to the present invention, since only a few components need to be added to the tap control unit when the connection delay tester is directly applied to the system on chip, a minimum circuit change is possible when designing the system on chip.

In addition, according to the present invention, if the original tap control unit is present in the system-on-chip when the circuit is changed, the connection delay delay check test controller can be configured using the tap control unit as it is, so that the core can be reused.

In addition, according to the present invention, the test can be easily performed by maintaining compatibility with IEEE 1149.1, and even in a system on chip where heterogeneous cores such as P1500 exist, the test can be performed simply by adding a wrapper interface port controller. have.

Furthermore, since it can be easily extended and used according to the number of system clocks even in a system on chip having multiple system clocks, there is an excellent effect that a test for delay failure can be easily performed even in a system on chip using multiple system clocks. .

Claims (8)

A connection line delay failure test controller for testing a connection delay error between cores in a system on chip including a plurality of cores by using an externally input system clock, a test clock, and a test mode selection signal. A tap controller configured to receive the test clock and a test mode selection signal and output a plurality of signals for inter-core connection line testing according to the IEEE 1149.1 standard; The state of the tap control unit may be determined by receiving the test clock and a test mode selection signal, and outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock when the connection delay delay test starts. In other cases, the first enable signal that outputs 0 and the enable signal that generates a second enable signal that outputs 1 from the time when the Update_DR state starts to the time when the Capture_DR state ends, and outputs 0 in the other cases. Generation unit; The system clock and the first enable signal are inputted, and 0 is output in an initial state, and then 1 is output at the first rising edge of the system clock after the first enable signal outputs 1, and the first enable signal is output. A first control signal generator configured to generate a Late_Update_DR signal that returns to an initial state when the enable signal is 0; Receives the system clock and the first enable signal, outputs 1 in an initial state, outputs 0 at the first rising edge of the system clock after the first enable signal outputs 1, and then the rising edge. A second control signal generator configured to generate an sck_DR signal outputting 1 in the first order; A first multiplexer for selectively outputting the Late_Update_DR signal when the second enable signal is 1 and an UpdateDR signal of the tap control unit when 0; And Including a second multiplexer for selectively outputting the sck_DR signal when the first enable signal is 1, and the ClockDR signal of the tap control unit when 0, When the connection delay delay test is executed, in the Capture_DR state of the tap controller, a rising edge of the Late_Update_DR signal in which an update occurs and a rising edge of the sck_DR signal in which a capture occurs occurs within one system clock. Delayed Failure Test Controller. The method of claim 1, The tap controller is connected to the delay delay test controller, characterized in that included in the core of the plurality of cores complying with IEEE 1149.1. The method of claim 1, And the enable signal generation unit receives a delay failure test determination signal for determining whether a connection delay error test is in progress. The method of claim 1, And a wrapper interface port controller configured to receive the test clock, the output signal of the tap control unit, and the output signals of the first and second multiplexers and convert them into signals for testing cores according to IEEE P1500. Fault test controller. The method of claim 4, wherein the wrapper interface port control unit, A ShiftWR signal combining the ShiftIR signal and the ShiftDR signal of the tap control unit through an OR gate; An UpdateWR signal combining the UpdateIR signal of the tap control unit and the output signal of the first multiplex through an OR gate; A WRSTN and SelectWIR signal outputting the reset signal and the select signal of the tap control unit, respectively; A CaptureWR signal having a value of 1 in a Capture_IR state and a Capture_DR state by combining a ClockIR, ShiftIR, ShiftDR signal, and an output signal of the second multiplexer, and 0 in the rest of the tap control unit; And And a WRCK signal multiplexing the test clock and the ClockDR signal when the tap control unit is in the Capture_DR state. The method of claim 5, wherein the CaptureWR signal, The rising edge is generated at the falling edge of the ShiftIR signal when the ClockIR signal of the tap control unit is 0, and the falling edge is generated after maintaining the value of '1' for one test clock, or the second multiplexer When the output signal is '0', the rising edge is generated at the falling edge of the ShiftDR signal and the falling edge is generated after maintaining the value of '1' during one test clock. . A connection line delay failure test controller for testing a connection delay failure between cores in a system on chip including a plurality of cores by using n system clocks, test clocks, and test mode selection signals input from an external device, A tap controller configured to receive the test clock and a test mode selection signal and output a plurality of signals for inter-core connection line testing according to the IEEE 1149.1 standard; The state of the tap control unit may be determined by receiving the test clock and a test mode selection signal, and outputs 1 from the time when the Capture_DR state is started to the falling edge of the test clock when the connection delay delay test starts. In other cases, the first enable signal that outputs 0 and the enable signal that generates a second enable signal that outputs 1 from the time when the Update_DR state starts to the time when the Capture_DR state ends, and outputs 0 in the other cases. Generation unit; The first enable signal and the n system clocks are input one by one, and a zero is output in an initial state, and then a one is output on a first rising edge of the received system clock after the first enable signal outputs one. And n first control signal generators generating Late_Update_DR signals according to respective system clocks, which return to an initial state when the first enable signal is 0; Receives the first enable signal and the n system clocks, respectively, and outputs 1 in an initial state, and then outputs 0 at the first rising edge of the received system clock after the first enable signal outputs 1; And n second control signal generators generating sck_DR signals according to respective system clocks that output 1 on the next rising edge; N first multiplexers for selectively outputting a Late_Update_DR signal according to each system clock when the second enable signal is 1 and an UpdateDR signal of the tap controller by 0; And If the first enable signal is 1, including the sck_DR signal according to each of the system clock, and if it is 0, n second multiplexers for selectively outputting the ClockDR signal of the tap control unit, When the connection delay failure test is executed, the rising edge of the Late_Update_DR signal according to each system clock in which an update occurs and the rising edge of sck_DR signal according to each system clock in which a capture occurs within the Capture_DR state of the tap controller. Connection delay test controller, characterized in that occurring within the system clock. A connector delay failure test controller according to any one of claims 1 to 8; And And a plurality of heterogeneous cores receiving a signal for a connection delay error from the connection delay error test controller.

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