KR20030010391A - Advanced tap linking module apparatus for testing system on chip comprising ip cores - Google Patents

Abstract

PURPOSE: A tap linking module(TLM) apparatus is provided to reduce design time by using IEEE 1149.1 as a standard for board testing without modification, and to perform an individual IP core test, connection checking between IP cores and chip testing. CONSTITUTION: A TLM is placed at a lower part of a system-on-chip on a board, and receives signals(TMS,TRST,TDO) to provide signals(SCE_EN,ENA,Reset) so as to dynamically control connections of respective TAPs. State condition expanders(SCE1,SCE2,SCE3,SCE4) are supplied with signals(SCE_EN,ENA) from the TLM. The state condition expanders(SCE1,SCE2,SCE3,SCE4) provide to respective TAP TMS signals for activating or inactivating respective TAPs(TAP1,TAP2,TAP3,TAP4) so as to have the same state transition as the TLM.

Description

ADVANCED TAP LINKING MODULE APPARATUS FOR TESTING SYSTEM ON CHIP COMPRISING IP CORES}

The present invention relates to an improved TAP linking module (TLM) device for system-on-chip (SoC) testing of IP cores, in particular IEEE 1149.1 standard boundary scan is implemented. An improved TLM device for SoC testing of IP cores that facilitates testing of system-on-chips (SoCs) that dynamically and dynamically connects existing IP cores.

In general, the P1500 has been proposed as a standard for testing system-on-chip (IP) cores, but it has not been confirmed as a standard. The TLM (TAP Linking Module) is an existing board test standard. Using IEEE 1149.1 provides an environment for testing SoCs composed of IP cores. To this end, several methods have been proposed to use the existing board test standard IEEE1149.1 to test SoC composed of IP cores.

1 is a schematic diagram of a SoC Test Access Architecture with Cascaded TDI and TDO in which all TAPs between a conventional TDI and a TDO are connected in series, and all TAPs are serially connected between the TDI and the TDO. In mode all TAPs are always active. However, it violates the IEEE 1149.1 standard because always the maximum scan path length and all the TAPs are activated from the chip level point of view.

FIG. 2 is a schematic diagram of a conventional SoC Test Access Architecture with Dedicated Select Pin, in which a TAP selection pin is added. This method adds select pins S0 and S1 for selecting a TAP. For on-chip (SoC) testing, select TAP1. For core testing, select one of TAP2-4. However, as the number of TAPs increases, the TAP select pin increases in proportion to the number of TAPs, which causes a problem in that a group of TAPs cannot be selected.

FIG. 3 is a schematic diagram of a SoC test board for considering a conventional process core, which is used when debugging a processor core having debug registers embedded in a method proposed by IBM. In other words, processor cores connected in series between the test access port using IEEE1149.1 on the system on chip (SoC) and the processor core are placed on the scan path in the test mode and placed on the processor core (P1-P3). This is how you can access debug registers.

However, there can be only one test data register between TDI and TDO, so there is a problem in that it is impossible to check the connection line between the IC Boundary Scan Register (ICBSR) and the processor core.

FIG. 4 is a schematic diagram of a SoC Test Access Architecture with TLM in which a conventional TLM is added. As a method proposed by Texas Instruments (TI), a TAP linking module can be used to dynamically connect all TAPs dynamically. That's the way.

By default, the chip (SoC) TAP, TAP1, is active, placing TAP1 on the TDI and TDO scan paths. Thus, at the chip level, the standard IEEE 1149.1 is fully satisfied. If you want to disable TAP1,4 for core testing and enable TAP2,3 on the TDI and TDO scan paths, insert the link_update command into the active TAP1. Then, the sel signal is applied from the TAP1 to the TLM so that the TLM changes the connection information, and the connection information is changed by the TDI and the TMS input. When the connection information is changed, a logic signal '1' is applied to the TAP (TAP2,3) to be activated from the TLM, and a logic '0' is applied to the TAP (TAP1,4) to be deactivated, so that the TAP2 and TAP4 are TDI and TDO. It is placed on the scan path to check core connection line. However, since the link_update command and the SEL and ENA signals need to be added to each standard TAP, there is a problem in that the design of the provided IP and the standard TAP is changed.

The present invention has been proposed to solve the problems of the prior art, and an object of the present invention is to implement the microcontrol unit (MCU), DSP IP core, etc. in a situation where standards for SoC testing with IP cores are not determined. Individual design changes can be made by reducing the design time by changing IEEE 1149.1, the standard for board testing, and dynamically connecting IP cores that implement IEEE 1149.1 standard boundary scan during SoC testing. And an improved TLM device for SoC testing consisting of IP cores that can efficiently check the interconnection between IP cores and chip on board (SoC) testing.

1 is a schematic diagram of a SoC test board in which all TAPs between a conventional TDI and a TDO are connected in series.

2 is a schematic diagram of a SoC test board in which a conventional TAP select pin is added.

Figure 3 is a SoC test board configuration in consideration of debugging a conventional process core.

4 is a configuration diagram of a SoC test board to which a conventional TLM is added.

5 is an overall configuration diagram of a TLM module for SoC testing according to the present invention.

6 is a timing diagram of selecting TLM to change connection information between taps according to the present invention, and starting to change the connection information.

7 is a timing diagram of selecting a TLM to change the connection information between the taps according to the present invention and ending the change of the connection information.

8 is a state transition diagram of standard TAPs on SoC by SCE and TLM.

<Description of Symbols for Main Parts of Drawings>

SoC: System on ChipTLM: TAP Linking Module

TAP1: IC (SoC) TAPTAP2-4: TAP of Core X, Y, Z

TDI: Test Data In TDO: Test Data Out

TCK: Test Clock TMS: Test Mode Sequence

TRST *: Test Reset ICBSR: IC Boundary Scan Register

NTC: Non TAP'ed CoreCBSR: Core Boundary Scan Register

In order to achieve the object of the present invention, the present invention is a board on the board consisting of IP cores that implement the IEEE 1149.1 standard boundary scan, which is a standard for board test implemented in a micro control unit (MCU), DSP IP core, etc. In a system having a chip (System On Chip (SoC)) test tap (TAP1) and core test taps (TAP2, TAP3, TAP4) having a core boundary scan register at the core of the tap: Located at the bottom of SoC), each tab is dynamically inputted with SEL_TLM, TDI (Test Data In), TCK (Test Clock), TMS (Test Mode Sequence), TRST * (Test Reset), and TDO (Test Data Out). A tap connection module (TLM) providing SCE_EN, ENA signals, Reset * signals to control all connections; And receiving a SCE_EN or ENA signal from the tap connection module (TLM) and forcing the TAP to be deactivated by gated on / off a TMS (Test Mode Sequence) signal inputted to each TAP. Since the TAP to be activated is input as it is, the TMS input to the tap connection module (TLM) is activated, or deactivates each tap (TAP1, TAP2, TAP3, TAP4) to have the same state transition as the tap connection module (TLM). Improved tap connection module (TLM) for system-on-chip (SoC) testing of IP cores, characterized by state condition extenders (SCE1, SCE2, SCE3, SCE4) providing TMS signals to each tap Provide a device.

Hereinafter, preferred embodiments of the present invention will be described in detail with reference to the accompanying drawings.

5 is an overall configuration diagram of a TLM (TAP Linking Module) module for a SoC (System On Chip) test composed of IP cores for testing a chip on a board according to the present invention.

Referring to FIG. 5, a state condition expander (SCE) module is a state condition extension used to enable or disable each tap. In other words, the SCE_EN and ENA signals from the TAP linking module (TLM) are received as inputs, and TMS (Test Mode Sequence) signals inputted to each TAP are gated on and off to force the TAP to be inactivated. Put it in Test / Idle state. The activated TAP has a state transition similar to that of the TLM since a TMS such as a TMS input to the tap connection module (TLM) is input.

The tap connection module (TLM) will be the main module of the present invention for maintaining or changing connection information between each TAP. It has an input of SEL_TLM that selects the tap connection module (TLM) to change TMS (Test Mode Sequence), TDI (Test Data In), TCK (Test Clock), TRST * (Test Reset) inputs and connection information. . Since there is a TLM controller inside the tap connection module (TLM) having the same state transition as the TAP controller in the IEEE1149.1 standard, the tap connection module (TLM) is a chip that is activated for a TMS (Test Mode Sequence) input. SoC) TAP or IP cores always have the same state transition. As the output signal of the tap connection module (TLM), SCE_EN is used to activate or deactivate the SCE module, and the ENA signal activates or deactivates each TAP by the connection information loaded in the tap connection module (TLM). Is the signal used for. The Reset * output signal from the tap connection module (TLM) was used without directly connecting the TRST * signal to TRST * of each TAP for reset. This is to provide a global reset function for all TAPs. In other words, the deactivated TAP is always in the Run-Test / Idle state regardless of the TMS (Test Mode Sequence) input. Therefore, the TAP applied to the system on chip (SoC) is repeatedly applied by '1' five times. You cannot put it in Logic-Reset state. Therefore, when the TLM controller of the tap connection module (TLM), which is always active, goes to the Test-Logic-Reset state by the TMS input, a Reset * signal is applied to TRST * of each TAP. In order to change the connection information between the taps, the timing of starting and ending the change of the connection information by selecting the TLM is performed in the Run-Test / Idle state as shown in FIGS. 6 and 7.

6 is a timing diagram for selecting a TLM to change connection information between taps according to the present invention, and FIG. 7 is a timing diagram for changing connection information between taps according to the present invention. Shows a timing diagram for finishing the change of the connection information.

The process of changing the connection of the TAPs is as follows. By default, the chip (SoC) TAP, TAP1, is enabled. If you want to deactivate TAP1 and TAP4 and activate TAP2 and TAP3, the tap connection module (TLM) applies a SEL_TLM signal to '1' when the tap connection module (TLM) is in the Run-Test / Idle state by the TMS input. The connection information is changed by the TDI (Test Data In) input by placing the connection module (TLM) on the TDI, TDO scan path as if it were a test data register. When the tap connection module (TLM) comes to Run-Test / Idle again after the change, the change of connection information is completed by granting SEL_TLM as '0' and Run-Test / Idle until TAP1 and TAP4 are activated again. In the state, TAP2 and TAP3 are activated to make the same state transition as the tap connection module (TLM). As a result, TAP2 and TAP3 are placed on the scan paths of TDI (Test Data In) and TDO (Test Data Out) so that connection lines between IP cores X and Y can be checked. 8 is a state transition diagram of standard TAPs on a SoC by SCE and TLM, and a state condition expander (SCE) and a standard TAP on a system on chip (SoC) by a tap linking module (TLM). It shows the state transition diagram of TAPs, which can be obtained without changing their design.

As described above, the improved TLM device for SoC testing composed of IP cores according to the present invention is a board test implemented in MCU, DSP IP core, etc. in a situation in which a standard for SoC testing with IP cores is not determined. Design time can be shortened by using IEEE 1149.1, the standard for standardization, and IP cores that implement IEEE 1149.1 standard boundary scan can be dynamically connected during SoC testing. It can effectively check core-to-core connection and chip on board (SoC) test.

Claims (2)

TAP1 for on-chip chip (System On Chip (SoC)) test with IP cores that implement IEEE 1149.1 standard boundary scan, a standard for board tests implemented in microcontrol unit (MCU), DSP IP core, etc. In a system with core test taps (TAP2, TAP3, TAP4) having a core boundary scan register at the core of the tab: Located at the bottom of the chip (SoC) on the board receives SEL_TLM, TDI (Test Data In), TCK (Test Clock), TMS (Test Mode Sequence), TRST * (Test Reset), TDO (Test Data Out) A tap connection module (TLM) providing SCE_EN, ENA signals, Reset * signals to dynamically control each connection of each tap; And Forcing the TAP to be deactivated by receiving SCE_EN and ENA signals from the tap connection module (TLM) and gated on / off the TMS (Test Mode Sequence) signal inputted to each TAP. In order to activate or deactivate the respective taps TAP1, TAP2, TAP3, and TAP4 to have the same state transition as the tap connection module TLM, since the TMS input to the tap connection module TLM is input as it is. Improved tap connection module (TLM) for system-on-chip (SoC) testing of IP cores characterized by being provided with state condition extenders (SCE1, SCE2, SCE3, SCE4) providing TMS signals to each tap Device. The method of claim 1, By default, when the chip (SoC) TAP TAP1 is enabled and you want to deactivate TAP1 and TAP4 and activate TAP2 and TAP3, the tap connection module (TLM) is run by a TMS (Test Mode Sequence) input. When placed in the Test / Idle state, the SEL_TLM signal is applied as '1' to place the tap connection module (TLM) on the TDI (Test Data In) and TDO (Test Data Out) scan paths as if they were a test data register. The connection information is changed by input, and when the tap connection module (TLM) comes to Run-Test / Idle again after the change is completed, the change of the connection information is finished by applying SEL_TLM to '0', and TAP1 and TAP4 are again changed. It is placed in Run-Test / Idle state until it is activated, and TAP2 and TAP3 are activated and have the same state transition as the tap connection module (TLM), so that TAP2 and TAP3 are placed on the scan path of TDI and TDO. I can check the connection line between Y An improved tap connection module (TLM) device for system-on-chip (SoC) testing of IP cores, characterized by the ability to dynamically make all possible connections to these IP cores at runtime.