JPH0763821A - Test circuit - Google Patents

Abstract

PURPOSE:To make it possible to reduce the number of test pins by using a part or more of boundary registers as P/S(parallel/serial) converters at the rime of scan tests, and performing the input and output of scan data through the converters. CONSTITUTION:Four registers 16 at the upper right among the boundary scan registers 16 are used as P/S converters 22, and the registers at the lower right can be used as S/P converters 24. The converters 22 shift the test data by one bit per clock pulse at the scan path test and outputs the serial data into an internal scan register 20 of a system logic circuit 12. Meanwhile, the converters 24 shift the output data, which are inputted in serial form from the registers 20, in accordance with the clock output the data in parallel. In this way, the input and the output of the scan data can be performed in parallel from the ordinary input/output pins. It is not necessary to provide scanning-type input/output pins additionally.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test circuit using both a scan method such as a scan path and a boundary scan method for facilitating test design.

[0002]

2. Description of the Related Art The testability design method is a method for designing a test systematically according to a certain rule so that a test is facilitated. As such a testability design method, there is a scan design such as a scan path, in which a storage element in the circuit is connected as a scan register by a shift register, and an arbitrary value is set inside from external input / output. It is a design method that allows you to observe and control the internal state. As a result, the circuit to be tested can be divided for each combinational circuit, so that the test becomes easy and the test input pattern can be automatically generated by using the test pattern generation algorithm for the combinational circuit.

Recently, not only automatic checking of design rules and automatic generation of test patterns, but also automatic conversion / insertion generation of test circuits for scan design, and
Automation including the conversion from an asynchronous circuit to a synchronous circuit is advancing, and CAD tools therefor are commercially available. Examples of this scan method include various methods such as a scan path design method, a random access scan design method, a level sensitive scan design method, an edge trigger scan design method, etc. depending on a clock supply to a register and a data access method. .

On the other hand, recently, as devices are highly integrated and large-scaled, high density mounting (surface mounting) of LSIs and the like is attempted by narrowing the pin pitch. As a result, board-level testing is becoming increasingly difficult, and it is expected that board-level testing will no longer be possible using conventional test methods. Against this background, JTAG (Joint Test Actio) is used as a board-level test method.
There is a boundary scan method standardized as an international standard of IEEE.

In this boundary scan method, a scan register circuit (boundary scan register) is inserted between the input / output pin of each LSI mounted on the board and the internal circuit, and further a control circuit and a dedicated pin are provided. This is a testability design method in which the boundary scan register of each LSI is connected on the board to enable access / control from the input / output of the board. By adopting this boundary scan method, the board level test can be performed by applying the input from the input / output of all the boards and observing the output. By using the boundary scan as a test method, it is possible to perform a connection test between LSIs on the board and a test inside the LSI without requiring contact of a probe for testing on the board.

A test that uses both a scan method such as a scan path and a boundary scan method in order to make it possible to perform a test of the state inside the circuit of such an LSI and a test on a board incorporating these LSIs. A circuit has been proposed. Such a test circuit is shown in FIG.

The test circuit 60 shown in FIG.
System logic (core logic) circuit 62, boundary scan logic circuit 64, and boundary scan register 66 provided for all input / output (I / O) pins of LSI 61 around these internal circuits. In addition to the normal input / output pins of the system logic circuit 62, the test circuit 60 has a scan data input terminal (SCAN I) as a scan test-dedicated pin for performing a scan test of a scan path system.
N), scan data output terminal (SCAN OUT),
A scan clock terminal (CLK), a scan enable terminal (SCAN EN), and a test access port (TA) for performing a boundary scan method test.
A test data input terminal (TDI), a test data output terminal (TDO), a test clock (TCK), a test mode selection (TMS), and the like are provided as test dedicated pins called P: Test Access Port) 68.
Further, the system logic circuit 62 has an internal scan register (internal scan register) 70, and the boundary scan logic circuit 64 has a TAP controller 72, an instruction register 74, an instruction decoder 76, and a multiplexer 78. is doing.

In the test circuit 60 shown in FIG. 5, the test methods of the scan path method and the boundary scan method are completely independent, and the tests are performed separately based on the respective methods. That is, during the boundary scan test, TDI, TDO, TC
The test is performed using the four TAP dedicated test pins of K and TMS, the boundary scan register and the boundary scan logic circuit 64 such as the TAP controller 72, the instruction register 74, the instruction decoder 76, and the multiplexer 78. , SCA
N IN, SCAN OUT, CLK, SCAN EN
The test is performed by using the dedicated test pin and the internal scan register 70.

[0009]

By the way, in the test circuit 60 shown in FIG. 5, both the boundary scan method and the scan path method can be performed. However, these test methods are performed independently independently. However, there is a problem in that the number of test pins increases because dedicated pins for testing are required for each method. On the other hand, in order not to increase the number of test pins, use a multiplexer etc. for test pins,
Although it is possible to use a normal input / output pin together, if a test pin and a normal input / output pin are used together, there arises a problem that a delay occurs and performance may be deteriorated.

An object of the present invention is to solve the above problems of the prior art and to describe by reducing the number of test pins even in a test circuit that uses both a scan method such as a scan path and a boundary scan method. An object is to provide a test circuit that can reduce the number of test patterns.

[0011]

In order to achieve the above object, the present invention is a test circuit that uses both the boundary scan method and the scan method, wherein at least a part of the boundary scan register is parallel / scanned during the scan test. It is to provide a test circuit characterized by being used as a serial converter and inputting / outputting scan data through this converter.

[0012]

The test circuit of the present invention is a circuit that uses both a scan method such as a scan path and a boundary scan method, and is used for a boundary scan method test in the scan method. Is used as a parallel / serial converter. By doing so, in the test circuit of the present invention, it is not necessary to provide test pins used for scan-in and scan-out in the scan method, and the number of test pins can be reduced. Further, in the test circuit of the present invention, since the data in / data out in the scan method can be executed in parallel, the number of test patterns to be described is reduced.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT A test circuit according to the present invention will be described in detail below based on a preferred embodiment shown in the accompanying drawings.

FIG. 1 is a conceptual diagram of an embodiment of the test circuit of the present invention. As shown in the figure, the test circuit 10 built in the LSI 11 includes a system logic circuit 12 that constitutes a logic circuit of the LSI 11, a boundary scan logic circuit 14, and all the normal input / output (I) of the system logic circuit 12. / O) pin, a test address port (T) connected to the boundary scan register 16 provided between the input / output pin and the system logic circuit 12 and the boundary scan logic circuit 14.
AP) 18 and.

The system logic circuit 12 has a combinational logic circuit (not shown) and an internal scan register 20. In the present invention, a part of the boundary scan register 16, that is, the four boundary scan registers 16 on the upper right side in the drawing are connected to the parallel / serial converter 22 for parallel data in-serial data out.
And the lower right four boundary scan registers 16 can be used as a serial / parallel converter 24 for serial data in-parallel data out.

In the figure, the output (TDO) of the boundary scan register 16 at the left end which constitutes the parallel / serial converter 22 is branched and input to the internal scan register 20 of the system logic circuit 12, and the output of the internal scan register 20. Is an input (T of the boundary scan register 16 at the left end of the serial / parallel converter 24).
DI). In addition, the internal scan register 20
A scan enable signal line for inputting a scan enable signal is connected to the corresponding I / O pin via the boundary scan register 16.

Here, the parallel / serial converter 22 functions as a test data input (SCAN IN) for inputting the test data in parallel (parallel data in) during the scan test of the scan path system, and outputs the test data according to the clock. The data is shifted bit by bit and serially output to the internal scan register 20 of the system logic circuit 12. On the other hand, the serial / parallel converter 24
Is the internal scan register 20 during the scan path test.
Test path output (SCAN OU) for shifting the scan path output data serially input from
Function as T).

Therefore, the boundary scan register 16
Are provided corresponding to the normal input / output pins of the system logic circuit 12, and simply pass the input / output signals input / output from the input / output pins during the normal operation, and the boundary scan logic circuit 1 during the boundary scan test.
It has a function of holding the test data input / output from the test data input / output by the control signal generated by 4 and inputting / outputting it to / from the system logic circuit 12. But,
The boundary scan register 16 which constitutes the parallel / serial converter 22 of the present invention, in addition to the above-mentioned two functions, scan path test data parallel input from a normal input pin functioning as SCAN IN at the time of a scan path test. The boundary scan register 16 which also has a function of outputting from the test data output for boundary scan, and which constitutes the serial / parallel converter 24 of the present invention, in addition to the above-mentioned two functions, also has a function of It also has a function of parallelly outputting the data input from the boundary scan test data input from the normal output pin functioning as SCAN OUT.

Such a boundary scan register 1
6 is shown in FIGS. 2 (a) and 2 (b). Figure 2
The register 16 shown in (a) has two multiplexers (MUX) 26, 27 and two flip-flop circuits (F / F) 28, 29. One input of the MUX 26 is an IN terminal for inputting a normal data signal or scan path test data from a normal I / O pin or output data from the system logic circuit 12, and the other input is for boundary scan. A TDI (Test Data Input) terminal for inputting test data is connected, and a shift / load (S / L) terminal is connected to its control terminal. The output of the MUX 26 is connected to the input terminal of the F / F 28, and the capture clock (CLKA Capture) is input to its clock terminal. The output of the F / F 28 is connected to the TDO (Test Data Output) terminal for outputting the boundary scan test data, and is also connected to the input of the F / F 29. The clock (CLKB Update) is input to the clock terminal of the F / F 29,
The output of the F / F 29 is input to one terminal of the MUX 27, the connection terminal is connected to the other terminal from the IN terminal, and the Mode terminal for inputting the mode switching signal is connected to the control terminal. The output of the MUX 27 is an output data signal to a normal I / O pin or the system logic circuit 12
Is connected to the OUT terminal for outputting an output signal to.

The boundary scan register 16 shown in FIG. 2A is operated by the Mode signal during the normal operation.
It has a function of controlling the UX 27 and directly outputting the normal data input from the IN terminal from the OUT terminal. Also, the register 16 holds the boundary scan test data input from the TDI terminal, which is selected as an input of the MUX 26 by the control of the S / L signal during the boundary scan test, in the F / F 28 according to the clock input from CLKA. And has a function of outputting from the TDO terminal. Further, the register 16 is selected by the MUX 26 on the input side during the scan path test.
The scan path test data input from the N terminal is F /
A function of holding in the F28 and serially outputting from the TDO terminal, or holding the scan path test data input from the TDI terminal selected by the MUX 26 on the output side in the F / F28 and F / F29, and using the clock C
It has a function of shifting according to LKA and CLKB and outputting in parallel from the OUT terminal by the MUX 27.

The boundary scan register 17 shown in FIG. 2B is the same as the boundary scan register 16 shown in FIG.
27 is connected to one input terminal of MUX 27, the inverted output of MUX 27 is connected to the OUT terminal and is also connected to one input terminal of MUX 26, and the inverted output (Q bar) of F / F 29 is to the other input terminal of MUX 27. It is exactly the same except that it is connected, and detailed description thereof will be omitted. Here, for example, the boundary scan register 16 may be used for both input and output, but, for example, the boundary scan register 17 may be used for input and the boundary scan register 16 may be used for output, or the boundary scan register 17 may be used. Of course, may be used for input / output.

In the test circuit 10 of the present invention, such boundary scan registers 16 and / or 17 are used to make connections for input and output so as to be mutually adjacent, and for input side and output side during the scan test. Both can be used as parallel / serial converters (including serial / parallel converters) 22 and 24 in the same number (four in the illustrated example). Therefore, in the test circuit 10 of the present invention, during the scan path test, scan test data input (scan in) and scan test data output (scan out) can be performed in parallel from normal input / output pins. Therefore, in the present invention, it is not necessary to provide scan type input / output test pins (scan in and scan out), and the number of test patterns to be described can be reduced.

That is, in the conventional scan path, in scan-in, four patterns of scan test data, for example, 1010 are input bit by bit to the system logic circuit 12 (internal scan register 20) from one test pin. go. On the other hand, in the present invention, the parallel / serial converter 22 shown in FIG.
To the four boundary scan registers 16 that make up
For example, one test data pattern of 1010 is input in parallel, and after that, four clocks are shifted and these test data are sequentially loaded into the internal scan register 20. Therefore, in the present invention, only one pattern is described as the test pattern, and thereafter, only four patterns are shifted by the clock, that is, one of the four patterns.
Internal scan register 2 for bit scan test data
Since the scan test can be performed by loading 0 into the 0, the number of patterns to be scan-tested in the system logic circuit 12 does not change, but the number of test patterns to be described can be reduced from 4 patterns to 1 pattern conventionally. Therefore, in the present invention, the test design becomes easier and the development load is reduced as compared with the conventional case.

In particular, a large-scale logic circuit, for example, the number of flip-flops (F / F) of the internal scan register is three.
In the case of about 00 stages, in the conventional one, a test pattern of only 300 clocks (300 shift registers) is prepared to load the test data into the internal scan register 20, and a pattern of 300 cycles is described and serialized. On the other hand, in the present invention, by using ten boundary scan registers 16 as the parallel / serial converter 22, 30 patterns are simply described, and then a test clock is written in one pattern. Since it can be shifted and loaded into the internal scan register 20, the efficiency of test pattern creation work is improved and the test design is significantly reduced. The input side (parallel / serial converter 22) and the output side (serial / serial converter)
Boundary scan register 1 of parallel converter 24)
By setting the number of 6 to the same number, data in and data out can be performed in parallel in accordance with the test clock, so automatic pattern generation (ATPG: Automatically T
est Patern Program Generator) is easy to apply.

Next, the boundary scan logic circuit 1
4 is shown in FIG. The circuit 14 shown in the figure includes a test access port (TAP) 18 for inputting / outputting data to / from the boundary scan and controlling the data.
, TAP controller 34, instruction register 36,
Instruction decoder 38, bypass register 40, MUX
42 and 43 and transfer gate (EN) 44
Have and. Here, the boundary scan is the above-mentioned T
AP32, TAP controller 34, instruction register 36
In addition to the instruction decoder 38 and the bypass register 40, the boundary scan register 16 as a register,
Although not shown, the device identification register is provided to set the serial number of the component and the like so that it can be identified on the board, and other internal registers (including the internal scan register 20) for use in the system. .

TAP is a test data input port (TDI: Test) for inputting boundary scan test data.
Data In), a test data output port (TDO: Test Data Out) that outputs boundary scan test data
), A test clock port (TCK: Test Cl) for the TAP controller 34 during the boundary scan test.
ock) and a test mode select port (T) for controlling the selection of test mode / normal operation mode.
It consists of four essential signal ports of MS: Test Mode Select) and one optional port of Test Reset (TRST: Test Reset) for resetting the TAP controller 34. The TAP controller 34 is
The instruction register 3 receives the MS signal and the TCK signal.
6, instruction decoder 38, bypass register 40, MUX
A clock signal and a control signal such as 43 and EN44 are controlled to control the boundary scan. The instruction register 36 and the instruction decoder 38 read an instruction from the TAP controller 34, select at the time of test, and access the data register (the boundary scan register 16, the bypass register 40, etc.). The bypass register 40 is a 1-bit register and is used as a bypass path.

The instruction register 36 has at least 2
A bit is required, the bypass register 40 is selected, and the internal logic circuit for normal operation is tested.
(ORMAL) and a sample mode (SAMPLE) in which the boundary scan register 16 is selected for the sample test and the input / output signals are fetched at a specific timing while the chip (LSI 11) is normally operated.
Boundary scan register 1 for external test
Three instructions for selecting 6 and an EXTEST mode for testing the wiring between chips are read. In addition, intest mode (INTEST), ID code (ID
It is also possible to provide instructions such as CODE) and user code (USERCODE).

The test circuit 10 of the present invention, which uses both the scan method and the boundary scan method in the LSI 11, is basically constructed as described above. One embodiment in which these test circuits 10 are arranged on a board Is shown in FIG. The test circuit 50 shown in FIG. 4 includes four LSIs 11a,
11b, 11c, and 11d are arranged on the board 51. In the boundary scan, the TDO in the front stage is connected to the TDI in the rear stage, and the TDI from the board 51 to the board 5 is connected.
Construct one path from 1 to TDO. On the other hand, the scan path in the test circuit 50 is also the parallel SCA of the preceding stage.
N OUT is connected to the parallel SCAN IN in the subsequent stage, and each constitutes one path in parallel. In this way, the boundary scan method and the scan method test can be performed on the board 51.

The test circuit according to the present invention is basically constructed as described above, but the present invention is not limited to this, and various improvements and design changes are made without departing from the gist of the present invention. Of course, it is possible.

[0030]

As described above in detail, according to the present invention, the input / output of the scan test data (scan-in and scan-out) is performed when the scan method such as the scan path is tested. Pin to parallel /
Since it is possible to perform parallel processing on a plurality of boundary scan registers provided so as to configure a serial converter, it is necessary to provide a test pin for scan data input / output (scan in, scan out) which has conventionally been required. No more, the number of test pins can be reduced, and circuit design can be facilitated.

Further, according to the present invention, during the scan test of the scan path or the like, the loading and unloading of the scan test data to the internal scan register is performed serially, whereas the scan test data is converted from parallel / serial. Since it is possible to input and output in parallel to a plurality of boundary scan registers that configure the device, it is possible to obtain the effect of reducing the number of test patterns to be described, and as a result, the test design becomes easy and the development load can be reduced. Therefore, in the present invention, although the test circuit uses both the scan method and the boundary scan method, it is possible to perform the scan test pattern by automatic pattern generation (ATPG).

[Brief description of drawings]

FIG. 1 is a conceptual configuration diagram of an embodiment of a semiconductor integrated circuit (LSI) having a test circuit according to the present invention.

FIGS. 2A and 2B are block diagrams showing a configuration of a boundary scan register used in the test circuit of the present invention.

3 is a block diagram showing a configuration of an embodiment of a boundary scan logic circuit of the test circuit shown in FIG.

FIG. 4 is a conceptual diagram showing an example of a configuration on a board of a test circuit according to the present invention.

FIG. 5 is a conceptual configuration diagram of a conventional test circuit.

[Explanation of symbols]

10, 50 Test circuit 11, 11a, 11b, 11c, 11d LSI (semiconductor integrated circuit) 12 System logic circuit 14 Boundary scan logic circuit 16, 17 Boundary scan register 18 Test access port (TAP) 20 Internal scan register 22, 24 Parallel / Serial converter (serial / parallel converter) 26, 27, 42, 43 multiplexer (MUX) 28, 29 flip-flop (F / F) 30 inverter 34 TAP controller 36 instruction register 38 instruction decoder 40 bypass register 51 board (semiconductor substrate)

Claims (1)

[Claims] 1. A test circuit using both the boundary scan method and the scan method, wherein at least a part of the boundary scan register is used as a parallel / serial converter during a scan test, and input / output of scan data is performed through this converter. A test circuit characterized by being performed.