JP3043871B2 - Semiconductor integrated circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a design for facilitating test of a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit which realizes a high-speed scan test while keeping consistency with a scan design.

[0002]

2. Description of the Related Art In recent years, as the density of semiconductor integrated circuits has increased, techniques for facilitating circuit tests have become increasingly important. In order to perform a failure test of a sequential circuit as a failure test of a combinational circuit, an easy-to-test design method (referred to as scan path design or simply scan design) that extends to a sequential circuit having a scan path is widely used. Recently, as a method for easily testing a mounting substrate of a semiconductor integrated circuit and the semiconductor integrated circuit itself, there is a test method generally called a boundary scan. However, regarding this method, an international standardization proposal (IEEE 114) has been proposed.
9.1) has been proposed by an organization called JTAG (the Joint Test Action Group).

As shown in FIG. 6, in a board adopting the boundary scan, a test circuit is previously built in the input / output cells of the chip, and when these chips are connected in series at the time of testing, the test data is reduced. (Scan path) is configured, and the chip can be accessed from the edge connector (scan in, scan out). For this reason, a test of an individual LSI on a board can be performed by a shift operation, a test of wiring on a board can be performed by a shift operation, and a multi-terminal fixed card is unnecessary in a wafer test of LSI manufacture. With benefits.

[0004] The basic structure of the test circuit of the standardization proposal proposed by JTAG has a configuration as shown in FIG. This test circuit has a structure similar to a simple CPU, and the test function changes according to an instruction to be loaded into the instruction register IR. The test registers included in the present invention are roughly classified into two types: an instruction register IR and a data register DR. The data register D
R is a generic name of a plurality of test data registers including a boundary scan register as shown in FIG. The entire control of the test circuit is performed by an instruction register IR and a TAP (Test Access Port) controller TAPC. The TAP controller TAPC is a controller having a total of 16 states, and is basically controlled by a test mode setting input value called TMS and a test clock TCK. That is, the test function of the entire test circuit is determined by the instruction in the instruction register IR and the state of the TAP controller TAPC.

FIG. 8 shows a state transition diagram of the TAP controller TAPC. The details of each state are omitted, but only important parts will be described briefly below.

First, the TEST-LOGIC-RESET state is the base state of the TAP controller TAPC. In this state, the test logic does not participate in the operation of the entire circuit and normal operation is performed.

The TAP controller TAPC executes the following RUN
Via the -TEST / IDLE state, a state can be entered in which either one of the two register groups, the instruction register IR or the data register DR, is operated. Instruction register IR
And T corresponding to each operation of the data register DR.
The state transition of the AP controller TAPC basically has the same specification.

[0008] SELECT-IR-SCAN or SELECT-DR-SCAN
The state initializes the scan sequence of the instruction register IR or the data register DR, respectively.

Next, the CAPTURE-IR and CAPTURE-DR states are modes for loading data. In the CAPTURE-DR state, some data is loaded into the data register DR currently selected by the instruction register IR. You.
In the case of the CAPTURE-IR state, a fixed pattern is taken into the shift register in the instruction register IR. The lower two bits of the instruction register cell are fixed to "01".

The SHIFT-IR or SHIFT-DR state is a state in which data in the instruction register IR or the data register DR can be shifted, respectively. That is, in the SHIFT-DR state, the data register DR is connected to the test common input terminal T.
It is connected between DI and the test-dedicated common output terminal TDO, and shifts data one by one toward the test-dedicated common output TDO each time the test clock TCK rises. Also SHI
In the case of the FT-IR state, the shift register in the instruction register IR is connected between the test-dedicated common input terminal TDI and the test-dedicated common output terminal TDO, and the data is transferred to the test-dedicated common output TDO every time the test clock TCK rises. Shift to

EXIT-1-IR, EXIT-2-IR, EXIT-1-DR, and
In the EXIT-2-DR state, the scan ends.

In the PAUSE-IR or PAUSE-DR state, the shift operation of the instruction register IR or the data register DR in the serial path between the test dedicated common input terminal TDI and the test dedicated common output terminal TDO is suspended. Used to load a new pattern from the external storage device to the memory in the test mechanism.

[0013] The UPDATE-IR or UPDATE-DR state indicates the status of the instruction register IR or data register D, respectively.
In this mode, R is updated. Several types of registers, such as the instruction register IR, do not exhibit their effect when data is shifted, and UPDATE-IR or UPDATE-DR
It works in mode only.

Next, the data register DR will be described.

The boundary scan register BSR is a shift register for realizing a serial shift function corresponding to an external terminal, which is a basic concept of the boundary scan test, and includes types (input, output, Although a circuit having a different circuit structure is prepared depending on the tristate or bidirectional), the circuit as a whole has 1
It is formed as a serial shift register of a book.

The bypass register BR is a register provided for bypassing another data register DR for testing a circuit, and is a 1-bit register in terms of a circuit. This bypass register BR reduces the number of shift clocks by setting the LSIs other than the test target in bypass mode, assuming that a plurality of JTAG-specific LSIs are further connected by a serial chain on the mounting board. It is an object.

The device identification register DIR is an option, but has a function of holding the identification number of the LSI, and is used for the test equipment to automatically determine the type of the LSI.

Also, the unique test data register DSTD
R is an optional register added for various purposes for testing purposes, and an internal scan register, for example, can be assigned to this part.

Next, the test-only terminal will be described.

The test-only common input terminal TDI functions as a serial input terminal common to the instruction register IR and the data register DR. Test-only common output terminal TDO
Functions as a serial output terminal common to the instruction register IR and the data register DR. The TAP controller control input terminal TMS is connected to the TAP controller TAPC.
The state transition of the TAP controller TAPC is determined by the signal value and the test clock TCK. The test-only common clock terminal TCK is used as a synchronization signal common to all of the data register DR, the instruction register IR, and the TAP controller TAPC. The test reset signal terminal TRST is used for initializing a test structure, but is treated as an option.

In the JTAG specification, the following seven types of common instructions are prepared.

The BYPASS instruction selects only the bypass register BR to connect the test dedicated common input terminal TDI and the test dedicated common output terminal TDO. The EXTEST instruction “disconnects the circuit from the external chip or LSI to be tested”. The IDCODE instruction uses the device identification register D
Select IR. The INTEST instruction sends test data to the system logic inside the part and obtains the result. The RUNBIST instruction executes a BIST (self test) of the component. SAM
The PLE instruction fetches input / output signals without affecting the circuit operation while operating the system logic normally. The USERCODE instruction loads or shifts an identification code rewritable by the user into the device identification register on a trial basis.

According to the JTAG specifications, the boundary scan register BSR shows an example of a circuit configuration for each of the input, output, tristate, and input / output terminals. FIGS. 9 and 1 show three types of circuit configuration diagrams for input, output and enable control designed based on these.
0 (a) and (b). These three types of boundary scan cells BSC (actually, boundary scan register B)
Since the SR is treated as one cell, this term will be used hereinafter). Here, each cell BSC includes two storage elements, the scan flip-flop SFF and the update flip-flop UFF, in order to prevent an external influence upon data shift. In other words, it is considered that data is transferred for the first time from the storage element in the shift stage to the storage element performing the final function in the UPDATE state.

In the boundary scan test based on the JTAG specification, one boundary scan cell BSC exists for each input / output terminal on the LSI. Therefore, the boundary scan cell BSC can be used as a virtual input / output terminal, and can be logically independent from the outside of the LSI during the test mode.

In the normal system mode, the boundary scan cell BSC is placed in the pass mode. In this passing mode, data is transferred from the input terminal IN to the internal logic (terminal OUT) of the LSI via the update selector UMUX.
It is a mode that can be passed without interruption. However, when the LSI is in the INTEST mode (internal test mode), the test data is shifted through a boundary scan chain formed by continuously connecting boundary scan cells BSC in the LSI, and the test data is transferred from the previous cell. Is supplied from the test common input terminal TDI and the boundary scan cell BS
C, and is passed to the next boundary scan cell via the test-only common output terminal TDO. Therefore, J
In the UPDATE-DR mode (update mode) of the TAG specification, the test data is supplied to the scan flip-flop SF by a signal UDDR (which is a control signal from the TAP controller TAPC and indicates the UPDATE-DR state).
F to the update flip-flop UFF. In the INTEST mode, the selection signal IMC of the update selector UMUX causes the update selector UMUX to select not the data from the input terminal IN but the output of the update flip-flop UFF. As a result, the test data can be passed to the LSI.

Next, a problem will be pointed out when testing an LSI of a scan design having an internal scan cell by such a boundary scan of the JTAG specification.

When testing an LSI using boundary scan, without changing the test vector to be applied,
The control signal needs to be changed during the test.
For example, an internal flip-flop requires a rising edge as its clock input to set a value. In this case, the data supplied to the D input of the flip-flop must be constant before and after the rising edge of the clock. Therefore, if test values for this circuit are continuously input through the boundary scan chain, two independent test vectors are required.

The first test vector is obtained from the boundary scan cell corresponding to the input terminal of the system clock.
While supplying the L "level (0 value), supply the appropriate data value from the appropriate boundary scan cell.
Again provides the exact same data value at the data input, but at the rising edge of the clock, providing an "H" level (one value) at the system clock input. Using this technique, LSI
It can be effectively tested by the TAP controller TAPC.

As described above, the TAP controller TAPC of the JTAG specification and its four terminals (TMS, TCK,
It is possible to test the LSI using only DI and TDO). However, this method is a very time-consuming method because it doubles the number of test patterns required to test the LSI. In addition, if a rising edge of the system clock is required, it has the same value for one entire test cycle (ie, 0 for the first cycle and 1 for the second cycle), Fine control cannot be performed during one test cycle.

As a specific example for explanation, an LS having internal scan chains ISC1 to ISC4 on the output side of a 4-bit adder ADDER as shown in FIG.
Consider I.

The LSI of this example is a TAP controller TA
It comprises a PC, an instruction register IR, an instruction decoder DEC, boundary scan cells BSC1 to BSC20, and internal scan cells ISC1 to ISC4.

Of the boundary scan cells BSC1 to BSC20, BSC1 to BSC7 are connected to input terminals and BSC8 to BSC8.
C12 is an output terminal, BSC13 and BSC14 to BS
Each pair of C19 and BSC20 corresponds to an input / output terminal. That is, BSC1 to BSC7, BSC1
4, BSC16, BSC18, and BSC20 are input boundary scan cells (see FIG. 9).
~ BSC13, BSC15, BSC17, and BSC1
Reference numeral 9 denotes an output boundary scan cell (see FIG. 10A).

When performing a boundary scan test in accordance with the boundary scan standard of the JTAG proposal,
Access to each element constituting the circuit is performed under the control of the TAP controller TAPC. In addition, all test data is continuously input / output to / from each circuit element through the TDI and TDI terminals. Further, the scan mode setting and control signals are generated by the TAP controller TAPC and the instruction register IR.

The internal scan cells ISC1 to ISC4 are simple flip-flops and have a system clock SYS.
4-bit adder ADDER at rising edge of CLK
Must be latched in this flip-flop. However, the test mode (INTE
During the (ST instruction), the test vector is shifted through the boundary scan chain formed by connecting the boundary scan cells BSC1 to BSC20 in series, so that a rising edge cannot be generated. That is, since the flip-flop is of a dynamic type, the system clock SYSCL is used during the scan shift mode.
K is required to be at the “H” level.

In the conventional boundary scan test method, the above-described method is employed to address this problem. That is, for one test pattern, the bit corresponding to the boundary scan cell (BSC7 in FIG. 11) connected to the system clock SYSCLK is initially set to the 0 value so as to be at the “L” level, and then the same bit is set to the “L” level. By preparing two patterns with one value and other bits being the same, repeating the input of the test data twice,
It is a method to realize.

Hereinafter, this method will be described with reference to the flowcharts of FIGS.

First, in step S101, TEST-LOGIC-RE
Enter the SET state. This resets the test logic and automatically generates an INCODE instruction to be entered into the instruction register IR. Next, in step S102, RUN-TEST / IDLE
The state enters the SELECT-DR-SCAN state in step S103.

Next, an INTEST instruction is input in step S104, which is executed by a subroutine shown in FIG. That is, in step SI1, SELSCT-IR-SCAN
The system enters the state, enters the CAPTURE-IR state in step SI2, and enters the SHIFT-IR state in step SI3. here,
The instruction code of INTEST is actually input. For example, if the instruction length is 4 bits, it takes four cycles to shift in the instruction. Further, in step SI4, EXI
Enter the T-1-IR state and enter the UPDATE-IR state in step SI5. Here, the parallel output of the instruction register IR is input to the instruction decoder DEC, and test logic suitable for the required operation is generated. In other words, when an instruction for INTEST is input, the device enters INTEST mode after UPDARE-IR.

Next, in step S105, test data in which the bit corresponding to the boundary scan cell BSC7 for the system clock SYSCLK is "0" is input. This is executed by a subroutine shown in FIG. That is, in step SD1, the state enters the SELECT-DR state,
Enter the CAPTURE-DR state in step SD2, and
Enter the SHIFT-DR state at D3. Here, test data is actually input. In this example, since the boundary scan cells of BSC1 to BSC20 are provided, the data length is 20 bits, and the seventh bit from the bottom is “0”. Further, the state enters the EXIT-1-DR state at step SD4, and enters the UPDATE-DR state at step SD5. Here, the parallel outputs of the boundary scan cells BSC1 to BSC20 are supplied to the internal circuits as if they came directly from the respective input terminals.

Next, at step S106, the bit corresponding to the boundary scan cell BSC7 for the system clock SYSCLK is "1", and the other bits are set at step S1.
Test data that is the same as the test data 05 is input. The processing is performed in the same manner as in step S105 in FIG.
Is executed in the subroutine. At this time, the system clock SYSCLK becomes a rising edge, and a new value is latched in the internal scan cells ISC1 to ISC4.

Next, at step S107, if there is the next test data, the process returns to step S105 to repeat the above-mentioned processing, and if not, the process ends. It should be noted that the result of the internal test by the above processing is determined in step S
In the state of CAPTURE-DR which is step SD2 in 105,
Boundary scan cells BSC8 to BSC13 for output,
It is held in BSC15, BSC17, and BSC19. Then, in the SHIFT-DR state in step SD3, the next new test data is shifted in, and at the same time, these results are shifted out from the terminal TDO.

In this example, a 4-bit adder is taken as an example for the sake of simplicity. However, an LSI which actually performs a boundary scan design generally becomes a very large circuit. The data length of the data is several hundred bits or more. Therefore, the method of repeating the test data for the same purpose twice as in the present method increases the test time.

In order to generate test data, the designer must take care that a series of boundary scan chains ends at the correct position, and that any control data is set at the correct position in the boundary scan chain as necessary. Must. That is, the work of setting a predetermined bit to "0" at first and then to "1" as in the present method is a constraint for a test designer and causes a mistake.

[0044]

As described above, in the conventional semiconductor integrated circuit by the boundary scan design of the JTAG specification, when it is desired to control an internal combinational logic circuit from an arbitrary control signal terminal during a test, for example, For example, when testing a semiconductor integrated circuit having a scan, two test patterns are prepared corresponding to the H / L level of the system clock in order to access the flip-flop of the internal scan cell.
The test takes time, and the system clock is H / L during the test cycle based on each test data.
There is a drawback in that fine control cannot be performed because it becomes constant at any one of them.

The present invention solves the above problems,
The purpose is to control the internal combinational logic circuit from an arbitrary control signal terminal at the time of a test, thereby enabling control by a control signal during a test cycle, and performing a test with a smaller number of test patterns to achieve a higher speed. An object of the present invention is to provide a semiconductor integrated circuit capable of performing a test.

[0046]

In order to solve the above-mentioned problems, a first feature of the present invention is that, as shown in FIG. 1, an internal combinational logic circuit 1 and a test circuit 3 for performing a boundary scan test. The test circuit 3 includes a TAP controller TAPC for controlling the test circuit 1.
An instruction register IR for inputting and holding a test instruction from a test dedicated input terminal TDI;
And an instruction decoder DEC that decodes the instruction word and outputs a control signal group. The instruction decoder DEC is individually connected to each of the input / output terminals of the combinational logic circuit 1. A boundary scan chain in which boundary scan cells BSC1 to BSCm and BSSCK functioning as data paths of the logic circuit 1 are connected in series, and the boundary scan cells BSC1 to BSCm and BSS are connected.
Among the CKs, a boundary scan cell BS connected to a control signal terminal SYSCLK for controlling the semiconductor integrated circuit.
SCK is used for executing a predetermined instruction even during a test.
It functions as a control signal supply path to the combinational logic circuit 1.

A second feature of the present invention is that, as shown in FIG. 2, for example, n (in FIG. 2, n = 2) combinational logic circuits A and B and a test circuit 13 for performing a boundary scan test are provided. And the test circuit 13 comprises:
TAP controller TAP for controlling the test circuit 13
C, an instruction register IR for inputting and holding a test instruction from a test-only input terminal TDI;
An instruction decoder DEC that decodes an R instruction word and outputs a control signal group is individually connected to an arbitrary input / output terminal of the combinational logic circuits A and B, and is used as a scan path during a test. Sometimes, internal scan chains ISC1 to ISC4 functioning as data paths of the combinational logic circuits A and B are connected in series with an internal scan chain, and predetermined input / output terminals of the combinational logic circuits A and B and the internal scan circuit. Cancel ISC
1 to ISC4, which are individually connected to correspond to predetermined output terminals, and function as a boundary scan path during a test and as a data path of the combinational logic circuits A and B during a normal operation.
1 to BCS8 and a BSSCK connected in series, and a boundary scan chain connected to a control signal terminal SYSCLK for controlling the semiconductor integrated circuit among the boundary scan cells BCS1 to BCS8 and the BSSCK. Is to function as a control signal supply path to the combinational logic circuits A and B at the time of executing a predetermined instruction even during a test.

According to a third feature of the present invention, in the semiconductor integrated circuit according to claim 1 or 2, as shown in FIG. 3, a boundary scan cell BSSCK connected to the control signal terminal SYSCLK receives test data input. An input multiplexer INMUX for selecting and outputting the control data input to the combinational logic circuit 1 or A and B at other times, and holding the output of the input multiplexer INMUX and outputting the test data TDI to the test dedicated output terminal TDO. Scan flip-flop S
FF, an update flip-flop UFF that holds the output of the scan flip-flop SFF when the test data is updated, and an output of the update flip-flop UFF during a test other than when the predetermined instruction is executed. An update multiplexer UMUX for selecting and outputting the control signal input IN to the combinational logic circuit 1 or A and B at the time of execution or other than the test.

[0049]

In the semiconductor integrated circuit according to the first and third aspects of the present invention, first, as shown in FIGS. 1 and 3, a test instruction (INTEST instruction) is shifted into an instruction register IR from a test dedicated input terminal TDI. Next, the test-only input terminal T
The test data is shifted from DI into a boundary scan chain in which the boundary scan cells BSC1 to BSCm and BSSCK are connected in series. Then, a predetermined command (ISCAN command; internal scan command) is shifted into the command register IR from the test dedicated input terminal TDI,
As a result, the signal ISC0 indicating the internal scan mode becomes "0", the control signal input IN is selected by the update multiplexer UMUX, and is supplied to the combinational logic circuit 1.

That is, even during the test, the boundary scan cell BSSCK can supply the control signal from the control signal terminal IN to the internal combinational logic circuit 1, and perform the test while controlling the combinational logic circuit 1. Since the test can be performed and one test cycle can be executed for one test data, as a result, control by a control signal can be performed and a high-speed test can be realized.

In the semiconductor integrated circuit according to the second and third aspects of the present invention, as shown in FIGS. 2 and 3, it is assumed that the control of the internal combinational logic circuit is performed from an arbitrary control signal terminal during a test. , For example, the internal scan cells ISC1 to ISC4 between the combinational logic circuits A and B.
And the boundary scan cell BSSCK connected to the system clock SYSCLK is configured as shown in FIG.

In this case, first, the test dedicated input terminal TD
Test instruction (INTEST instruction) from I to instruction register IR
, And then the boundary scan cells BSC1 to BSC8 and BSS from the test dedicated input terminal TDI.
The first test data is shifted into a boundary scan chain in which CKs are connected in series. Then, a predetermined command (ISCAN command; internal scan command) is shifted into the command register IR from the test-dedicated input terminal TDI. As a result, in the boundary scan cell BSSCK, the signal ISC0 indicating the internal scan mode is set to "
0 ", and the control signal input IN (that is, the system clock SYSCL) is input to the update multiplexer UMUX.
K) is selected and internal scan cells ISC1 to ISC
4 can be supplied with a negative pulse. At this time, internal scan cells ISC1 to ISC4 have boundary scan cells BS.
The output result of the combinational logic circuit A which receives the test data shifted into C1 to BSC4 is held.
Further, the next second test data is transferred to the test dedicated input terminal T.
DI shifts into the boundary scan chain. Further, an INTEST instruction is input again, the process returns to the first test data input process, and the next third test data is shifted into the boundary scan chain, and so on.

That is, even in the test, the boundary scan cell BSSCK can supply the control signal from the control signal terminal IN (the system clock SYSCLK in FIG. 2) to the internal scan cells ISC1 to ISC4, Even in a semiconductor integrated circuit having a configuration in which an internal scan cell is provided between combinational logic circuits, a test can be continuously and efficiently performed.

Also, when the internal combinational logic circuit is controlled from an arbitrary control signal terminal, the test can be performed while controlling the combinational logic circuits A and / or B.

[0055]

Embodiments of the present invention will be described below with reference to the drawings.

As a first embodiment of the present invention, the present invention is applied to the example used in the description of the prior art. In the test circuit having the internal scan chains ISC1 to ISC4 and the LSI of the 4-bit adder ADDER shown in FIG. 11, the boundary scan cell BSC7 connected to the system clock SYSCLK is realized by the boundary scan cell BSSCK having the configuration shown in FIG. . The other components are exactly the same as those of the conventional example, and the description thereof is omitted.

The configuration of the boundary scan cell shown in FIG. 3 includes an input multiplexer INMUX, a scan flip-flop SFF, and an update flip-flop UF.
F and an update multiplexer UMUX.

The input multiplexer INMUX supplies the test data TDI at the time of inputting test data, and the control signal input IN (in FIG. 11, the internal scan cells ISC1 to ISC4 in FIG. 11) to the internal combinational logic circuit (in this embodiment, the internal scan cells ISC1 to ISC4). System clock SYSCLK)
Is selected and output by the signal SFDR. Selection signal S
FDR is a signal indicating whether the state is the SHIFT-DR state, and is supplied from the TAP controller TAPC.

The scan flip-flop SFF holds the output of the input multiplexer INMUX and outputs it to the test dedicated output terminal TDO. The clock signal CKDR is a signal generated by the TAP controller TAPC from the test clock TCK. The scan flip-flop S
The FF is a storage element of the boundary scan chain.

The update flip-flop UFF is
When the test data is updated (UPDATE-DR state), the output of the scan flip-flop SFF is held. In other words, SHIFT-
The data at the time when the data is shifted in through the boundary scan chain in the DR state is held in the UPDATE-DR state and supplied to the internal combinational logic circuit. The clock signal UDDR is a signal generated by the TAP controller TAPC.

The update multiplexer UMUX receives the output of the update flip-flop UFF during a test other than when the internal scan instruction (ISCAN instruction) is executed, and inputs the control signal input IN during the test and when the internal scan instruction is executed or other than the test. A signal obtained by calculating the logical product of the signal IMC and the signal ISC0 is selected and output. The internal scan instruction (ISCAN instruction) is a newly added instruction and
Not in the AG specification. The mode setting signal IMC is a signal for setting the operation mode of the boundary scan cell, is determined by the type of instruction, and is generated by the instruction decoder DEC. In the case of the INTEST instruction and ISCAN instruction, both are "1". Also, the internal scan signal I
SC0 is a signal which is set to "0" when the ISCAN instruction is executed, and is set to "1" at other times, and is generated by the instruction decoder DEC.

In the boundary scan cell BSSCK having such a configuration, even in the internal scan test, the ISC
When the AN instruction is executed, it functions as a control signal supply path to the internal combinational logic circuit, and supplies a clock pulse to control the internal scan chain and enables or disables a specific control signal as in this embodiment. Can control an internal combinational logic circuit.

Next, as shown in this embodiment (the BSC in FIG. 11)
FIG. 4 and FIG. 1 show the operation when testing a scan-designed LSI having internal scan chains ISC1 to ISC4 (where 7 is a control signal boundary scan).
This will be described according to the flowchart of FIG.

First, as in the conventional example (FIG. 12), in step S1, a TEST-LOGIC-RESET state is entered, and an INCODE instruction to be input to the instruction register IR is automatically generated. Next, the process enters the RUN-TEST / IDLE state in step S2, and enters the SELECT-DR-SCAN state in step S3.

Next, an INTEST instruction is input in step S4, which is executed by a subroutine shown in FIG. That is, the system enters the SELSCT-IR-SCAN state in step SI1, enters the CAPTURE-IR state in step SI2, and enters the SHIFT-IR state in step SI3. Where actually
The instruction code of INTEST is input. Further, step S
Enter EXIT-1-IR state at I4, UPD at step SI5
Enter ATE-IR state. Here, the parallel output of the instruction register IR is input to the instruction decoder DEC, and test logic suitable for the required operation is generated. That is, when the instruction for INTEST is input, INTEST is added after UPDARE-IR.
Mode.

Next, test data is input in step S5, which is executed by a subroutine shown in FIG. That is, the operation enters the SELECT-DR state in step SD1, enters the CAPTURE-DR state in step SD2, and enters the SHIFT-DR state in step SD3. Here, test data is actually input. In this example, BSC1 to BSC2
Since it has a boundary scan cell of 0, the data length is 20 bits. In step SD4, EXIT-
Enter the 1-DR state and enter the UPDATE-DR state in step SD5. Here, each boundary scan cell BSC1
The parallel output of the BSC 20 is supplied to a 4-bit adder ADDER which is an internal circuit.

Next, in step S6, an ISCAN instruction is input, and is executed in the subroutine of FIG. 13A as in step S4.

Next, in step S7, if there is the next test data, the flow returns to step S2 to repeat the processing of steps S2 to S6. If not, the flow returns to step S2.
By shifting in the dummy test data in step S5, the result for the previous test data is shifted out, and the process ends.

Returning to step S2, when entering the RUN-TEST / IDLE state, the boundary scan cell BSSCK (B
SC7) supplies the system clock SYSCLK (negative clock pulse) to the internal scan cells ISC1 to ISC4. At this time, at the rising edge of the system clock SYSCLK, the internal scan cells ISC1 to ISC1
4 is latched with the new value.

The test result for the test data input in a certain repetition process is output to the boundary scan cells BSC8 to BSC8 in the CAPTURE-DR state in step SD2 of step S5 in the next repetition.
13, BSC15, BSC17, and BSC19. Then, in the SHIFT-DR state in step SD3, the next new test data is shifted in, and at the same time, these results are shifted out from the terminal TDO.

As described above, in the test of the semiconductor integrated circuit of this embodiment, it is possible to perform one test cycle for one test data. Further, in the present embodiment, a 4-bit adder is taken as an example for the sake of simplicity.
Generally, I is a very large circuit, and the test data has a data length of several hundred bits or more. Therefore,
The processing time for inputting an instruction is negligible compared to the time required for inputting test data, and the processing time for a test according to the present embodiment can be reduced to about half as compared with the related art.

In the test data generation operation, there is no restriction that a specific bit is set to "0" at first and then to "1" as in the prior art, thereby facilitating the generation of test data.

Next, FIG. 2 shows a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

The configuration of the semiconductor integrated circuit of this embodiment includes two internal combinational logic circuits A and B and a test circuit 13 for performing a boundary scan test.

The test circuit 13 includes a TAP controller TAPC for controlling the test circuit 13, an instruction register IR for inputting and holding a test instruction from a test-dedicated input terminal TDI, and an instruction register IR for decoding and controlling the instruction. An instruction decoder DEC for outputting a group of signals is individually connected to an arbitrary input / output terminal of the combinational logic circuits A and B, and serves as a scan path at the time of a test. Internal scan cells ISC1 to ISC4 functioning as paths
Internal scan chains connected in series are individually connected to predetermined input / output terminals of the combinational logic circuits A and B and predetermined output terminals of the internal scan cells ISC1 to ISC4. , And the combinational logic circuits A and B
And a boundary scan chain in which boundary scan cells BCS1 to BCS8 and BSSCK functioning as a data path are connected in series.

The system clock S to the internal scan cells ISC1 to ISC4 in the boundary scan cell is used.
Boundary scan cell BSS connected to YSCLK
The CK has the configuration shown in FIG. 3 and functions as a control signal supply path to the combinational logic circuits A and B during the ISCAN instruction even during the test.

Next, the operation for testing the semiconductor integrated circuit of this embodiment will be described with reference to the flowcharts of FIGS.

First, similarly to the first embodiment (FIG. 4), the state is changed to the TEST-LOGIC-RESET state in step S11, and step S11 is executed.
RUN-TEST / IDLE status at 12 and SEL at step S13
Enter ECT-DR-SCAN state.

Next, in step S14, an INTEST instruction is input, which is executed by a subroutine shown in FIG.

Next, test data is input in step S15, which is executed by a subroutine shown in FIG. 13 (2).

Next, in step S16, an ISCAN instruction is input, and is executed in the subroutine of FIG. 13A as in step S14.

Next, in step S17, RUN-TEST / IDLE
The state is entered, and the system clock SYSCLK (negative clock pulse) is supplied from the boundary scan cell BSSCK to the internal scan cells ISC1 to ISC4. At this time, the rising edge of the system clock SYSCLK causes the internal scan cells ISC1 to ISC4 to perform step S
The result of the combinational logic circuit A for the test data input at 15 is latched.

Next, in step S18, the next test data is input, and is executed in the subroutine of FIG. 13B as in step S15.

Next, in step S19, an INTEST instruction is input again.

Next, at step S20, if there is the next test data, the process returns to step S15 and returns to steps S15 to S15.
The process of S19 is repeated.
Returning to step S15, the result for the previous test data is shifted out by shifting in the dummy test data in step S15, and the process ends.

The test result of the combinational logic circuit A with respect to the test data input in step S15 during a certain repetition processing is held in the internal scan cells ISC1 to ISC4 in the step S17 during the repetition processing. Is test data for the combinational logic circuit B, and the result is held in the output boundary scan cells BSC4 to BSC8 in the CAPTURE-DR state, which is step SD2 in step S15 in the next repetition. Then, in the SHIFT-DR state in step SD3, the next new test data is shifted in, and at the same time, these results are shifted out from the terminal TDO.

As described above, in this embodiment, a test can be continuously and efficiently performed even in a semiconductor integrated circuit having a configuration having an internal scan between two combinational logic circuits. It is possible to perform one test cycle for one test data. Further, in this embodiment, a semiconductor integrated circuit composed of two combinational logic circuits has been described as an example for the sake of simplicity, but the same applies to a configuration in which a plurality of combinational logic circuits are continuously connected. Test can be performed.

[0088]

As described above, according to the present invention, a boundary scan cell for a control signal which functions as a control signal supply path to an internal combinational logic circuit when a predetermined instruction is executed even during a test is constituted. Since the control signal boundary scan cell is connected to the control signal terminal for controlling the internal combinational logic circuit during the test, the test can be performed while controlling the internal combinational logic circuit. Since the test can be performed in one test cycle for one test data, as a result, a semiconductor integrated circuit that can be controlled by a control signal and can realize a high-speed test can be provided.

Also, in a semiconductor integrated circuit having an internal scan cell between n combinational logic circuits, a control signal terminal for controlling the internal combinational logic circuit during a test is connected to the control signal terminal. Because we decided to connect the boundary scan cell, for example,
By supplying the system clock to the internal scan cells between the combinational logic circuits during the test, a semiconductor integrated circuit capable of realizing a continuous and highly efficient test can be provided.

[Brief description of the drawings]

FIG. 1 is a diagram illustrating the principle of the present invention.

FIG. 2 is a configuration diagram of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 3 is a configuration diagram of a control signal boundary scan cell of the semiconductor integrated circuit of the present invention.

FIG. 4 is a flowchart of a test of the semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 5 is a flowchart of a test of a semiconductor integrated circuit according to a second embodiment of the present invention.

FIG. 6 is an explanatory diagram of a boundary scan test.

FIG. 7 is a basic configuration diagram of a boundary scan test circuit of a standardization proposal proposed by JTAG.

FIG. 8 is a state transition diagram of the TAP controller TAPC.

FIG. 9 is a circuit configuration diagram of a conventional input boundary scan register.

10A is a circuit configuration diagram of a conventional output boundary scan register, and FIG. 10B is a circuit configuration diagram of a conventional enable control boundary scan register.

FIG. 11 is a configuration diagram of a conventional semiconductor integrated circuit including a 4-bit adder and a test circuit, or a configuration diagram of a semiconductor integrated circuit according to the first embodiment of the present invention.

FIG. 12 is a flowchart of a test of a conventional semiconductor integrated circuit.

FIG. 13 is a flowchart of a test of the semiconductor integrated circuit. FIG. 13A shows a subroutine for inputting an instruction, and FIG.
(2) is a test data input subroutine.

[Explanation of symbols]

1, A, B Combinational logic circuit 3, 13 Test circuit TAPC TAP controller IR Instruction register DEC Instruction decoder DEC BSC1 to BSCm, BSSCK Boundary scan cell ISC1 to ISC4 Internal scan cell INMUX Input multiplexer SFF Scan flip-flop UFF Update flip-flop UMUX Update Multiplexer CKGEN Clock generation circuit TDI Test dedicated input terminal (test data) TDO test dedicated output terminal SYSCLK System clock (control signal terminal) ISC0 Internal scan signal IMC, OMC mode signal TMS test mode signal (terminal) TCK Test dedicated common clock (terminal ) TRST Test reset signal (pin) SFDR SHIFT-DR status signal CKDR CLOCK-DR status Signal UDDR UPDATE-DR Status signal IN, INA, IN1 to IN4 Input data (terminal) CIN Carry input (terminal) OUT, OT1 to OT4 Output data (terminal) COT Carry output (terminal) BI1 to BI4 Input / output terminal DR Data register BSR Boundary Scan Register BR Bypass Register DIR Device Identification Register DSTDR Unique Test Data Register

Claims (3)

(57) [Claims] An internal combinational logic circuit and a test circuit for performing a boundary scan test, wherein the test circuit inputs a test instruction from a TAP controller for controlling the test circuit and a test dedicated input terminal An instruction register to be held, an instruction decoder to decode a command word of the instruction register and output a control signal group, and are individually connected to respective input / output terminals of the combinational logic circuit. And a boundary scan chain formed by serially connecting a boundary scan cell functioning as a data path of the combinational logic circuit, and any control for controlling the semiconductor integrated circuit among the boundary scan cells. The boundary scan cell connected to the signal terminal is The semiconductor integrated circuit even when a predetermined instruction is executed Oite, characterized in that it functions as a control signal supply path to the combinational logic circuit. 2. An internal logic circuit comprising n (n: an arbitrary positive integer) combinational logic circuits and a test circuit for performing a boundary scan test, wherein the test circuit controls a TAP controller for controlling the test circuit; An instruction register for inputting and holding a test instruction from a dedicated test input terminal, an instruction decoder for decoding a command word of the instruction register and outputting a control signal group, and an arbitrary input / output terminal of the n combinational logic circuits And an internal scan chain formed by serially connecting internal scan cells, which are individually connected in correspondence with each other and function as a scan path during a test and as a data path of the n combinational logic circuits during a normal operation, and Individually connected to predetermined input / output terminals of the combinational logic circuits and predetermined output terminals of the internal scan cell. A boundary scan chain that is connected in series with a boundary scan path functioning as a path of a boundary scan during a test and as a data path of the n combinational logic circuits during a normal operation; and The boundary scan cell connected to an arbitrary control signal terminal for controlling the semiconductor integrated circuit functions as a control signal supply path to the n combinational logic circuits at the time of executing a predetermined instruction even during a test. Semiconductor integrated circuit. 3. A boundary scan cell connected to an arbitrary control signal terminal, comprising: an input multiplexer for selecting and outputting test data at the time of test data input and a control signal input to the combinational logic circuit at other times. A scan flip-flop that holds the output of the input multiplexer and outputs the output to a dedicated test output terminal; an update flip-flop that holds the output of the scan flip-flop when test data is updated; and an update flip-flop that holds the output during a test other than when the predetermined instruction is executed. 2. An update multiplexer for selecting and outputting a control signal input to the combinational logic circuit when outputting the output of the flip-flop at the time of testing and executing the predetermined instruction or other than testing. Or 2
3. The semiconductor integrated circuit according to claim 1.