JP2002323542A - Boundary scan register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a macro cell capable of testing a signal wiring therebetween even when an IC on an other side does not correspond with a JTAG. SOLUTION: In a normal mode, a selector 26 is switched to a side of a terminal A, input data XI of an input terminal 21 is outputted as output data XO as it is from an output terminal 27. In a test mode, selectors 23, 26, 28 are switched to a side of a terminal B, FFs 24, 29 are cascade-connected through the selector 28, and a shift register of two stages is structured. At that time, the FFs 24, 28 respectively hold data to be outputted to the output terminal 27 and actual data which was outputted to the output terminal 27. Thereby, the holding data of the FFs 24, 28 is shifted by a control signal TCK, and is read out as a control signal TDO from an output terminal 25 so that whether the signal wiring connected to the output terminal 27 is good or not is tested.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a JTAG (Joint
Test Action Group) relates to a boundary scan register (hereinafter, referred to as a “macro cell”) incorporated in a device compatible with a test system.

[0002]

2. Description of the Related Art Conventionally, as a test of a printed circuit board, a needle mountain such as a sword used for ikebana is pressed against a terminal or the like of a device mounted on a printed circuit board to be tested.
The “in-circuit test method” was the mainstream.
However, due to high integration of devices and high-density mounting of printed circuit boards, the number of terminals of the device is increasing and the interval between terminals is becoming narrower. For this reason, the interval between the terminals is narrower than the interval between the test needles, and a state in which the test becomes extremely difficult has occurred. Furthermore, BGA (BallGrid
In an Array) package, since ball-shaped terminals are arranged on the back surface of the package, it is impossible to apply a test needle to the package terminals after surface mounting on a printed circuit board. The JTAG test standardized by IEEE1149.1 has emerged as a new test method to save such situations.

In the JTAG test, a printed circuit board on which a device such as an IC in which a JTAG-compatible circuit is pre-installed is mounted, and a test circuit in the device is driven to judge the quality of the printed circuit board. This is a test method.

FIG. 2 is a configuration diagram for explaining the concept of the JTAG test system. As shown in FIG.
In the TAG test system, a test apparatus 1 and a printed circuit board 2 to be tested are connected by a serial interface called a TAP (Test Access Port). TAP is T
DI (Test Data In), TDO (Test DataOut), TC
K (Test Clock), TMS (Test Mode Select), TR
It is composed of five control signals ST (Test Reset).

The control signal TDI is a signal that gives test data from the test apparatus 1 to the printed circuit board 2 in series. The control signal TDO is a signal for outputting data from the printed circuit board 2 to the test apparatus 1. Control signal TC
K is a clock signal for giving a timing such as data input / output from the test apparatus 1 to the printed circuit board 2. The control signal TMS is a signal for giving a command for controlling a test operation from the test apparatus 1 to the printed circuit board 2. The control signal TRST is a reset signal for asynchronously initializing the printed circuit board 2 from the test apparatus 1.

The test apparatus 1 is usually a personal computer, which is provided with a JTAG control board for inputting and outputting a control signal TDI and the like, and a control program. Also,
The test apparatus 1 includes a test data creation tool for creating test data to be output as a control signal TDI, and a test result for decoding a control signal TDO output from the printed circuit board 2 and determining whether the printed circuit board 2 is defective. It has software such as analysis tools.

On the other hand, the printed circuit board 2 to be tested is provided with a connector 3 for connecting a test cable from the test apparatus 1 and a plurality of JTAG-compliant ICs (In
integrated circuit) 10 is mounted.

Each IC 10 has an internal logic circuit 11 for executing an original function, and a plurality of terminals 12 for inputting / outputting an original signal to / from the internal logic circuit 11. Further, each IC 10 has a control signal TD for testing.
A terminal 13 to which I, TMS, TCK, and TRST are inputted;
14, 15, 16 and a terminal 1 for outputting a control signal TDO
7 is provided.

A TAP controller 18 is connected to terminals 14, 15, and 16, and an instruction register (IN) is connected to terminal 13.
-REG) 19a, and a bypass register (BP-REG) 19b is connected between the terminals 13 and 14. A macro cell 20 is provided between the internal logic circuit 11 and each terminal 12.

The TAP controller 18 samples the control signal TMS at the terminal 14 at the rise of the control signal TCK supplied from the terminal 15, and controls the control signal TMS.
Is a state machine that transits to a preset next state according to the logical value “0” / “1” of the current state. Various control signals (not shown) are output from the TAP controller 18 to the registers 19a and 19b and the macro cell 20 in accordance with the transition state.

The instruction register 19a reads and decodes instruction bits in a control signal TDI supplied from the terminal 13, and thereby allows the TAP controller 18 to execute various functions. Also, the bypass register 19b is connected to the terminal 13 without passing through the macrocell 20.
The control signal TDI input from the
And a bypass path for outputting the control signal TDO to the control circuit.

The macro cell 20 is inserted between the internal logic circuit 11 of the IC 10 and the input / output terminal 12. In the test mode, all the macro cells 20 in the IC 10 are connected in series, A shift register for sequentially transferring twelve signals can be configured. The input side of the first macrocell 20 of this shift register is connected to terminal 13 and the output side of the last macrocell 20 is connected to terminal 17.

A plurality of ICs 1 mounted on a printed circuit board 2
0 (in this figure, IC10₁, 10 ₂Only display)
The power terminals 12 are connected by a plurality of signal wires 4.
I have. The terminals 14, 15, 16 of each IC 10 are
Control signals TMS, TCK, TRS from connector 3 respectively
They are connected so that T is given in common.

On the other hand, terminals 13 and 17 of each IC 10 are connected in a daisy chain. That is, the control signal TDI from the connector 3 is applied to the IC 10 ₁ of terminal 13, a control signal TDO output from the IC 10 ₁ terminal 17
But the next IC 10 ₂ of terminal 13, is supplied as a control signal TDI. Furthermore, the control signal TDO output from IC 10 ₂ to terminal 17, the test device through the connector 3 1
Is output as a control signal TDO.

FIG. 3 is a configuration diagram of a conventional macro cell 20 in the IC 10 in FIG. This macro cell 20
Has an input terminal 21 to which input data XI is supplied from the internal logic circuit 11 or the input terminal 12, and an input terminal 22 to which a control signal TDI is supplied from a preceding macro cell or the like. The input terminals 21 and 22 are connected to a selector (SE
L) 23 are connected to terminals A and B, respectively. The selector 23 is controlled by a shift signal SFT provided from the TAP controller 18 to the terminal C, and the terminals A and B
Is selected and output to the terminal O. A terminal O of the selector 23 is connected to a terminal D of a flip-flop (hereinafter, referred to as “FF”) 24.

The FF 24 holds the signal at the terminal D and outputs it to the terminal Q at the rising timing of the control signal TCK applied to the terminal CK. The terminal Q of the FF 24 is connected to an output terminal 25 that outputs a control signal TDO to a subsequent macro cell or the like, and is also connected to a terminal B of a selector 26. The terminal A of the selector 26 is connected to the input terminal 21, and a mode signal MOD for switching between the test mode and the normal mode is supplied to the terminal C from the TAP controller 18. The terminal O of the selector 26 is connected to the output terminal 27. The output terminal 27 connects the internal logic circuit 11 or the output terminal 12 to the output terminal 27.
The output data XO is output to the

In the JTAG test system, when the normal mode is set, the selector 26 in each macro cell 20 is switched to the terminal A by the mode signal MOD given from the TAP controller 18 of each IC 10. Thereby, the terminal 21 of the macro cell 20
And the terminal 27 are connected to the internal logic circuit 11 of each IC 10.
And the input / output terminal 12 are directly connected to perform a normal operation.

On the other hand, when the test mode is set, the selector 2 in each macro cell 20 is operated by the mode signal MOD.
6 is switched to the terminal B side, and the internal logic circuit 11 of the IC 10 and the input / output terminal 12 are disconnected.

Further, the TAP controller 1 of each IC 10
When the selector 23 is switched to the terminal A side by the shift signal SFT given from 8, the input data XI of the input terminal 21 is given to the terminal D of the FF 24 via the selector 23. Here, when the control signal TCK rises, the input data XI is held in the FF 24 and
5 is output as a control signal TDO.

Thereafter, when the selector 23 is switched to the terminal B side by the shift signal SFT, the control signal TDI of the input terminal 22 is transmitted through the selector 23 to the FF 24.
Of the terminal D. As a result, all the macro cells 20 in the IC 10 are daisy-chain-connected to form a shift register. Further, since the respective ICs 10 are also connected by the signal wiring 4, the printed circuit board 2
The macrocells 20 of all the above ICs 10 are daisy-chained to form a series of shift registers.

Here, the control signal TDI is applied from the test apparatus 1 in accordance with the timing of the control signal TCK. As a result, the control signal TDI is sequentially transferred to the FFs 24 of the macro cells 20 in each IC 10, and the data held in these FFs 24 is sequentially read out and output to the connector 3 as the control signal TDO. The test apparatus 1 outputs test data as a control signal TDI and analyzes the control signal TDO read from the printed circuit board 2 to determine the quality of the signal wiring 4 on the printed circuit board 2. it can.

[0022]

However, the conventional macro cell 20 has the following problems. JTA
The G test, for example, compares the signal output from the terminal 12 for IC 10 ₁ of the output signal line 4 in FIG. 2, the signal input to the terminal 12 for the IC 10 ₂ inputs, based on the comparison result The quality of the signal wiring 4 during that time is determined. That is, JTAG is provided on both sides of the signal wiring 4 to be tested.
It is assumed that the corresponding IC 10 is connected. Therefore, when one of the ICs (for example, IC10 ₂ ) connected to the signal wiring 4 does not support JTAG,
There is a problem that the test of the signal wiring 4 becomes extremely difficult.

The present invention solves the above-mentioned problems of the prior art, and the IC on the other side connected by signal wiring is JTA.
It is an object of the present invention to provide a macro cell which can test whether a signal wiring is good or not even if it does not support G.

[0024]

In order to solve the above-mentioned problems, a first aspect of the present invention is to provide an internal device in a device mounted on a printed circuit board for testing signal wiring on the printed circuit board. Provided between a logic circuit and an input or output terminal, connects the internal logic circuit to the input or output terminal in a normal mode, and sequentially shifts the signal of the internal logic circuit or the input or output terminal in a test mode The macro cell connected so as to transfer the data is configured as follows.

That is, the macro cell comprises: a first selection means for selecting and outputting one of a signal of the internal logic circuit and a signal from the macro cell of the preceding stage in accordance with a selection signal;
First holding means for holding the signal selected by the selection means according to the clock signal, and selecting the signal of the internal logic circuit in the normal mode, and holding the signal held by the first holding means in the test mode. And a shift means for sequentially outputting the signal selected by the second selection means and the signal held by the first holding means to a subsequent macro cell in accordance with the clock signal. Have.

According to a second aspect of the present invention, the shift means in the macro cell according to the first aspect of the present invention selects the signal output from the second selecting means when the signal of the internal logic circuit is selected by the first selecting means. And a third selecting means for selecting the signal held by the first holding means when the signal of the preceding macro cell is selected by the first selecting means, and a selecting means for selecting the signal held by the third selecting means. And a second holding means for holding the signal in accordance with the clock signal and sequentially outputting the signal to a subsequent macro cell.

According to the present invention, since the macro cell is configured as described above, the following operation is performed. In the normal mode, the signal of the internal logic circuit is selected and output by the second selection means. On the other hand, in the test mode, the first and second holding units are cascade-connected via the third selection unit by the selection signal, thereby forming a two-stage shift register. Then, the signal from the preceding macro cell is given to the first holding means via the first selecting means, and the output signal of the second holding means is output to the subsequent macro cell.
When a clock signal is commonly applied to the first and second holding units, a signal indicating the state of the output terminal held by the second holding unit is output, and the first holding signal is output by the next clock signal. A signal given from the internal logic circuit held by the means is output. Therefore, by comparing these two signals, it is possible to test the state of the state of the signal wiring connected to the output terminal.

[0028]

FIG. 1 is a configuration diagram of a macro cell 20A showing an embodiment of the present invention, and is used as the macro cell in FIG. 2 instead of the macro cell 20 in FIG. In FIG. 1, components common to those in FIG. 3 are denoted by common reference numerals.

The macro cell 20A has an internal logic circuit 1
1 or an input terminal 21 to which input data XI is supplied from an input terminal 12;
Has an input terminal 22 to which a control signal TDI is applied. The input terminals 21 and 22 are connected to terminals A and B of a first selection unit (for example, a selector) 23, respectively. The selector 23 is controlled by a shift signal SFT provided from the TAP controller 18 to the terminal C,
One of the signals of the terminals A and B is selected and output to the terminal O. The terminal O of the selector 23 is connected to the terminal D of the first holding means (for example, FF) 24.

The FF 24 holds the signal at the terminal D and outputs it to the terminal Q at the rising timing of the control signal TCK applied to the terminal CK. The terminal Q of the FF 24 is connected to the terminal B of the second selecting means (for example, a selector) 26. The terminal A of the selector 26 is connected to the input terminal 21, and a mode signal MOD for switching between the test mode and the normal mode is supplied to the terminal C from the TAP controller 18. The terminal O of the selector 26 is connected to the output terminal 27. The output terminal 27 connects the internal logic circuit 11 or the output terminal 12 to the output terminal 27.
, The output data XO is output.

Further, a terminal O of the selector 26 is connected to a terminal A of a third selecting means (for example, a selector) 28. The terminal Q of the FF 24 is connected to the terminal B of the selector 28. The selector 28 is controlled by a shift signal SFT applied to the terminal C, selects one of the terminals A and B, and outputs the selected signal to the terminal O, similarly to the selector 23. The terminal O of the selector 28 is
It is connected to the terminal D of the second holding means (for example, FF) 29.

The FF 29 has a terminal CK like the FF 24.
The signal at the terminal D is held and output to the terminal Q at the rising timing of the control signal TCK given to the terminal. The terminal Q of the FF 29 is connected to the output terminal 25 that outputs the control signal TDO to the macro cell or the terminal 17 at the subsequent stage.

FIG. 4 is a signal waveform diagram showing an example of the operation of the macro cell 20A of FIG. 1 in the test mode. Hereinafter, the operation of the macro cell 20A of FIG. 1 will be described with reference to FIG.

At time t1 in FIG. 4, the mode signal MO
It is assumed that D and the shift signal SFT are both at the level “L”, and the selectors 23, 26, and 28 are all switched to the terminal A side. As a result, the data “b” of the input signal XI of the input terminal 21 is provided to the terminal D of the FF 24 via the selector 23 and is output to the output terminal 27 via the selector 26. Further, the output signal XO of the output terminal 27 is output.
Is supplied to the terminal D of the FF 29 via the selector 28. Therefore, if the signal wiring 4 connected to the output terminal 27 is normal, the data “b” of the input signal XI and the data “a” of the output signal XO should match. If the signal wiring 4 is short-circuited to the ground potential or the like, the data “a” and “b” do not always match.

At time t2, when the control signal TCK rises from "L" to level "H", the data "b" is held in the FF 24, the signal S24 becomes "b", and the terminal B of the selectors 26 and 28 Is output. Also, FF2
9 holds data "a", and the control signal TDO of the output terminal 25 becomes data "a".

At time t3, when both the mode signal MOD and the shift signal SFT become "H", the selector 23,
26 and 28 are all switched to the terminal B side. As a result, the data “c” of the control signal TDI of the input terminal 22
Is supplied to the terminal D of the FF 24 via the selector 23. Further, the signal S24 of the FF 24 is output to the output terminal 27 via the selector 26 and is also applied to the terminal D of the FF 29 via the selector 28. That is, the input terminal 2
The control signal TDI given to the FF2 is input to the FF2
4, 29 to form a two-stage shift register.
The control signal TDO is output to the output terminal 25 from F29.

At time t4, when the control signal TCK rises from "L" to "H", the data "c" of the control signal TDI is held in the FF 24 and output as a signal S24, and is held in the FF 24 until then. The data “b” is held in the FF 29 and output from the output terminal 25 as the control signal TDO.

Further, when the control signal TCK rises from "L" to "H" at the time t5, the data "d" of the control signal TDI is held in the FF 24 and output as a signal S24. The data “c” held is held in the FF 29 and output from the output terminal 25 as the control signal TDO.

Similarly, at the rising timing of the control signal TCK, the control signal T
DI is sequentially shifted by the FFs 24 and 29 and output from the output terminal 25 as a control signal TDO.

Therefore, by providing the control signal TCK from the test apparatus 1 of FIG. 2, the data held in the FFs 29 and 24 of the macrocell 20A in each IC 10 mounted on the printed circuit board 2 is sequentially read out. Connector 3
Is output as a control signal TDO. In the test apparatus 1, by analyzing the control signal TDO read from the printed board 2, the quality of the signal wiring 4 on the printed board 2 can be determined.

That is, if the data "a" and "b" of the control signal TDO read from the macro cell 20A in the IC 10 match, the output terminal 27 of this macro cell 20A
Is determined to be normal. If these data "a" and "b" do not match, the signal wiring 4 connected to the output terminal 27 of the macro cell 20A.
Is determined to be abnormal.

In the normal mode, the mode signal MO
The selector 26 is switched to the terminal A by D, and the input data XI given to the input terminal 21 is output from the output terminal 27 as it is as the output data XO.

As described above, the macro cell of this embodiment is
In addition to the FF 24 for holding the data “b” output to the output terminal 27, the output terminal 2 to which the signal wiring 4 is connected
An FF 29 for holding the data “a” in the state 7 is provided. Further, in the test mode, there is provided a selector 28 for connecting these FFs 24 and 29 in series by the shift signal SFT to constitute a two-stage shift register. As a result, the IC at one end of the signal wiring 4 is
Even if it is not compatible with G, there is an advantage that the quality of the signal wiring 4 can be determined by comparing the data “a” and “b” held and read by the FFs 24 and 29.

It should be noted that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications.

(A) The macro cell 20A shown in FIG. 1 has a configuration having the minimum necessary functions, but may further include elements for executing various test functions.

(B) It is not necessary that all the macrocells in the IC 10 are constituted by the macrocells 20A as shown in FIG. 1, but may be mixed with the conventional macrocells 20 of FIG. 3 according to the connected IC. .

[0047]

As described in detail above, according to the first aspect, the state of the signal selected by the second selecting means and output to the output terminal and the state of the signal held by the first holding means are stored. There is a shift means for sequentially shifting and outputting a signal to be output to the output terminal. Thus, by comparing the two signals output from the shift means, it is possible to test the quality of the state of the signal wiring connected to the output terminal.

According to the second invention, the shift means is constituted by the third selecting means similar to the first selecting means and the second holding means similar to the first holding means. Thus, the shift means can be configured with a simple circuit.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a macro cell 20A showing an embodiment of the present invention.

FIG. 2 is a configuration diagram for explaining the concept of a JTAG test system.

FIG. 3 shows a conventional macro cell 2 in the IC 10 in FIG.
FIG.

FIG. 4 is a signal waveform diagram showing an example of an operation of the macro cell 20A of FIG. 1 in a test mode.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test apparatus 2 Printed circuit board 3 Connector 4 Signal wiring 10 IC 11 Internal logic circuit 12-17 Terminal 18 TAP controller 20A Macrocell 21,22 Input terminal 23,26,28 Selector 24,29 FF (flip flop) 25,27 Output Terminal

Claims (2)

[Claims] 1. A test circuit for testing a signal wiring of a printed circuit board, which is provided between an internal logic circuit in a device mounted on the printed circuit board and an input or output terminal. An input or output terminal, and a boundary scan register connected to sequentially shift and transfer the signal of the internal logic circuit or the input or output terminal in a test mode; First selecting means for selecting and outputting one of the signals from the boundary scan register of the preceding stage in accordance with a selection signal, and first holding for holding the signal selected by the first selecting means in accordance with a clock signal Means for selecting a signal of the internal logic circuit in the normal mode, and a signal held by the first holding means in the test mode. And a signal selected by the second selecting means and a signal held by the first holding means are sequentially output to a subsequent boundary scan register in accordance with the clock signal. And a shift means. 2. The method according to claim 1, wherein the shifter selects a signal output from the second selector when a signal of an internal logic circuit is selected by the first selector. Boundary scan
A third selecting means for selecting a signal held by the first holding means when a signal of the register is selected; and holding the signal selected by the third selecting means in accordance with the clock signal. And a second holding means for sequentially outputting the data to a subsequent boundary scan register.
Scan register.