JP2002323541A - Boundary scan register - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a macro cell capable of testing an analogue signal wiring. SOLUTION: In a test mode, a control signal TDI is inputted in an input terminal 32, and is converted into an analogue signal by a D/A 37, and an analogue output signal AO is outputted from an output terminal through a selector 38. Thereby, the analogue signal for a test can be outputted to a signal wiring or the like connected to the output terminal 35. On the other hand, an analogue input signal AI of the input terminal 31 is converted into a digital signal by an A/D 33, is fed to a parallel input terminal PI of a register 34, and is held in parallel by the register 34 in accordance with a control signal SFT. The digital signal held by the resister 34 is sequentially shifted in accordance with a timing of a control signal TCK, is read out, and is outputted as a control signal TDO from the output terminal 35. Thus, whether the signal wiring connected to the input terminal 31 is good or not is tested by analyzing the control signal TDO.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a JTAG (Joint
Test Action Group) relates to a boundary scan register (hereinafter, referred to as a “macro cell”) incorporated in a device compatible with a test system.

[0002]

2. Description of the Related Art Conventionally, as a test of a printed circuit board, a needle mountain such as a sword used for ikebana is pressed against a terminal or the like of a device mounted on a printed circuit board to be tested.
The “in-circuit test method” was the mainstream.
However, due to high integration of devices and high-density mounting of printed circuit boards, the number of terminals of the device is increasing and the interval between terminals is becoming narrower. For this reason, the interval between the terminals is narrower than the interval between the test needles, and a state in which the test becomes extremely difficult has occurred. Furthermore, BGA (BallGrid
In an Array) package, since ball-shaped terminals are arranged on the back surface of the package, it is impossible to apply a test needle to the package terminals after surface mounting on a printed circuit board. The JTAG test standardized by IEEE1149.1 has emerged as a new test method to save such situations.

In the JTAG test, a printed circuit board on which a device such as an IC in which a JTAG-compatible circuit is pre-installed is mounted, and a test circuit in the device is driven to judge the quality of the printed circuit board. This is a test method.

FIG. 2 is a configuration diagram for explaining the concept of the JTAG test system. As shown in FIG.
In the TAG test system, a test apparatus 1 and a printed circuit board 2 to be tested are connected by a serial interface called a TAP (Test Access Port). TAP is T
DI (Test Data In), TDO (Test DataOut), TC
K (Test Clock), TMS (Test Mode Select), TR
It is composed of five control signals ST (Test Reset).

The control signal TDI is a signal that gives test data from the test apparatus 1 to the printed circuit board 2 in series. The control signal TDO is a signal for outputting data from the printed circuit board 2 to the test apparatus 1. Control signal TC
K is a clock signal for giving a timing such as data input / output from the test apparatus 1 to the printed circuit board 2. The control signal TMS is a signal for giving a command for controlling a test operation from the test apparatus 1 to the printed circuit board 2. The control signal TRST is a reset signal for asynchronously initializing the printed circuit board 2 from the test apparatus 1.

The test apparatus 1 is usually a personal computer, which is provided with a JTAG control board for inputting and outputting a control signal TDI and the like, and a control program. Also,
The test apparatus 1 includes a test data creation tool for creating test data to be output as a control signal TDI, and a test result for decoding a control signal TDO output from the printed circuit board 2 and determining whether the printed circuit board 2 is defective. It has software such as analysis tools.

On the other hand, the printed circuit board 2 to be tested is provided with a connector 3 for connecting a test cable from the test apparatus 1 and a plurality of JTAG-compliant ICs (In
integrated circuit) 10 is mounted.

Each IC 10 has an internal logic circuit 11 for executing an original function, and a plurality of terminals 12 for inputting / outputting an original signal to / from the internal logic circuit 11. Further, each IC 10 has a control signal TD for testing.
A terminal 13 to which I, TMS, TCK, and TRST are inputted;
14, 15, 16 and a terminal 1 for outputting a control signal TDO
7 is provided.

A TAP controller 18 is connected to terminals 14, 15, and 16, and an instruction register (IN) is connected to terminal 13.
-REG) 19a, and a bypass register (BP-REG) 19b is connected between the terminals 13 and 14. A macro cell 20 is provided between the internal logic circuit 11 and each terminal 12.

The TAP controller 18 samples the control signal TMS at the terminal 14 at the rise of the control signal TCK supplied from the terminal 15, and controls the control signal TMS.
Is a state machine that transits to a preset next state according to the logical value “0” / “1” of the current state. Various control signals (not shown) are output from the TAP controller 18 to the registers 19a and 19b and the macro cell 20 in accordance with the transition state.

The instruction register 19a reads and decodes instruction bits in a control signal TDI supplied from the terminal 13, and thereby allows the TAP controller 18 to execute various functions. Also, the bypass register 19b is connected to the terminal 13 without passing through the macrocell 20.
The control signal TDI input from the
And a bypass path for outputting the control signal TDO to the control circuit.

The macro cell 20 is inserted between the internal logic circuit 11 of the IC 10 and the input / output terminal 12. In the test mode, all the macro cells 20 in the IC 10 are connected in series, A shift register for sequentially transferring twelve signals can be configured. The input side of the first macrocell 20 of this shift register is connected to terminal 13 and the output side of the last macrocell 20 is connected to terminal 17.

A plurality of ICs 1 mounted on a printed circuit board 2
0 (in this figure, IC10₁, 10 ₂Only display)
The power terminals 12 are connected by a plurality of signal wires 4.
I have. The terminals 14, 15, 16 of each IC 10 are
Control signals TMS, TCK, TRS from connector 3 respectively
They are connected so that T is given in common.

On the other hand, terminals 13 and 17 of each IC 10 are connected in a daisy chain. That is, the control signal TDI from the connector 3 is applied to the IC 10 ₁ of terminal 13, a control signal TDO output from the IC 10 ₁ terminal 17
But the next IC 10 ₂ of terminal 13, is supplied as a control signal TDI. Furthermore, the control signal TDO output from IC 10 ₂ to terminal 17, the test device through the connector 3 1
Is output as a control signal TDO.

FIG. 3 is a configuration diagram of a conventional macro cell 20 in the IC 10 in FIG. This macro cell 20
Has an input terminal 21 to which input data XI is supplied from the internal logic circuit 11 or the input terminal 12, and an input terminal 22 to which a control signal TDI is supplied from a preceding macro cell or the like. The input terminals 21 and 22 are connected to a selector (SE
L) 23 are connected to terminals A and B, respectively. The selector 23 is controlled by a shift signal SFT provided from the TAP controller 18 to the terminal C, and the terminals A and B
Is selected and output to the terminal O. A terminal O of the selector 23 is connected to a terminal D of a flip-flop (hereinafter, referred to as “FF”) 24.

The FF 24 holds the signal at the terminal D and outputs it to the terminal Q at the rising timing of the control signal TCK applied to the terminal CK. The terminal Q of the FF 24 is connected to an output terminal 25 that outputs a control signal TDO to a subsequent macro cell or the like, and is also connected to a terminal B of a selector 26. The terminal A of the selector 26 is connected to the input terminal 21, and a mode signal MOD for switching between the test mode and the normal mode is supplied to the terminal C from the TAP controller 18. The terminal O of the selector 26 is connected to the output terminal 27. The output terminal 27 connects the internal logic circuit 11 or the output terminal 12 to the output terminal 27.
The output data XO is output to the

In the JTAG test system, when the normal mode is set, the selector 26 in each macro cell 20 is switched to the terminal A by the mode signal MOD given from the TAP controller 18 of each IC 10. Thereby, the terminal 21 of the macro cell 20
And the terminal 27 are connected to the internal logic circuit 11 of each IC 10.
And the input / output terminal 12 are directly connected to perform a normal operation.

On the other hand, when the test mode is set, the selector 2 in each macro cell 20 is operated by the mode signal MOD.
6 is switched to the terminal B side, and the internal logic circuit 11 of the IC 10 and the input / output terminal 12 are disconnected.

Further, the TAP controller 1 of each IC 10
When the selector 23 is switched to the terminal A side by the shift signal SFT given from 8, the input data XI of the input terminal 21 is given to the terminal D of the FF 24 via the selector 23. Here, when the control signal TCK rises, the input data XI is held in the FF 24 and
5 is output as a control signal TDO.

Thereafter, when the selector 23 is switched to the terminal B side by the shift signal SFT, the control signal TDI of the input terminal 22 is transmitted through the selector 23 to the FF 24.
Of the terminal D. As a result, all the macro cells 20 in the IC 10 are daisy-chain-connected to form a shift register. Further, since the respective ICs 10 are also connected by the signal wiring 4, the printed circuit board 2
The macrocells 20 of all the above ICs 10 are daisy-chained to form a series of shift registers.

Here, the control signal TDI is applied from the test apparatus 1 in accordance with the timing of the control signal TCK. As a result, the control signal TDI is sequentially transferred to the FFs 24 of the macrocells 20 in each IC 10, and the data held in these FFs 24 is sequentially read out and output to the connector 3 as the control signal TDO. The test apparatus 1 outputs test data as a control signal TDI and analyzes the control signal TDO read from the printed circuit board 2 to determine the quality of the signal wiring 4 on the printed circuit board 2. it can.

[0022]

However, the conventional macro cell 20 has the following problems. That is,
The input signal XI applied to the terminal 21 has a logical value “0” /
It is assumed that the digital signal is "1". For this reason,
It could not be applied to analog signals, making it impossible to test analog signal wiring.

The present invention solves the problems of the prior art and provides a macrocell capable of testing analog signal wiring.

[0024]

SUMMARY OF THE INVENTION In order to solve the above-mentioned problems, the present invention provides a method for testing a signal wiring on a printed circuit board, which comprises connecting an internal circuit in a device mounted on the printed circuit board to an input / output terminal. A macro cell is provided between the internal circuit and the input / output terminal in the normal mode, and is connected to sequentially transfer the signal of the internal circuit or the input / output terminal in the test mode. It is configured as follows.

That is, the macro cell includes an analog / digital conversion means for converting an analog signal of an internal circuit or an input / output terminal into a digital signal, a signal from a macro cell in a preceding stage and a digital signal converted by the analog / digital conversion means. When the holding mode is designated by the control signal, the digital signal is held, and when the transfer mode is designated by the control signal, the held digital signal and the signal from the preceding macrocell are clocked by the clock signal. , A serial / parallel converter for converting a signal sequentially output from the shift unit into parallel data, and a parallel data converted by the serial / parallel converter into an analog signal. Digital / analog conversion means for performing Select the analog signal parts circuit or output terminal, wherein the test mode comprises a selection means for outputting to the output terminal or internal circuit selects the converted analog signal by the digital / analog converter.

According to the present invention, since the macro cell is configured as described above, the following operation is performed. In the test mode, when the holding mode is designated by the control signal, the analog signal of the internal circuit or the input / output terminal converted into the digital signal by the analog / digital converting means is held in the shift means. Next, when the transfer mode is designated by the control signal, the digital signal held by the shift means and the signal from the preceding macrocell are sequentially shifted and output according to the clock signal. The digital signals sequentially output from the shift means are converted into parallel data by the serial / parallel conversion means, and are converted into analog signals by the digital / analog conversion means. Further, the analog signal converted by the digital / analog conversion means is selected by the selection means and output to an input / output terminal or an internal circuit.

In the normal mode, an analog signal of the internal circuit or the input / output terminal is selected by the selection means and output to the input / output terminal or the internal circuit.

[0028]

FIG. 1 is a block diagram of a macro cell 30 showing an embodiment of the present invention, which is used as a macro cell for an analog signal in FIG. 2 together with a macro cell 20 in FIG. .

The macro cell 30 has an input terminal 31 to which an analog input signal AI is supplied from the internal logic circuit 11 or the input terminal 12 of the IC 10, and an input terminal 32 to which a control signal TDI is supplied from the preceding macro cell or terminal 13. have. The input terminal 31 is connected to an input side of an analog / digital converter (for example, an analog / digital converter, hereinafter, referred to as “A / D”) 33. The A / D 33 converts an analog signal supplied to the input side into a digital signal and outputs the digital signal as, for example, an 8-bit parallel signal. The output side of the A / D 33 is connected to a parallel input terminal PI of a shift means (for example, a register (REG)) 34.

The register 34 is an 8-bit parallel input serial output type shift register having a parallel input terminal PI and a serial input terminal SI. When the shift signal SFT applied to the control terminal PL is at level "H", the register 34 holds an 8-bit digital signal applied to the parallel input terminal PI. Also, the shift signal S
When FT is at level “L”, the register 34 controls the control signal TD applied to the serial input terminal SI at the rising timing of the control signal TCK applied to the clock terminal CK.
The digital signal held as I is sequentially shifted one bit at a time, and output in series from an output terminal SO. The output terminal SO of the register 34 receives the control signal T
An output terminal 35 for outputting a DO is connected to an input side of a serial / parallel converter (for example, a serial / parallel converter, hereinafter, referred to as “S / P”) 36.

The S / P 36 is a serial input / parallel output type 8-bit shift register which holds the signal on the input side and sequentially shifts one bit at a time when the control signal TCK applied to the clock terminal CK rises. Things. The 8-bit digital signal held in the S / P 36 is output in parallel. On the output side of the S / P 36, digital / analog conversion means (for example,
A digital / analog converter (hereinafter, referred to as “D / A”) 37 is connected. The D / A 37 converts an 8-bit digital signal supplied to the input side into a voltage and outputs an analog signal. An output side of the D / A 37 is connected to a second input side of the selection means (for example, a selector) 38.

The selector 38 switches an analog signal supplied to the first and second input sides based on the mode signal MOD and outputs the signal to an output terminal 39. The selector 38 corresponds to the first and second inputs. Analog switches (SW)
38a and 38b. Analog switch 3
The input side of 8a is connected to the input terminal 31, and the input side of the analog switch 38b is connected to the output side of the D / A 37. The output sides of the analog switches 38a and 38b are commonly connected to an output terminal 39. Analog switch 3
8a and 38b are set to be turned on and off, respectively, when the mode signal MOD is "L", and turned off and turned on, respectively, when the mode signal MOD is "H".

Next, the operation will be described. In normal mode,
The mode signal MOD is set to “L”, and the first input side of the selector 38, that is, the analog switch 38a is turned on. As a result, the analog input signal AI input to the input terminal 31 is directly output from the output terminal 39 to the output signal A.
Output as O.

In the test mode, the mode signal MOD is set to "H", and the second input of the selector 38, that is, the analog switch 38b is turned on. This gives D
/ A37 is output from an output terminal 39
Is output as an output signal AO. On the other hand, input terminal 3
The analog input signal AI inputted to the A / D 33
Is converted into an 8-bit digital signal, and supplied to the parallel input terminal PI of the register 34.

In the test mode, an input test for checking the state of the analog signal on the signal wiring 4 connected to the input terminal 31 and an output test for outputting a test analog signal to the signal wiring 4 connected to the output terminal 39 are performed. It is possible.

In the case of the input test, first, when the "H" shift signal SFT is supplied, the 8 output from the A / D 33 is output.
The bit digital signal is held in the register 34. Next, when the shift signal SFT is switched from “H” to “L”, the register 34 stores an 8-bit digital signal as an initial value, and an 8-bit shift register to which a control signal TDI is input in series. Become. And
According to the rising timing of the control signal TCK, the control signal TDI is sequentially held in the register 34,
The digital signal held in the register 34 is
The signals are shifted one bit at a time and are sequentially output from the output terminal 35 as the control signal TDO. Therefore, by analyzing the control signal TDO output from the output terminal 35 of the macro cell 30 with the test apparatus 1, the state of the analog signal on the signal wiring 4 connected to the input terminal 31 can be tested.

On the other hand, in the case of the output test, the shift signal SFT
Is set to “L”, in synchronization with the control signal TCK, the control signal TDI is input to the input terminal 32 of the macro cell 30 as
An 8-bit digital signal corresponding to a test analog signal is input. The digital signal is sequentially shifted one bit at a time in accordance with the control signal TCK in the register 34 and applied to the S / P 36. The S / P 36 converts the digital signal into an 8-bit parallel digital signal. Digital signals output in parallel from the S / P 36 are converted to analog signals by the D / A 37, and output to the output terminal 3 via the selector 38.
9 is output as an analog output signal AO. Therefore, a test analog signal is output from the output terminal 39 to the signal wiring 4 at a timing when the output signal of the S / P 36 matches the 8-bit digital signal given as the control signal TDI.

As described above, the macro cell 3 of the present embodiment
0 is an A / D for converting an analog signal to a digital signal
33, and a register 34 for sequentially transferring the digital signal serially as a control signal TDO. Further, it has an S / P 36 for converting a digital signal provided in series as the control signal TDI into parallel, and a D / A 37 for converting the digital signal converted in parallel into an analog signal. Thus, the test analog signal can be output to the signal wiring 4 and the state of the analog signal on the signal wiring 4 can be read. Therefore, it is possible to test the analog signal wiring.

Note that the present invention is not limited to the above embodiment, and various modifications are possible. For example, there are the following modifications. (A) The digital signal in the A / D 33 and the D / A 37 is not limited to 8 bits.

(B) The selector 38 is composed of analog switches 38a and 38b.
Alternatively, a buffer amplifier with a voltage amplification factor of 1 whose operation is controlled may be used.

[0041]

As described above in detail, according to the present invention, analog / digital conversion means for converting an analog signal of an internal circuit or an input / output terminal into a digital signal, and sequentially shifting the digital signal in accordance with a clock signal. And shifting means for outputting. Further, it has digital / analog conversion means for converting a digital signal output from the shift means into an analog signal.
This makes it possible to test the quality of the signal wiring connected to the analog input / output terminal.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a macro cell 30 showing an embodiment of the present invention.

FIG. 2 is a configuration diagram for explaining the concept of a JTAG test system.

FIG. 3 shows a conventional macro cell 2 in the IC 10 in FIG.
FIG.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Test apparatus 2 Printed circuit board 3 Connector 4 Signal wiring 10 IC 11 Internal logic circuit 12-17 Terminal 18 TAP controller 30 Macrocell 31, 32 Input terminal 33 A / D (analog / digital converter) 34 Register 35, 39 Output terminal 36 S / P (serial / parallel converter) 37 D / A (digital / analog converter) 38 selector

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2G132 AA12 AB01 AC15 AK15 AK22 AK23 AL32 AL33 5B048 AA22 CC18 EE07 FF01

Claims (1)

[Claims] 1. A test circuit for testing a signal wiring of a printed circuit board, which is provided between an internal circuit in a device mounted on the printed circuit board and an input / output terminal. In a normal mode, the internal circuit and the input / output terminal are provided. And a boundary scan register connected to sequentially shift and transfer the signal of the internal circuit or the input / output terminal in the test mode, wherein the analog signal of the internal circuit or the input / output terminal is digitally input. Analog / digital conversion means for converting the signal into a signal, a signal from a boundary scan register in the preceding stage and a digital signal converted by the analog / digital conversion means are provided, and when a holding mode is designated by a control signal, The digital signal is held, and when the transfer mode is designated by the control signal, the held data is held. Shift means for sequentially shifting and outputting the digital signal and the signal from the preceding boundary scan register according to a clock signal; serial / parallel conversion means for converting a signal sequentially output from the shift means into parallel data; Digital / analog conversion means for converting the parallel data converted by the serial / parallel conversion means into an analog signal; selecting the analog signal of the internal circuit or the input / output terminal in the normal mode; Selecting means for selecting an analog signal converted by the analog converting means and outputting the selected signal to the input / output terminal or an internal circuit.