KR100419935B1 - Apparatus for detecting delay fault - Google Patents

Abstract

The present invention relates to a delay failure detection apparatus, and in the prior art, it is not a problem even if several TCKs are required to check for static failures, but in order to check for delay failures, it is necessary to observe a pattern input in 1TCK. Therefore, since the test clock TCK is slower than the system clock, there is no meaning of delay failure on the TCK, and thus there is a problem in that the actual delay failure cannot be detected. Accordingly, the present invention outputs a signal (bs-clk) synchronized with the system clock Sys-clk instead of the test clock TCK when the input signal is a command signal Extest used when checking the connection line between the chips. Clock selection means for performing; Performs the operation of the standard TAP Outputs a command signal (Extest) to the clock selecting means and the signal generating means for checking the delay failure, and then when the signal (bs-clk) output from the clock selecting means is input, the boundary cell A test access port (TAP) for outputting a signal UpdateDR for outputting data stored in the apparatus to the outside; After the command signal is input, by providing a device comprising a signal generating means for outputting a signal (UpdateUpdate) in synchronization with the signal (bs-clk) output from the clock selection means (UpdateDR) input from the TAP In addition, it is possible to minimize the cost of delay failure inspection by enabling detection of delay failure as the connection line of the board becomes longer without changing the standard.

Description

Delay failure detection device {APPARATUS FOR DETECTING DELAY FAULT}

The present invention relates to a device for detecting a delay failure in the Institute of Electrical and Electronics Engineers (IEEE) 1149.1 standard, and specifically to detect a delay failure on a connection line in the IEEE 1149.1 standard for testing a board. The present invention relates to a delay failure detection apparatus for outputting data later than a predetermined time by using a system clock to enable the signal in real time.

Recently, due to the development of semiconductor and design technology, the degree of integration of the system to be developed is becoming more difficult, the cost is being increased, and the demand for developing more reliable chips is increasing. In addition, as the system operates at high speeds, the cost of the required test equipment is increasing. In order to reduce the overhead of these tests, efforts are being made to consider testing from the early stage of design, and the trend of design and test is becoming one and the weight of test is getting bigger and more important.

In the related art, the IEEE 1149.1 standard boundary scan structure for testing a board is composed of a test access port (TAP), a TAP controller, instructions, and data registers as shown in FIG. The TAP includes a test data input (TDI), a test data output (TDO), a test clock (TCK), and a test mode selector (TMS) pin, and a test reset (TRST) pin is selectively used. .

In FIG. 1, each of the input pins D1 to D4, EN, and CLK of the chip inputs a signal into the chip through associated boundary scan cells BSC 1 to 13, and the signal generated in the circuit is It is output to the chip external output pins (Q1 to Q4) through the BSC.

The TAP controller transitions to 16 states as shown in FIG. 2, and basically executes a test by inputting commands and data into a register in series, so that the test result can be directly observed.

In the above 16 states, the state of initializing the TAP (Test-Logic-Reset), the standby state (Run-Test-IDLE), the data state (Select-DR-Scan, Capture-DR, Shift-DR, Exit1-DR, Pause-DR, Exit2-DR, Update-DR) and command status (Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, Update-IR). Among the data states, Select-DR-Scan, Exit1-DR, Pause-DR, and Exit2-DR are temporary states, and in the Capture-DR state, the input of test data is loaded in parallel cells. In the Shift-DR state, the value of the test data moves to the next connected cell. In the Update-DR state, the value of the test data is output in parallel. The state of the command is the same as that of the data state, but operates on the instruction register. different.

The command used in the boundary scan includes mandatory commands (BYPASS, EXTEST, SAMPLE / PRELOAD) and optional commands (CLAMP, HIGHZ, RUNBIST, etc.). The mandatory BYPASS command scans the boundary of test data input (TDI). It is a command to send out the test output (TDO) immediately without going through the cell.It reduces the chip pass time of the test data.The EXTEST command is used to check the connection line between chips.The SAMPLE / PRELOAD command This command is used to subtract the value of the leg scan cell to the outside or to load a specific value into the boundary scan cell.

In the EXTEST command, test data is applied through the boundary scan register to check the connection line and the state transition of the boundary scan at that time is first read and decoded after the EXTEST command (Test-Logic-Reset). -→ Run-Test-IDLE-→ Select-DR-Scan-→ Select-IR-Scan-→ Capture-IR-→ Shift-IR-→…-→ Exit1-IR-→ Update-IR) Read through the Boundary Scan register with (Select-DR-Scan-→ Capture-DR-→ Shift-DR-→…-→ Exit1-DR), and then apply the read test pattern through the Update latch. It stores the value of 'transmitted' through the input BSC of the chip to be observed (Update-DR-→ Select-DR-Scan-→ Capture-DR) and outputs the value captured by the input BSC to the TDO through the boundary scan register. (Capture-DR-→ Shift-DR →…-→ Exit1-DR).

The connection line check of the board is performed by applying a test pattern (when an UpdateDR signal is input in the Update-DR state) and sampling (when a CaptureDR signal is input in the Capture-DR state) during the EXTEST command.

That is, as an example showing the application and sampling of the test pattern in the board consisting of two chips as shown in Figure 3, UpdateDR is activated in the dotted line portion as shown in Figure 4 to apply the test pattern, To sample the pattern, CaptureDR is activated in the thick solid line, which takes 2.5 TCKs from UpdateDR to CaptureDR (ie, applying a test pattern through the output BSC and observing it through the input BSC takes a total of 2.5 TCKs). have).

However, in the prior art, even if several TCKs are required to check for static failures, there is no problem, but for checking for delayed failures, it is necessary to observe a pattern input in 1TCK. Since the speed is slow (2.5 TCK is required as described above), there is a problem in that there is no meaning of delay failure on the TCK and a substantial delay failure cannot be detected.

Accordingly, the present invention has been made to solve the problems of the prior art, and provides an apparatus that enables detection of delay failure on a connection line in real time (takes one system clock from test pattern input to observation). There is this.

1 is an IEEE 1149.1 standard boundary scan architecture for testing a conventional board.

2 is a state transition diagram of the tap controller in FIG.

FIG. 3 is an exemplary diagram illustrating a connection line check between chips during a boundary scan EXTEST command in FIG. 1. FIG.

4 is a signal waveform diagram of the tap controller in FIG.

Figure 5 is a block diagram showing a brief configuration of the delay failure detection apparatus of the present invention.

6 is a signal waveform diagram of the signal generating means in FIG.

Explanation of symbols on the main parts of the drawings

10: clock selection means 13: test access port (TAP)

30: signal generating means

The delay delay detection apparatus of the present invention for achieving the above object is a system clock Sys-clk instead of a test clock TCK when the input signal is a command signal Extest used when checking a chip-to-chip connection line. Clock selection means for outputting a signal (bs-clk) in synchronization with the < RTI ID = 0.0 > Performs the operation of the standard TAP Outputs a command signal (Extest) to the clock selecting means and the signal generating means for checking the delay failure, and then when the signal (bs-clk) output from the clock selecting means is input, the boundary cell A test access port (TAP) for outputting a signal UpdateDR for outputting data stored in the apparatus to the outside; When the command signal Extest is not input, the signal UpdateDR output from the access port TAP is received and a signal synchronized with the test clock TDK is output. After the command signal Extest is input, the signal UpdateDR is received. And a signal generating means for outputting a signal SUpdateDR in synchronization with the signal UpdateDR input from the TAP to the signal bs-clk output from the clock selecting means.

Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

FIG. 5 is a block diagram schematically illustrating a configuration of a delay failure detecting apparatus according to the present invention. As shown in FIG. 5, a test is performed when an input signal is a command signal (hereinafter referred to as 'Extest') used when checking a connection line between a chip and a chip. Clock selection means (10) for outputting a signal (bs-clk) in synchronization with the system clock (Sys-clk) instead of the clock (TCK); To perform the operation of the standard TAP to output a command signal (Extest) to the clock selection means 10 and the signal generating means 30 to check the delay failure, and then the signal (bs) output from the clock selection means 10 a test access port (IEEE 1149 TAP 20) for outputting a signal UpdateDR for outputting data stored in a boundary cell to the outside when -clk) is inputted; After the command signal Extest is input, the signal UpdateDR input from the TAP 20 is delayed by 1.5 TCK in synchronization with the signal bs-clk output from the clock selecting means 10, and then delayed. And signal generating means 30 for outputting a signal SUpdateDR.

Referring to the operation of the embodiment according to the present invention configured as described above are as follows.

FIG. 6 is a signal waveform diagram of the signal generating means in FIG. 5. As shown in FIG. 5, the TAP 20 performs an operation of a standard eye TAP in FIG. 5. When the command signal (Extest) is output to the generating means (30), the clock selecting means (10) indicates a command indicating a connection line checking state among the input signals (TMS, TRST, TCK, Sys-clk, ShiftDR, and Extest). When the signal Extest is input, the signal bs-clk converted from the test clock TMS to the system clock Sys-clk is output.

Thereafter, when the signal bs-clk output from the clock selecting means 10 is input, the TAP 20 outputs a signal UpdateDR to externally output data stored in the boundary cell BS. Output to the signal generating means (30).

When the command signal Extest is not input, the signal generating means 10 receives a signal UpdateDR output from the TAP 20 and outputs a signal synchronized with the test clock TDK.

After the command signal Extest is input, when the signal UpdateDR output from the TAP 20 is input, the 1.5 TCK delayed signal SUpdateDR is output in synchronization with the system clock bs-clk.

In addition, the command signal Extest (usually 1 or 0) is not a standard that should be used for all TAP implementations, and it is usually determined that the command signal is decoded by decoding a command signal of 2 bits or more.

Although the invention has been particularly shown and described with reference to the preferred embodiments, those skilled in the art will appreciate that various modifications are possible without departing from the spirit and scope of the invention. Accordingly, the invention is limited only by the claims.

As described above, the delay failure detection apparatus of the present invention enables the detection of delay failures that arise as the connection line of the board becomes longer without changing the standard, thereby minimizing the cost for delay failure check.

Claims (2)

A clock selection means for outputting a signal (bs-clk) in synchronization with the system clock (Sys-clk) instead of the test clock (TCK) when the input signal is a command signal (Extest) used to check the connection line between the chip and the chip; ; Performs the operation of the standard TAP Outputs a command signal (Extest) to the clock selecting means and the signal generating means for checking the delay failure, and then when the signal (bs-clk) output from the clock selecting means is input, the boundary cell A test access port (TAP) for outputting a signal UpdateDR for outputting data stored in the apparatus to the outside; When the command signal Extest is not input, the signal UpdateDR output from the access port TAP is received and a signal synchronized with the test clock TDK is output. After the command signal Extest is input, the signal UpdateDR is received. Signal generation means for outputting a signal SUpdateDR in synchronization with the signal UpdateDR inputted from the TAP to the signal bs-clk outputted from the clock selection means; Delay failure detection device comprising a. The method of claim 1, The signal generating means is a delay failure detection device, characterized in that for outputting the signal (UpdateDR) input from the TAP delayed by 1.5 TCK when the command signal (Extest) is input.