KR100672082B1 - At-speed interconnect test controller for soc with heterogeneous wrapped cores and system on chip comprising the same - Google Patents

Abstract

The present invention relates to a connection delay delay check test controller between cores in a system on chip (SoC) having heterogeneous cores. The present invention relates to a connection delay check controller for checking a connection delay delay between cores in a system on chip including a plurality of cores, the test clock (TCK) provided from an external test device and the system on chip. Receives the system clock (SCK), and generates and outputs a connection line delay failure check test clock (Real_Clock) by combining the test clock and the system clock during the connection delay failure check test. A clock generator for outputting a test clock; A tap controller configured to receive a connection delay test check clock or a test clock from the clock generator to generate a plurality of signals according to the IEEE 1149.1 standard and a Late_Update_DR signal delaying an Update_DR signal among the plurality of signals by 1.5 test clocks; And a signal selector which receives the Update_DR signal and the Late_Update_DR signal, and outputs the Late_Update_DR signal when the connection delay test is checked and outputs the Update_DR signal when a test other than the connection delay test is performed. to provide. In addition, in the system on chip including an interface control unit for changing the signal of the connection delay test check according to the present invention into a signal suitable for the P1500 core, it is possible to test the connection delay test between heterogeneous cores covering IEEE 1149.1 and P1500.

IEEE 1149.1, P1500, Connector, Delay Fault, Tap Controller, Update, Capture

Description

CONNECTION DELAY DETECTION TESTING TEST CONTROLLER AND SYSTEM ON CHIP WITH THE SAME CORE DEVELOPMENT CORRECTION {AT-SPEED INTERCONNECT TEST CONTROLLER FOR SOC WITH HETEROGENEOUS WRAPPED CORES AND SYSTEM ON CHIP COMPRISING THE SAME             

1 is a block diagram showing the structure of a core (or chip) designed for a general IEEE 1149.1 boundary scan.

2 is a transition diagram showing an operation state of a general tap controller according to the IEEE 1149.1 standard.

3 is a diagram illustrating the structure of a standard boundary scan cell.

4 is a waveform diagram illustrating waveforms in a conventional connection line check test.

5 is a diagram illustrating the structure of a boundary scan cell used in a conventional early capture method.

6 is a waveform diagram showing a simulation result of a conventional rate update method.

7 is a configuration diagram of a delay failure check test controller according to an embodiment of the present invention.

FIG. 8 is a waveform diagram illustrating an operation of the delay failure check test controller of FIG. 7.

9 is a block diagram of a system on a chip with heterogeneous cores of IEEE 1149.1 and P1500 according to an embodiment of the present invention.

10 is a waveform diagram illustrating a connection line delay failure check test performed in the system on chip of FIG. 9.

* Explanation of symbols for main parts of drawings *

70: connection delay check test controller 71: clock generator

72: tap control unit 73: signal selection unit

90: System On Chip (SoC)

91: connection delay failure check test controller 92: interface control unit

93: IEEE 1149.1 core 94, 95: P1500 core

BACKGROUND OF THE INVENTION 1. Field of the Invention [0001] The present invention relates to a test controller for link delay failure checking between cores in a system on chip (SoC) having heterogeneous cores. More specifically, the present invention relates to an Eye-Triple-Eee (IEEE). IEEE 1149.1 and IEEE P1500's heterogeneous cores on a system-on-chip can provide test engineers more convenient test methods with minimal hardware changes and full compatibility with IEEE 1149.1. The present invention relates to a delay failure check test controller that can check for dynamic delay failure on a connection line.

As the design technology of system-on-chip, which is a technology that implements a system with multiple functions in one chip, has been developed to the nanometer level, the cost of materials has been reduced, but the test is more difficult and the cost is increased. to be. Testing system-on-chip is not impossible, but as technology advances, complexity increases and testing becomes more difficult, making test cost an important factor in system-on-chip development.

System-on-chip testing is a static failure test that tests for failures such as short circuits or open circuits that occur over time, and a delay failure test that tests for failures such as speed or delay on the core-to-core connection. At-speed test). Here, since the speed or delay failure on the connection line, which is a major defect of the nanometer process, cannot be found by the static failure inspection test alone, the delay failure inspection test as well as the static failure inspection test are urgently required.

For connection test between cores embedded in system-on-chip, board test standard uses core that adopts IEEE 1149.1, standard proposed by IEEE that is standard for board test on all chips, or core on system-on-chip. A core was adopted to adopt IEEE P1500 (hereinafter referred to as P1500), which has been proposed to test and is currently proposed as a standard. The P1500 is a part of the IEEE 1149.1 boundary scan that uses command, data, and bypass registers and receives control signals directly from the outside. As such, since system-on-chip can embed heterogeneous cores adopting IEEE 1149.1 and P1500 together, system-on-chip testing also requires a method of testing a connection line between such heterogeneous cores.

The IEEE 1149.1 is widely used in a non-memory chip currently manufactured by a boundary scan design method selected as a standard. Figure 1 shows one core 10 (or chip) designed for IEEE 1149.1 boundary scan. All input / output pins 11 are connected to internal circuits through boundary scan cells 12 and include test pins and boundary scan control circuits 13 (hereinafter referred to as 'TAP controllers'). The TAP controller 13 operates in 16 states that are transitioned by a TMS (Test Mode Select) signal, and basically executes a test by inputting commands and data into the register 14 in series and directly observes the test result. It executes commands such as EXTEST for checking the connection line, SAMPLE for verifying the normal operation of the internal circuit, and INTEST for testing the chip mounted on the board.

2 is a transition diagram showing 16 operating states of the TAP controller. These 16 states are for initializing the TAP controller (Test-Logic-Reset), Standby (Run-Test-IDLE), Data Status (Select-DR-Scan, Capture-DR, Shift-DR, Exit1-DR). , Pause-DR, Exit2-DR, Update-DR) and command status (Select-IR-Scan, Capture-IR, Shift-IR, Exit1-IR, Pause-IR, Exit2-IR, Update-IR).

Among the data states, Select-DR-Scan, Exit1-DR, Pause-DR, and Exit2-DR are temporary states, and in the Capture-DR state, the core injection force value (a value at the core's normal operation) is in the boundary stan cell. In the shift-DR state, the test data value is moved to the next connected boundary scan cells, and in the update-DR state, the test data values are output in parallel.

The instruction state is the same as the data state above except that it operates on the instruction register. Commands used in boundary scan include mandatory commands (BYPASS, EXTEST, SAMPLE / PRELOAD) and optional commands (CLAMP, HIGHZ, RUNBIST, etc.). It is a command to send out the test output (TDO) immediately, and it shortens the chip pass time of the test data. The EXTEST command is used to check the connection line between the chips. The SAMPLE / PRELOAD command is used for boundary scan. This command is used to pull out a cell value or load a specific value into a boundary scan cell.

3 shows the structure of a standard boundary scan cell. If the data cells of IEEE 1149.1 and the P1500 are in the form of the standard cell of FIG. 3, the data passed through the grant latch (Update Latch: operates the apply latch on the rising edge of the Update_DR signal) 32 on one core is the other core. In the method of receiving through the capture latch (Capture Latch: operates the capture latch on the rising edge of the Clock_DR signal) (31) to test the connection between cores.

Referring to Figures 2 and 3 will be described in more detail the process of performing a connection test between cores through the IEEE 1149.1 as follows.

First, read and decode the EXTEST command, which is used to test the connection line (Test-Logic-Reset-→ Run-Test-IDLE-→ Select-DR-Scan-→ Select-IR-Scan-→ Capture-IR-). → Shift-IR-→…-→ Exit1-IR-→ Update-IR, and test pattern is read through serially boundary scan register (Select-DR-Scan-→ Capture-DR-→ Shift-DR-→…) -→ Exit1-DR). Subsequently, the read test pattern is applied through the application latch 32 and captured by the capture latch 31 of the input boundary scan cell of the chip to observe the value transmitted through the connection line (Update-DR-→ Select-DR-). Scan-→ Capture-DR), and outputs the value captured in the input boundary scan cell to the TDO through the boundary scan register (Capture-DR-Shift-DR--> Exit -DR). At this time, the connection line check between cores may be performed by applying a test pattern (when the Update_DR signal is input in the Update-DR state) and capturing (when the Clock_DR signal is input in the Capture-DR state) during the EXTEST command.

The signal waveform at the time of such a connection test is shown in FIG. As shown in FIG. 4, a 2.5 test clock (TCK) is required from a time point A at which an application occurs in the application latch of the output boundary scan cell to a time point B at the capture latch of the input boundary scan cell. In other words, the input boundary scan cell at the time (B) when the rising edge of the clock_DR signal 42 occurs after the application latch of the output boundary scan cell is operated at the time (A) when the rising edge of the Update_DR signal 41 occurs. It takes 2.5 test clocks for the capture latch to operate. In this connection test, static fault checks such as open circuits and short circuits can be performed regardless of the test clock required, but delay fault checks test for time delays to determine if a delay occurs when a 2.5 test clock is required. It is impossible to check. In particular, since the test clock is generally slower than the system clock, there is no problem of delay failure on the test clock, so there is a problem in that the actual delay failure cannot be tested. In the above description, the problem of the delay failure test is described in IEEE 1149.1. However, since the P1500 adopts a method of performing a partial function of the IEEE 1149.1 boundary scan, the same problem exists in the P1500.

In order to solve the problem of such a delay failure test, conventionally proposed techniques include early capture method (K. Lofstrom, "EARLY CAPTURE FOR BOUNDARY SCAN TIMING MEASUREMENTS", Proceedings of IEEE International) that can be adopted in IEEE 1149.1. Test Conference, pp. 417-422, 1996) and Rate Update Method (S Park and T Kim, "A New IEEE 1149.1 BOUNDARY SCAN DESIGN FOR THE DETECTION OF DELAY DEFECTS", Design, Automation and Test in Europe Conference , pp. 458-462, 2000), and in the P1500, the enhanced P1500 wrapper approach (HJVermaak and HG Kerkhoff, "Enhanced P1500 Compliant Wrapper suitable for Delay Fault), which seeks to solve problems through wrapper cells. Testing of Embedded Cores ", Proceedings of the Eighth IEEE European Test Workshop, 2003).

5 shows the structure of the boundary scan cell used in the conventional early capture method. In the conventional early capture method, as shown in FIG. 5, the structure of the boundary scan cell of the core or chip, which is previously covered, must be changed. That is, when compared to the structure of the standard boundary scan cell shown in FIG. 3, the boundary scan cell used in the early capture method should be changed to a structure in which a latch 51 for early capture is further added, and an input line is added accordingly. Should be. Therefore, in a chip or core having hundreds of pins, it is practically impossible to change all the boundary scan cell structures and provide additional input lines.

6 is a waveform diagram showing a simulation result of a conventional rate update method. Referring to FIG. 6, a test mode select (TMS) 61 is a signal in which a test engineer directly inputs data to change a state of a TAP controller, and data is recognized on a rising edge of the TCK (test clock) 62. The conventional rate update scheme generates BS_Clk 63 to perform the role of TCK 62 instead. At this time, the rising edge of SYS_CLK (system clock) 64 is generated several times in the part where one rising edge of TCK 62 is to be generated, and the TMS 61 is recognized whenever the rising of SYS_CLK 64 occurs. The state of the TAP controller will change. Not only is this approach completely incompatible with IEEE 1149.1, but it also requires test engineers to be familiar with the new TMS test patterns for delayed fault check tests, and the test clocks and system clocks vary patterns, which complicates testing. There is a problem.

In addition, although not shown, the conventional and improved P1500 wrapper method merely suggests the structure of the boundary scan cell that enhances the P1500 wrapper functionality to enable delayed failure checking tests. There is a problem in that the test method in a system-on-chip environment does not appear in detail. The improved P1500 wrapper is a logic dedicated to the P1500 wrapper, which makes it nearly impossible to test on a system-on-chip with multiple cores.

The present invention has been made to solve the above-described problems of the prior art, the object of the system on a chip in the connection delay delay check test between different types of cores from the update (Update) to the capture (Capture) operation 1 By providing a system clock, a link delay fault check controller can be used to test the link delay fault check.                         

In addition, another object of the present invention, a failure check controller for use in heterogeneous cores capable of performing static failure test and delay failure check test between different types of cores on a system on a chip and a system having the same To provide an on-chip.

As a technical configuration for achieving the above technical problem, the present invention provides a connection line delay failure check controller for checking and testing the connection line delay failure between the core in a system on a chip comprising a plurality of cores,

A test clock (TCK) provided from an external test device and a system clock (SCK) of the system-on-chip are input, and the test clock and the system clock are combined to combine the test clock and the system clock during a connection delay check test clock. A clock generator which generates and outputs (Real_Clock) and outputs the test clock when a test other than the connection delay delay check test is performed; A tap controller configured to receive a connection delay test check clock or a test clock from the clock generator to generate a plurality of signals according to the IEEE 1149.1 standard and a Late_Update_DR signal delaying an Update_DR signal among the plurality of signals by 1.5 test clocks; And a signal selector configured to receive the Update_DR signal and the Late_Update_DR signal, and to output the Late_Update_DR signal during a connection delay check test and to output the Update_DR signal when a test other than the connection delay check test is performed. To provide.

Here, the connection delay test clock (Real_Clock) is a signal provided as a test clock during the connection delay check test, the output form follows the test clock (TCK) and the two clocks rising in the Capture_DR state It is desirable to keep the value of 1 and then follow the test clock TCK again on the falling edge of the next test clock TCK.

In addition, the clock generation unit and the signal selection unit preferably receive a delay failure check test determination signal (I.EN.) for determining whether a connection line delay failure check test is in progress. Accordingly, the clock generator selectively outputs a general test clock or a connection line delay failure check test clock (Real_Clock), and the signal selector selectively outputs an Update_DR signal or a Late_Update_DR signal generated by the tap controller.

In still another aspect of the present invention, there is provided a system-on-chip including a plurality of heterogeneous cores.

The above-described connection line delay failure check test controller; An interface controller which receives a signal according to IEEE 1149.1 outputted from the connection line delay failure check test controller and converts the signal into a signal used in the P1500; A plurality of IEEE 1149.1 cores receiving a signal according to IEEE 1149.1 from the connection line delay failure check test controller; And a plurality of P1500 cores for receiving signals from the interface controller.

Since the tap controller is included in the core according to IEEE 1149.1, the connection delay failure check test controller may be included in the IEEE 1149.1 core. In this case, the interface control unit will have a connection type that receives an input signal from the connection delay check test controller included in the IEEE 1149.1 core.

The signal generated by the interface controller is a signal that can be used for the test of the P1500, and includes a WRCK, WRSTN, ShiftWR, CaptureWR, UpdateWR, and SelectWIR signal. The double WRCK signal is a signal that outputs a test clock (TCK) or a connection delay test check clock (Real_Clock) generated by the connection delay check test controller as it is, and the WRSTN signal is a reset signal of the connection delay check test controller. The signal is output as it is, the ShiftWR signal is a signal that combines the Shift_IR signal and the Shift_DR signal output from the connection line delay failure check test controller through the OR gate. The CaptureWR signal is a signal generated by combining the Clock_IR signal, the Shift_IR, Clock_DR signal, and the Shift_DR signal output from the connection line delay failure check test controller. More specifically, the CaptureWR signal generates a rising edge when the Shift_IR signal goes from '1' to '0' (falling edge) when the Clock_IR signal is 0, and sets the value of '1' during one test clock. After holding, falling edge occurs. In addition, the CaptureWR signal generates a rising edge when the Shift_DR signal goes from '1' to '0' (falling edge) when the Clock_DR signal is '0' and generates a value of '1' during one test clock. After holding, falling edge occurs. As a result, the condition that the capturing operation, which is a condition of the CaptureWR signal required by the P1500, should be '1' and other operations, must be '0'. The UpdateWR signal is a signal obtained by combining the Update_IR signal and the Update_DR signal or the Update_IR signal and the Late_Update_DR signal output from the connection line delay failure check test controller through an OR gate, and the SelectWIR signal is the same as the Select_R signal output from the connection delay check failure controller. Output signal.

Hereinafter, the configuration and operation of a connection line delay failure check test controller according to the present invention will be described in more detail with reference to the accompanying drawings. In the following description, the connection delay failure check test controller may be simply referred to as a delay failure check test controller.

7 is a configuration diagram of a connection line delay failure check test controller according to an embodiment of the present invention. Referring to FIG. 7, a delay failure check test controller 70 according to an exemplary embodiment of the present invention may include a clock generator 71, a tap (TAP) controller 72, and a signal selector 73. It is composed. Hereinafter, each component included in the delay failure check test controller 70 according to an embodiment of the present invention will be described in more detail.

The clock generator 71 serves to provide a test clock to the tap controller 72. During a general failure check test, the clock generator 71 taps a general test clock (TCK) input from a test device as it is. When the delay test check connection line, the system clock (SCK) and the test clock (TCK) is combined to generate a delay check clock (Real_Clock) to the tap controller 72. do. This will be described in more detail as follows.

The clock generator 71 receives a test clock TCK, a system clock SCK, and a delay failure check test determination signal I.EN. The delay failure check test determination signal I.EN. may be provided by the command decoder as a signal for determining whether a connection delay delay check test between cores in a system on chip is currently in progress. For example, the delay failure check test determination signal (I.EN.) outputs '1' when performing the delay failure check test, and other static failure check tests (eg, EXTEST, INTEST, In case of BYPASS mode, '0' can be output. When the value of the delay failure check test determination signal I.EN. is 0 (when the delay failure check test is not in progress), the clock generator 71 keeps the input test clock TCK as it is. When the value of the delay failure check test determination signal I.EN. is '1' (when performing the delay failure check test), the clock generator 71 generates a test clock TCK and a system clock. The clock for the delay failure check test generated by combining SCK) is output.

The delay failure check test clock Real_Clock is a general test clock when the delay failure check test is not in progress (for example, when the value of the delay failure check test determination signal I.EN. is 0). (TCK) is output as is, and when the delay fault check test is in progress (for example, when the value of the delay fault check test discrimination signal (I.EN.) is '1'), the system clock starts from the point where it enters the Capture_DR state. A clock that follows the two rising edges of (SCK). This may be more clearly understood with reference to the waveform diagram shown in FIG. 8. FIG. 8 is a waveform diagram showing waveforms of signals in a state in which a delay failure check test is in progress according to the present invention. The clock for delay failure check test Real_Clock 83 is input to a clock generator 71 of FIG. 7. Follows the waveform of the general test clock (TCK, 81) is followed by the form of the system clock (SCK, 82) in the Capture_DR state. Then, after two rising edges r821 and r822 of the system clock SCK are maintained, the value is maintained at 1, and the test clocks TK and 82 are again followed by the falling edge d81 of the next test clock TCK and 82. Print the value.

The tap controller 72 receives a clock for the delay failure check test generated by the clock generator 71 to a general tap controller that conforms to the IEEE 1149.1 standard, and uses a new Update_DR used for a connection delay check. Added a function to generate a signal (hereinafter, referred to as a Late_Update_DR signal).

The tap control unit 72 receives a test mode select (TMS) signal for selecting a test mode from a test facility and a test reset signal (TRST) for test initialization, and a signal generated by the clock generator 71 as a test clock. Accept. As described above, the signal generated by the clock generator 71 is a test clock of a test fixture when the connection delay test is not in progress, and a test clock of the test fixture when the connection delay test is not in progress. This is a clock for delay failure check test (Real_Clock) generated by combining the system clock.

The tap controller 72 generates and outputs signals such as Shift_DR, Clock_DR, Update_DR, Shift_IR, Clock_IR, and Update_IR, which are signals according to the IEEE 1149.1 standard, and generates a Late_Update_DR signal which delays Update_DR by 1.5 test clocks. As described in the prior art, in the standard of IEEE 1149.1, the Update_DR signal generates a rising edge on the falling edge of the test clock in the Update_DR state, and an update operation of the boundary scan cell occurs on the rising edge of the Update_DR signal. In contrast, the Late_Update_DR signal delays the Update_DR signal by 1.5 test clocks, so that the rising edge is generated on the second rising edge of the test clock after the Update_DR signal is generated. When the delay test for delay connection is in progress, the Late_Update_DR signal is generated according to the delay fault check test clock (Real_Clock) generated by the clock generator, and particularly, the part that follows the system clock in the delay fault check test clock (Real_Clock). The rising edge of the Late_Update_DR signal is generated at the rising edge of. That is, the rising edge of the Late_Update_DR signal occurs when the Capture_DR state starts. This can be seen in more detail with reference to the waveform diagram of FIG. 8.

 In the general Update_DR signal, a rising edge is generated at the portion indicated by 'C' of FIG. 8. On the other hand, since the Late_Update_DR signal delays the Update_DR signal by 1.5 test clocks, the rising edge is generated on the second rising edge after the falling edge of the test clock in which the Update_DR signal is generated (that is, the boundary scan cell is updated.) However, when the delay connection check delay test is in progress, the Late_Update_DR signal 84 operates because of the delay check clock (Real_Clock), so a rising edge occurs at the point 'D' where the Capture_DR state starts. Update operation of the boundary scan cell occurs).

Meanwhile, since the clock_DR signal maintains 1 and follows the test clock in the Capture_DR state or the Shift_DR state, one falling edge and one rising edge are generated in the Capture_DR state as shown in FIG. do. At this time, the capture operation of the boundary scan cell of core occurs at the rising edge ('E') of the Clock_DR signal 85. In the Capture_DR state, the clock for delay failure check test (Real_Clock) follows the system clock. Therefore, both an update operation (D) and a capture operation (E) of the boundary scan cell may be performed within one system clock. As described above, according to the present invention, both an update operation (D) and a capture operation (E) of a boundary scan cell may occur within a system clock, so a delay failure that may occur in a connection line may occur. You can check

In addition, the delay failure check test apparatus according to the present invention generates a delay failure check test clock (Real_Clk) such that two system clock rising edges are generated in the Capture_DR state in order to take one system clock from the Update_DR signal to the Clock_DR signal. However, as shown in FIG. 8, after the second rising edge of the system clock occurs on the delay failure check test clock (Real_Clk, 83), the output signal is output as '1' until the falling edge of the next test clock occurs. TMS) recognition is the same as when tested with a typical test clock (TCK), allowing the user performing the test to perform the link delay fault check test in the same way as any other test of IEEE 1149.1. have.

The Select_R signal among the signals generated by the tap controller 72 is a signal indicating whether the current tap controller is in a data state or a command state. For example, when the state of the tap control unit is a command state, the Select_R signal may output '1', and when the state of the tap control unit is a data state, the Select_R signal may output '0'.

The signal selector 73 receives an Update_DR signal and a Late_Update_DR signal among the signals generated by the tap control unit 72, outputs an Update_DR signal when performing a general static failure test, and performs a delay test for connection delay. Outputs a Late_Update_DR signal. In order to discriminate between the static failure check test and the connecting line delay failure check test, the delay selection check test determination signal I.EN. The delay failure check test determination signal I.EN. is the same signal as the delay failure check test determination signal I.EN. which is input to the clock generation section 71 described above. For example, when the value of the delay failure check test determination signal I.EN. is 0 (when the delay failure check test is not in progress), the signal selector 73 outputs an Update_DR signal. When the value of the delay failure check test determination signal I.EN. is '1' (when performing the delay failure check test), the signal selector 73 outputs a Late_Update_DR signal. Therefore, by the Update_DR signal and the Late_Update_DR signal selectively output by the signal selecting unit 73, the user can selectively perform the static failure test and the connection line delay failure check test without additional manipulation.

As described above, according to the delay failure check test controller according to the present invention, since an update operation and a capture operation of boundary scan cells can occur within one system clock, a delay that can occur in a connection line can occur. Enable to check for faults.

In addition, according to the present invention, the recognition of the test mode (TMS) is the same as when tested with the general test clock (TCK), so that the user performing the test connection delay in the same way as the other test method of IEEE 1149.1 The ability to perform troubleshooting checks allows the user to avoid having to learn a separate test pattern.

In addition, the delay failure check test controller according to the present invention is fully compatible with the IEEE 1149.1 standard, and thus, there is an advantage in that a connection delay delay check test between chips is performed on a board conforming to the IEEE 1149.1 standard.

In addition, in case of a system-on-chip in which cores complying with the IEEE 1149.1 standard and cores covered by the P1500 are provided with a separate interface control unit capable of providing a signal to the wrapper of the P1500, connection delay delay between heterogeneous cores of the system-on-chip There is an advantage to performing inspection tests. In the following, the delay failure check test in a system on chip having heterogeneous cores of IEEE 1149.1 and P1500 will be described in detail.

9 is a block diagram of a system on a chip with heterogeneous cores of IEEE 1149.1 and P1500 according to an embodiment of the present invention. The system-on-chip 90 according to one embodiment of the present invention is a signal to one IEEE 1149.1 core 93, two P1500 cores 94 and 95, a connection delay failure check test controller 91, and a wrapper of the P1500. It is configured to include a separate interface control unit 92 that can provide. The system on chip 90 illustrated in FIG. 9 is shown to include one IEEE 1149.1 core 93 and two P1500 cores 94 and 95, but the number of cores does not limit the present invention.

The connection line delay failure check test controller 91 is a connection line delay failure check test controller shown in FIG. 7 described above. Since the configuration and operation of the connection delay failure check test controller 91 are as described with reference to FIG. 7, a detailed description thereof will be omitted.

The interface control unit 92 is for applying a signal necessary for a test to the boundary scan cell of the cores 94 and 95 covered with P1500. The interface control unit 92 receives the signals of the connection line delay failure check test controller 91 according to the IEEE 1149.1 standard. It performs the function of converting and providing the signals that can be used for the cores 94 and 95 covered by the P1500. According to P1500, a control unit such as a tap controller of IEEE 1149.1 does not exist. In the present invention, the signal output from the connection line delay failure check test controller 91 according to the IEEE 1149.1 standard is converted into a signal suitable for P1500.

The interface control unit 92 receives all signals generated by the connection line delay failure check test controller and generates and outputs a signal suitable for the P1500. Signals generated by the interface controller 92 include WRCK, WRSTN, ShiftWR, CaptureWR, UpdateWR, and SelectWIR as signals used by the P1500.

The WRCK signal outputs the test clock generated by the connection delay check device 91 as it is. As described in FIG. 7, the test clock is a test clock (TCK) input from an external test device when the connection delay failure check test is not performed, and a test clock (TCK) when the connection delay failure check test is in progress. And a test clock Real_Clk for connection delay delay check test generated by combining the system clock SCK, which is a clock generated by the clock generator (71 of FIG. 7) in the connection delay check failure test controller 91. FIG.

The WRSTN signal is a signal for resetting all tests, and is a signal obtained by outputting the reset signal of the connection line delay failure check test controller 91 as it is.

The ShiftWR signal is a signal obtained by combining the Shift_IR signal and the Shift_DR signal output from the tap control unit (72 of FIG. 7) in the connection line delay failure check test controller 91 through an OR gate.

The CaptureWR signal is a signal generated by combining the Clock_IR signal, the Shift_IR, Clock_DR signal, and the Shift_DR signal outputted from the tap control unit (72 in FIG. 7) in the connection delay tester 91. More specifically, the CaptureWR signal generates a rising edge when the Shift_IR signal goes from '1' to '0' (falling edge) when the Clock_IR signal is 0, and sets the value of '1' during one test clock. When the falling edge occurs after holding, or when the Clock_DR signal is '0', the rising edge occurs when the Shift_DR signal goes from '1' to '0' (falling edge). It is a signal that a falling edge occurs after maintaining the value of 1 '.

The UpdateWR signal is a signal obtained by combining the Update_IR signal and the Update_DR signal outputted from the connection line delay failure check test controller 91 through the OR gate. As described above with reference to FIG. 7, the Update_DR signal is a general Update_DR signal that is a signal at which a rising edge occurs on the falling edge of the test clock in the Update_DR state when the connection delay test is not performed. In case of progress, the Late_Update_DR signal is obtained by delaying the Update_DR signal by 1.5 test clocks when the connection line delay failure check test is not performed.

The SelectWIR signal is a signal obtained by outputting the Select_R signal output from the connection line delay failure check test controller 91 as it is.

The cores 94 and 95 covered with P1500 can perform various core tests as in IEEE 1149.1 using the WRCK, WRSTN, ShiftWR, CaptureWR, UpdateWR, and SelectWIR signals described above.

The core 93 covered by the IEEE 1149.1 may receive a signal from the connection line delay failure check test controller 91 outside the core and perform a test, but according to the IEEE 1149.1 standard, the core controller includes a tap controller therein. Accordingly, in the core 93 of the present invention, the core 93 covered by the IEEE 1149.1 may be included in the core as it is. In view of the above, in another embodiment of the present invention, the interface control unit described above does not provide a signal generated by the connection line delay failure check test controller inside the core covered by IEEE 1149.1 without providing a separate connection line delay failure check test controller outside the core. It may also be possible to generate a signal used in the P1500 by transferring the signal to P1500. Further, in another embodiment in the form of a system on a chip consisting of cores covered with P1500 without including the cores covered by IEEE 1149.1, the interface delay failure check test controller 91 and interface controller 92 shown in FIG. ) Can be used to perform a link delay fault check test between the P1500 cores.

A connection line delay failure check test performed in a system on chip according to the present invention having such a structure will be described with reference to the configuration diagram of FIG. 9 and the waveform diagram of FIG. 10.

First, as shown in FIG. 9, the connection delay failure check test between the boundary scan cell 932 of the first core 93 covered by IEEE 1149.1 and the boundary scan cell 942 of the second core 94 covered with P1500 is described. Explain.

During normal testing, I.EN. indicates that a connection delay failure check test is performed. When the signal 103 outputs a value of '1' (point 'I' in FIG. 10), the connection delay delay check test is executed. Accordingly, the connection delay check test control unit performs the test using the connection delay check test clock (Real_Clock) as a test clock. As described above with reference to FIG. 7, the connection delay test clock (Real_Clock) is a test clock used in the connection delay test and checks the two rising edges of the system clock (SCK) from the time of entering the Capture_DR state. The clock signal maintains a value of 1 after two rising edges of the clock SCK and outputs the value along the test clock again on the falling edge of the next test clock. In the present embodiment, the connection delay test clock clock Real_Clock 104 outputs the general test clock TCK 101 as it is, as shown in FIG. 10. In the Capture_DR state 111, two system clocks SCK 102 ) To generate a rising edge.

The boundary scan cell 932 of the first core 93 receives the Update_DR signal from the connection line delay failure check test control unit 931 in the core to operate the application latch to apply test data. The Update_DR signal is a signal in which a rising edge occurs on the falling edge of the test clock in Update_DR state 110 when the connection delay failure check test is not performed (i.e., when the I.EN.signal 103 is zero) (FIG. 10). Reference numeral '107a'). However, when the delay test check connection is performed (that is, when the I.EN.signal 103 is 1), the test delay is 1.5 times, so when the Update_DR signal occurs when the delay test check is not performed. Thereafter, a delayed Update_DR (Late_Update_DR) signal is generated at the rising edge of the second test clock (see reference numeral 107 of FIG. 10). Therefore, the update operation occurs in the boundary scan cell 932 of the first core at a time indicated by “U1” in FIG. 10.

The boundary of the second core 94 connected to the boundary scan cell 932 of the first core 93 after test data is updated at 'U1' in the boundary scan cell 932 of the first core 93. The scan cell 942 captures the applied test data. The clock_IR signal and the Clock_DR signal generated by the connection line delay failure check test controller 91 of FIG. 9 are combined by the interface controller 92 and output as the CaptureWR signal 108 which is one of the test signals of the P1500. According to P1500, a capture operation is performed on the rising edge of the test clock Wrck 105 while the CaptureWR signal is 1. Accordingly, a capture operation is performed at the boundary scan cell 942 of the second core 94 at the time indicated by 'C2'.

That is, an update operation is performed at the 'U1' point in the boundary scan cell 932 of the first core 93, and at the 'C2' point in the boundary scan cell 942 of the second core 94 connected thereto. Since a capture operation is performed at the same time, an update operation and a capture operation between different heterogeneous cores are performed within one system clock. As described above, according to the present invention, an update and a capture operation may be performed within one system clock even when testing a connection delay failure check between different heterogeneous cores.

The present invention can be applied not only to the connection delay failure check test between heterogeneous cores described above, but also to the connection delay failure check test between homogeneous cores.

In the connection line delay failure check test between the boundary scan cell 943 of the second core 94 covered with P1500 of FIG. 9 and the boundary scan cell 953 of the third core 95 covered with P1500, the interface control unit 92 Update occurs in the boundary scan cell 943 of the second core 94 at a time point 'U2' by the UpdateWR signal 109 generated at the second core 94 and the boundary scan cell 953 of the third core 95. In this case, a capture occurs at a 'C2' time point of the CaptureWR signal 108 so that update and capture operations can be performed within a system clock. Similarly, during the connection delay failure check test between cores covered by IEEE 1149.1, an update occurs at the time point 'U1' by the Late_Update_DR signal 107 generated by the connection delay failure check test unit and the Capture_DR signal 106 is performed. By the capture occurs at the 'C1' time point (Update) and capture (Capture) operation can be performed within a system clock.

As described above, according to the present invention, the update operation and the capture operation can be performed within one system clock to accurately determine whether a delay occurs between cores when testing connection delay between heterogeneous or homogeneous cores. You can test the test.

The present invention is not limited by the above-described embodiment and the accompanying drawings, but is intended to be limited by the appended claims, and various forms of substitution, modification, and within the scope not departing from the technical spirit of the present invention described in the claims. It will be apparent to those skilled in the art that changes are possible.

As described in detail above, according to the present invention, it is possible to substantially take one system clock from an update operation to a capture operation during a test of delay connection failure between system-on-chip heterogeneous or homogeneous cores. This test has the effect of a possible connection delay fault check test.

In addition, according to the present invention, it is possible to reduce the test cost by changing only the tap controller on the chip and the core tap controller consisting of IEEE 1149.1 when configuring a circuit for the connection delay failure check test, and is fully compatible with IEEE 1149.1 There is an effect that can be easily performed a variety of tests on the system on a chip (SoC) without the user to perform a separate test pattern.

Claims (11)

delete A connection line delay failure check controller for checking and checking a connection line delay failure between cores in a system on chip including a plurality of cores, A test clock (TCK) provided from an external test device and a system clock (SCK) of the system-on-chip are input, and the test clock and the system clock are combined to combine the test clock and the system clock during a connection delay check test clock. A clock generator which generates and outputs (Real_Clock) and outputs the test clock when a test other than the connection delay delay check test is performed; A tap controller configured to receive a connection delay test check clock or a test clock from the clock generator to generate a plurality of signals according to the IEEE 1149.1 standard and a Late_Update_DR signal delaying an Update_DR signal among the plurality of signals by 1.5 test clocks; And The signal receiving unit receives the Update_DR signal and the Late_Update_DR signal, and outputs the Late_Update_DR signal when the connection delay test is checked and outputs the Update_DR signal when a test other than the connection delay test is performed. The connection delay test clock (Real_Clock) follows the test clock (TCK) and outputs two system clock rising edges in the Capture_DR state, and then maintains a value of 1 and then descends the next test clock (TCK). Connection delay failure check test controller, following the test clock (TCK) again at the edge. The method of claim 2, And the clock generator and the signal selector receive a delay failure check test determination signal (I.EN.) for determining whether a connection delay delay check test is in progress. In a system on a chip comprising a plurality of heterogeneous cores, Connecting line delay failure check test controller according to claim 2; An interface controller which receives a signal according to IEEE 1149.1 outputted from the connection line delay failure check test controller and converts the signal into a signal used in the P1500; A plurality of IEEE 1149.1 cores receiving a signal according to IEEE 1149.1 from the connection line delay failure check test controller; And System on a chip comprising a plurality of P1500 core to receive a signal from the interface control unit. The method of claim 4, wherein The connection delay delay check test controller is included in the IEEE 1149.1 core. The method of claim 4, wherein Among the signals generated by the interface controller, the WRCK signal is a system on chip, which is a signal outputting a test clock (TCK) or a connection line delay failure check test clock (Real_Clock) generated by the connection line delay failure check test controller as it is. . The method of claim 4, wherein The WRSTN signal of the signals generated by the interface controller is a signal outputting the reset signal of the connection delay delay check test controller as it is. The method of claim 4, wherein The shift-WR signal of the signals generated by the interface controller is a signal on which the shift_ir signal and the shift_dr signal output from the connection line delay failure check test controller are combined through an OR gate. The method of claim 4, wherein Among the signals generated by the interface control unit, the CaptureWR signal has a rising edge at the falling edge of the Shift_IR signal when the Clock_IR signal output from the connection delay check test controller is 0 and a value of '1' during one test clock. When the falling edge is generated or the clock_DR signal is '0', the rising edge is generated at the falling edge of the Shift_DR signal, and the falling edge is generated after maintaining the value of '1' for one test clock. A system on chip, characterized in that the signal. The method of claim 4, wherein The UpdateWR signal among the signals generated by the interface controller is a signal on which the Update_IR signal and the Update_DR signal or the Update_IR signal and the Late_Update_DR signal output from the connection delay delay check test controller are combined through an OR gate. The method of claim 4, wherein The SelectWIR signal among the signals generated by the interface controller is a signal for outputting the Select_R signal output from the connection delay delay check test controller as it is.

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