JP3594340B2 - Testing equipment - Google Patents

Description

[0001]
[Industrial applications]
The present invention relates to a test apparatus, and more particularly, to a test that can execute both an external scan method in which a clock signal is supplied from an external circuit to perform an external scan and an internal control scan method (JTAG scan method) based on IEEE. It concerns the device.
[0002]
[Prior art]
Generally, in a test of a semiconductor integrated circuit or the like, the number of conceivable states increases with an increase in the scale of the logic circuit, and control of the logic circuit and the like cannot follow the increased number of states, so that the test cannot be performed.
[0003]
In particular, in a semiconductor integrated circuit including a logic circuit which is limited in the number of input / output terminals and in which direct observation of the internal state is practically impossible due to its complicated structure, the control of the logic circuit and the like are limited by the number of states. Therefore, the test of the semiconductor integrated circuit has become more difficult.
[0004]
Therefore, conventionally, a test circuit in which sequential circuits are combined in a pseudo manner to form a circuit has been used in this type of test apparatus.
Some of such test apparatuses use, for example, a JTAG (ie, Joint Test Action Group) test port, which is an internal control scan method based on IEEE, for testing an IC chip mounted on a board.
[0005]
In accordance with the JTAG method, the Institute of Electrical and Electronics Engineers, INC. And currently defined as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary Scan Architecture.
[0006]
An overview of the development, definition, and application of this JTAG is provided in the Test Access Port and Boundary Scan Architecture published by IEEE Computer Society Press, Los Alamitos, California (1990), author C.A. M. Maunder and R.A. E. FIG. Available at Tulloss
Have been.
[0007]
FIG. 8 shows an example of a test apparatus for a semiconductor integrated circuit employing such a JTAG scan method.
In FIG. 8, control signals generation circuits 50a to 52a including an instruction register (IR) and a scan A / B clock generation circuit for generating a two-phase clock which is a scan A / B phase are provided inside the LSIs 50 to 52, Scanning is performed by setting the states of control circuits inside the LSIs 50 to 52 according to a sequence signal from an external circuit.
[0008]
In FIG. 8, ACK is an input terminal for the A clock signal, and BCK is an input terminal for the B clock signal.
The scan input terminal SI is an input terminal for inputting a scan signal, and the scan output terminal SO is an output terminal for outputting a scan signal.
[0009]
Further, a chain select CS is a chain select input terminal for selecting a range to be connected in the same scan chain, and a test mode selection signal input terminal TM is an input terminal for a signal for selecting a test mode.
[0010]
In order to test the LSIs 50 to 52 using the JTAG scan method, to set the flip-flops FF and the like in the LSIs 50 to 52 or the flip-flop FF mounted on the printed wiring board 53 to an arbitrary value, the processing shown in the flowchart of FIG. Need to do.
[0011]
In other words, in the flowchart shown in FIG. 9, in order to activate a chain connection of an instruction register scan system in which FF groups (referred to as Instruction Registers, IR registers) for setting instructions for performing a test are connected in series. First, the scan mode and the tap TAP controller, which is a JTAG test system control circuit, are set (ST100).
[0012]
After the scan mode is set and the tap TAP controller is set, the instruction register IR code is set and input from the test clock terminal TCK to the scan A / B phase clock terminal in order to perform the scan operation of the instruction register IR. A voltage is applied (ST101).
[0013]
After setting the IR code and applying it from the test clock terminal TCK to the scan A / B clock terminal, the scan mode and the tap TAP controller are set to activate the scan chain connection (ST102).
[0014]
After the setting of the scan mode and the setting of the tap TAP controller, in order to perform the scanning operation, the setting of the scan-in value to be input to the scan input terminal and the input voltage from the test clock terminal TCK to the scan A / B clock terminal are performed. It is applied (ST101).
[0015]
When the scan-in value setting signal input to the scan input terminal and the input voltage from the test clock terminal TCK to the scan A / B clock terminal are applied, the processing of the above-described flowchart ends.
[0016]
On the other hand, in a test apparatus that performs a test by employing the external scan method shown in FIG. 10, a signal for scanning is supplied from an external circuit, and is mounted inside the LSIs 54 to 56 and on the printed wiring board board 57. An arbitrary value is set to the flip-flop FF or the like.
[0017]
In FIG. 10, a timing clock input terminal TCK indicates a timing clock input terminal, and a timing signal input terminal TMS indicates a timing signal input terminal.
[0018]
The scan signal input terminal SI is an input terminal for inputting a scan signal, and the scan signal output terminal SO is an output terminal for outputting a scan signal.
The test data output terminal TRST is a test data output terminal, and the test mode signal input terminal TM is a test mode signal input terminal.
[0019]
In the test apparatus of FIG. 10, when setting any value to the LSIs 54 to 56, the flip-flop FF mounted on the board, or the like, it is necessary to perform processing according to the flowchart of FIG.
[0020]
That is, in the flow chart shown in FIG. 11, in order to activate the chain connection of the instruction register IR scan, first, the scan mode is set and the chain select is set (ST110).
[0021]
After the setting of the scan mode and the setting of the loop select, an input voltage is applied from the test clock TCK to the scan A / B clock terminal in order to perform a scan operation (ST101).
[0022]
After setting the scan-in value and applying the input voltage to the scan A / B clock signal terminal from the test clock TCK to the scan A / B clock terminal, the processing of the above-described flowchart ends.
[0023]
Thus, for example, it is possible to set the LSIs 54 to 56 and the flip-flop FF mounted on the board to an arbitrary value, and when the values are not the set values, it is possible to test for an abnormality in the LSIs 54 to 56.
[0024]
Examples of the test apparatus described above include, for example, JP-A-5-164826 and JP-A-5-180911, which use the internal control method, and those using the external scan method. And JP-A-64-68843 or JP-A-61-155874.
[0025]
[Problems to be solved by the invention]
However, in the test apparatus described above, the LSI, the printed wiring board, and the entire system are tested at the time of system development or the like. When the test methods are different, the test of the LSI, the printed wiring board, and the entire system are performed. The test cannot be performed by one device.
[0026]
For example, when the LSI test is performed by the internal control (JTAG) method and the total test of the printed wiring board and the system is performed by the external scan method, it is difficult to perform these tests with one test apparatus. become.
[0027]
Therefore, the present invention has been made in view of these problems, and when a system is developed, the test method is switched to an external scan method or a JTAG method. It is another object of the present invention to provide a test apparatus capable of testing a printed wiring board and an entire system.
[0028]
[Means for Solving the Problems]
The present invention employs the following means in order to solve the above problems.
(1) Summary of the first invention
According to the first aspect of the present invention, a target electronic component is diagnosed and tested using both an external scan method in which a clock signal is supplied from an external circuit to perform an external scan and a JTAG scan method which is an internal control scan method conforming to IEEE. For this reason, a switching circuit is provided for switching to both the external scan and the JTAG scan for use.
[0029]
When the external scanning method is selected by this switching circuit, in order to input a clock signal from an external device to diagnose or test the target electronic component, for example, the target electronic component is set as a set of points and the target electronic component is set as a set of points. Are scanned in, for example, the horizontal or vertical direction to diagnose and test the target electronic component.
[0030]
When the switching circuit selects the JTAG scan system conforming to IEEE, in order to diagnose the target electronic component based on the internal control signal input from the internal control circuit, for example, the target electronic component is set as a set of points and the target electronic component is set as a target. The electronic component is scanned, for example, in the horizontal or vertical direction to diagnose and test the target electronic component.
[0031]
This tester is used by switching between the external scan method and the internal control (JTAG) scan method using a switching circuit, so that it can be used for both a system that scans with the external scan method and a system that scans with the JTAG scan method. can do.
[0032]
This allows one test apparatus to diagnose or test target electronic components used in a system that scans using the external scan method or a system that scans using the JTAG scan method. Since it is possible to switch between the scan method and the JTAG scan method, it is convenient to develop a system using a different scan method.
[0033]
The JTAG method is a standard based on the Institute of Electrical and Electronics Engineers (IEEE (Institute of Electrical and Electronics Engineers Inc.)), and the JTAG (that is, a port using a Joint Test Action Group test) is a standard based on the Institute of Electrical and Electronics Engineers Inc. .
[0034]
The JTAG standard is currently defined as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary Scan Architecture.
An overview of the development, definition, and application of this JTAG is provided in the Test Access Port and Boundary Scan Architecture published by IEEE Computer Society Press, Los Alamitos, California (1990), author C.A. M. Maunder and R.A. E. FIG. Available at Tulloss
Have been.
(2) Summary of the second invention
In the second aspect, the target electronic component is a semiconductor integrated circuit and a printed wiring board on which the semiconductor integrated circuit is mounted.
(3) Summary of the third invention
In a third aspect of the present invention, the circuit block switching circuit includes a scan range for scanning a target electronic component in a horizontal direction or a vertical direction when a voltage corresponding to the test mode is applied to the test mode terminal. The target electronic component is scanned, for example, horizontally or vertically by external scanning in response to the setting signal set by the setting unit and set by the scan range setting unit, to diagnose the target electronic component. Or do a test.
(4) Summary of the fourth invention
In the fourth invention, when a voltage corresponding to the test mode is not applied to the test mode terminal, the circuit block switching circuit applies a signal to the target electronic component based on an internal control signal sent from the internal control unit, for example, in a horizontal direction. Alternatively, the target electronic component is diagnosed or tested by scanning vertically.
(5) Summary of the fifth invention
In the fourth invention, the circuit block switching circuit is provided with a printed circuit board test terminal for testing the printed circuit board.
[0035]
[Action]
(1) In the first invention, the scanning of the target electronic component is performed by the clock signal sent from the external device. Therefore, the external scanning method of supplying the clock signal from the external device and the internal control scanning method (JTAG scanning method) conforming to the IEEE. In order to diagnose or test the target electronic component or the like by using both of the above, both the external scan circuit block and the JTAG scan circuit block are switched to be used.
[0036]
In this way, by switching to and using both the external scan circuit block and the JTAG scan circuit block, a system that allows the external scan circuit block to scan in the horizontal direction or the vertical direction, The scan circuit block can be used, for example, in a system in which scanning is performed in the horizontal or vertical direction, so that the external scan circuit block and the JTAG scan circuit block can be quickly switched according to the target electronic component, and the usability is improved. Can be.
(2) In the second invention, a diagnosis and a test of a semiconductor integrated circuit which is a target electronic component and a printed wiring board on which the semiconductor integrated circuit is mounted are performed.
[0037]
This makes it possible to quickly diagnose and test the semiconductor integrated circuit and the printed wiring board on which the semiconductor integrated circuit is mounted.
(3) In the third invention, in the circuit block switching circuit, when a voltage corresponding to the test mode is applied to the test mode terminal, the target electronic component is scanned in a horizontal or vertical direction, for example. The target electronic component is scanned by the external scan circuit block in the horizontal or vertical direction, for example, in response to the setting signal set by the scan range setting unit. Diagnose or test parts.
[0038]
As a result, the target electronic component can be diagnosed and tested by quickly switching to a circuit block adapted to a system employing the so-called external scanning method.
(4) In the fourth invention, when a voltage corresponding to the test mode is not applied to the test mode terminal, the circuit block switching circuit sends the target electronic component based on an internal control signal sent from the internal control unit. For example, scanning or scanning in the horizontal or vertical direction is performed to diagnose or test the target electronic component.
[0039]
For this reason, it is possible to quickly switch to a circuit block adapted to a system adopting a so-called internal control scanning method, and diagnose and test the target electronic component.
(5) In the fourth aspect, the circuit block switching circuit is provided with a printed circuit board test terminal for testing the printed circuit board, so that the printed circuit board test can be performed smoothly.
[0040]
【Example】
Hereinafter, embodiments of the present invention will be described with reference to the drawings.
(Example 1)
A first embodiment will be described with reference to the circuit diagrams of FIGS.
[0041]
[Overview of Example 1]
In the first embodiment, a printed circuit board on which an LSI and an LSI are mounted by using both an external scan method in which a clock signal is supplied from an external circuit to perform an external scan and an internal control scan method (JTAG scan method) compliant with IEEE. In order to make a diagnosis or a test of the external scanning circuit block, both the external scanning circuit block and the JTAG scanning circuit block are used.
[0042]
As described above, by switching to use both the external scan circuit block and the JTAG scan circuit block, it is possible to easily use the system for scanning with the external scan circuit block or the system for scanning with the JTAG scan circuit block. Testing and evaluation can be performed quickly.
[Contents of Embodiment 1]
The configuration of the first embodiment will be described with reference to the circuit diagrams of FIGS.
[0043]
FIG. 1 is a circuit diagram when the first embodiment of the test apparatus of the present invention is applied to an LSI, FIG. 2 is a specific circuit diagram of FIG. 1, and FIG. 3 is a detailed circuit diagram of main parts.
In this embodiment, the LSI 30 shown in FIGS. 1 to 3, the printed wiring board, and the entire system are tested using the internal control scan (JTAG) method and the external scan method. Is provided with a test mode input terminal EX that enables the switching of the test mode.
[0044]
The JTAG method used in the first embodiment is a standard based on the Institute of Electrical and Electronics Engineers (IEEE (the Institute of Electrical and Electronics Engineers Inc.)), and is a JTAG (ie, Joint Test Action) test. Is a method that uses
[0045]
The JTAG standard is currently defined as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary Scan Architecture. A summary of the development, definition and application of this JTAG is also provided in the Test Access Port and Boundary Scan Architecture published by IEEE Computer Society Press, Los Alamitos, California (1990), author C.A. M. Maunder and R.A. E. FIG. Provided by Tulloss.
[0046]
Now, let us return to the description of the circuits of FIGS.
1 to 3, an operation mode generation circuit 19 for generating an operation mode, a clock generation circuit 20 for generating a clock, an instruction register 16 as an instruction register, and a control signal generation circuit for generating a control signal are provided on an LSI 30. 17, a test circuit 10 including a JTAG signal suppress circuit 18 for checking the signal level of the JTAG signal, a control signal selection circuit 21 for selecting a control signal, and a scan output selection circuit 22 for selecting a scan output, For example, a scan flip-flop 11 that scans electronic components in horizontal and vertical directions, a gate circuit 23 that supplies a gate signal to the scan flip-flop 11 to operate the scan flip-flop 11, a scan selection circuit 22, and a control signal Selection circuit O macro circuit 15 supplies a scan clock signal on the basis of the output signal is provided.
[0047]
In FIGS. 1 and 2, the test circuit 10 is represented by a two-dot chain line, and in FIG. 3, the test circuit 10 is represented by one IC.
In the operation mode generating circuit 19 shown in FIGS. 1 and 2, a test signal input terminal TM for inputting a test signal, a test mode signal terminal EX for inputting a test mode signal, or a printed circuit board test signal input for testing a printed circuit board. A test signal, a test mode signal or a printed wiring board test signal is input from a terminal PTM or the like, and an operation mode generation output is input to the scan output selection circuit 22, the JTAG signal suppression circuit 18, or the control signal selection circuit 21.
[0048]
In the clock generation circuit 20 shown in FIGS. 1 and 2, an A / B clock generation output is input to a control signal selection circuit 21 from a scan A / B clock signal input terminal for inputting a scan A / B clock signal.
[0049]
On the other hand, in the instruction register 16 shown in FIGS. 1 and 2, when a scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.
[0050]
The control signal generation circuit 17 shown in FIGS. 1 and 2 operates by a test data in terminal TRST, a test clock terminal TCK, a test data in signal input to a test mode selector terminal TMS, a test clock signal and a test mode selector signal. A state transition circuit (not shown) is provided.
[0051]
For this reason, in the control signal generation circuit 17, a test data in signal, a test clock signal, and a test mode selector signal input from the external device outside the LSI 30 to the test data in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. Is input in a predetermined procedure, a basic operation mode is set.
[0052]
In the control signal generation circuit 17, the value of the dedicated scan FF is input to a pin of the LSI 30 to a state transition circuit (not shown) that operates by switching mode information, and the control signal generation circuit 17 generates the value based on the value input to the pin of the LSI 30. The control signal is input to the scan output selection circuit 22 and the JTAG signal suppression circuit 19.
[0053]
In this embodiment, in order to operate the LSI 30 of the JTAG scan system by the external scan system, the JTAG signal suppressor circuit 18, the control signal selection circuit 21, and the scan output selection circuit 22 shown in FIGS. A JTAG scan signal is blocked by setting the test mode signal to an ON state (H level voltage) at a test mode signal terminal EX which is a scan method selection signal supplied from the device.
[0054]
In this embodiment, at the same time, the operation mode of the scan clock generation circuit 20 and the input / output macro circuit 15 is set to a value suitable for the external scan method, and the same operation as the external scan method is guaranteed.
[0055]
That is, in the present embodiment, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the JTAG signal suppressor circuit 21 causes the control signal generating circuit 18 to output the instruction register signal from the instruction register. The control signal to the control signal generator 16 is set to the non-operation state, and the register data from the instruction register 16 to the control signal generation circuit 17 is set to the non-operation state.
[0056]
At this time, in the scan output selection circuit 22, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the scan chain is controlled by a chain select signal from outside the LSI 30. select.
[0057]
In the control signal selection circuit 21, when the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), a scan clock and a chain select signal transmitted from outside the LSI 30. Thus, the scan clock is supplied to the scan FF 11 and the input / output macro circuit 15, and the operation mode of the input / output macro circuit 15 is set to the same mode as the external scan method.
[0058]
On the other hand, inside the LSI 30, an instruction register 16 that defines a test state in the test circuit 10 and an instruction register value of the register 16 are decoded to generate a scan clock, select a scan path, and operate an input / output macro. An input / output macro circuit 15 for selecting a mode is provided.
[0059]
A dedicated scan FF 11 is connected to the input / output macro circuit 15 so that a scan chain connecting macros is formed.
In the control signal generation circuit 17 described above, the value of the dedicated scan FF is input to a pin of the LSI 30 to a state transition circuit (not shown) that operates by switching the mode information, and the value input to the pin of the LSI 30 is The control signal generated based on the signal can be input to the scan output selection circuit 22 and the JTAG signal suppression circuit 19.
[0060]
The control signal generation circuit 17 is operated by the test data-in terminal TRST, the test clock terminal TCK, the test data-in signal input to the test mode selector terminal TMS, the test clock signal, and the test mode selector signal as described above. The basic operation mode can be set by inputting these signals from an external device external to the LSI 30 in a state transition circuit in a predetermined procedure.
[0061]
Among these, there is a scan operation mode for the instruction register 16. First, this mode is set and a detailed operation mode value is scanned into the instruction register 16.
[0062]
After that, by setting the state transition circuit of the control signal generation circuit 17 to a decoding operation mode for decoding the register value of the instruction register 16, complicated scan operation and mode switching control are performed.
[0063]
In this embodiment, a JTAG signal suppression circuit 18, a control signal selection circuit 21 and a scan output selection circuit 22 are provided in order to operate the JTAG scan type LSI 30 in the external scan mode. The scan mode selection signal is external to the LSI 30. The test mode signal EX prevents input of a JTAG scan signal.
[0064]
In this embodiment, at the same time, the operation mode of the scan clock generation circuit 20 and the input / output macro circuit 15 is set to a value suitable for the external scan method, and the same operation as the external scan method is guaranteed.
[0065]
That is, in the present embodiment, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the JTAG signal suppressor circuit 21 causes the control signal generating circuit 18 to output the instruction register signal from the instruction register. The control signal to the control signal generator 16 is set to the non-operation state, and the register data from the instruction register 16 to the control signal generation circuit 17 is set to the non-operation state.
[0066]
At this time, in the scan output selection circuit 22, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the scan chain is controlled by a chain select signal from outside the LSI 30. select.
[0067]
In the control signal selection circuit 21, when the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), a scan clock signal transmitted from outside the LSI 30 is supplied to the gate circuit. By supplying a scan clock to the input / output macro circuit 15 in accordance with the chain select signal supplied to the scan FF 11 via the input / output circuit 23, the operation mode of the input / output macro circuit 15 can be set to the same mode as the external scan mode. it can.
(Operation of Embodiment 1)
Next, the operation of the first embodiment will be described with reference to FIGS.
[0068]
This operation will be described with reference to the circuit diagrams of FIGS. 1 to 3 described above.
FIG. 7 is a diagram for explaining the operation of the JTAG & external scanning method.
[0069]
In the operation explanatory diagram of FIG. 7, JTAG scan LSIs 31 and 32 and a JTAG / external scan LSI 33 are used.
<External scanning method>
FIG. 4 shows a circuit block for selecting whether the LSI 30 operates in the external scan mode or the internal control scan mode in the JTAG mode, thereby determining whether to select the JTAG scan circuit block or the external scan circuit block. (ST10).
[0070]
Here, for example, when changing from the JTAG scan method to the external scan method as described above, the external scan method is selected, and the settings in ST20 to ST22 described below are performed. A test is performed on a printed wiring board on which the LSIs 31 to 33 are mounted.
[0071]
FIG. 5 is an explanatory diagram for explaining an operation when switching a circuit block from a JTAG scan circuit block to an external scan circuit block.
When the external scan circuit block is selected in ST19 in FIG. 4, a test mode signal is input to the test mode terminals EX of the LSIs 31 to 33 in FIGS. 1 and 2 to be turned on (H level voltage) (ST20).
[0072]
In the operation mode generating circuit 19 shown in FIGS. 1 and 2, a test signal input terminal TM for inputting a test signal, a test mode signal terminal EX for inputting a test mode signal, or a printed circuit board test signal input for testing a printed circuit board. A test signal, a test mode signal or a printed wiring board test signal is input from a terminal PTM or the like, and an operation mode generation output is input to the scan output selection circuit 22 or the control signal selection circuit 21.
[0073]
At this time, the test circuit 10 sets the scan mode and the chain select to activate the scan chain (ST21).
After the activation of the scan chain, the scan-in value is set and the A / B clock voltage is applied from the scan A / B clock signal terminal (ST22). Thus, the operation of the JTAG scan circuit block is stopped by operating the external scan circuit block.
[0074]
That is, in the clock generation circuit 20 shown in FIGS. 1 and 2, the scan A / B clock signal is input to the A / B clock signal input terminals A-CLK and B-CLK clocks shown in FIG. The clock generation output is input to the control signal selection circuit 21.
[0075]
On the other hand, in the instruction register 16 shown in FIG. 5 and the like, when a scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.
[0076]
The control signal generation circuit 17 shown in FIG. 5 and the like has a state transition circuit based on a test data in terminal TRST, a test clock terminal TCK, a test data in signal input to a test mode selector terminal TMS, a test clock signal, and a test mode selector signal. (Not shown).
[0077]
For this reason, in the control signal generation circuit 17, a test data in signal, a test clock signal, and a test mode selector signal input from the external device outside the LSI 30 to the test data in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. Is input in a predetermined procedure, a basic operation mode is set.
[0078]
In the control signal generation circuit 17, the value of the dedicated scan FF is input to a pin of the LSI 30 to a state transition circuit (not shown) that operates by switching mode information, and the control signal generation circuit 17 generates the value based on the value input to the pin of the LSI 30. The control signal is input to the scan output selection circuit 22 and the JTAG signal suppression circuit 19.
[0079]
Further, in this embodiment, in order to operate the LSI 30 of the JTAG scan method by the external scan method, FIG. 3 including the JTAG signal suppress circuit 18, the control signal selection circuit 21, and the scan output selection circuit 22 shown in FIGS. The test system circuit 10 is provided, and a test mode signal is input to a test mode signal terminal EX which is a scan mode selection signal from the outside of the LSI 30 to be turned on (H level voltage). Any input terminal of the LSI 30 can be prevented from being supplied to the LSI 30.
[0080]
In this embodiment, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the JTAG signal suppressor circuit 21 sends the instruction register 16 from the control signal generator circuit 18 to the instruction register 16. Is set to the non-operation state, and the register data from the instruction register 16 to the control signal generation circuit 17 is set to the non-operation state.
[0081]
At this time, in the scan output selection circuit 22, the test mode signal input from the test mode signal input terminal EX of the LSI 30 is turned on (H level voltage), so that the scan chain is controlled by a chain select signal from outside the LSI 30. select.
[0082]
In the control signal selection circuit 21, when the test mode signal input from the test mode signal input terminal EX is turned on (H level voltage), a scan clock signal sent from outside the LSIs 31 to 33 is supplied to the gate circuit. By supplying a scan clock to the input / output macro circuit 15 in accordance with the chain select signal supplied to the scan FF 11 via the input / output circuit 23, the operation mode of the input / output macro circuit 15 can be set to the same mode as the external scan mode. it can.
[0083]
By performing the above processing, it is possible to prevent the JTAG scan signal from being input to the test circuit 10 by the test mode EX signal which is the scan method selection signal from outside the LSIs 31 to 33, and to prevent the scan clock and the input / output The operation mode of the macro circuit 15 is set to a value suitable for the external scanning method, and the operation as the external scanning method is also guaranteed.
[0084]
Therefore, in order to diagnose and test an external scan LSI using both an external scan method in which a clock signal is supplied from an external circuit to perform an external scan and an internal control scan method (JTAG scan method) compliant with IEEE. And switch to an external scan circuit block for use.
[0085]
As described above, by switching to the external scan circuit block and using it, it is possible to easily use the system for scanning by the external scan circuit block, and it is possible to quickly test and evaluate the system.
<When JTAG scan method is selected>
Next, in ST10 of FIG. 4, when the JTAG scan method is selected from the external scan method, the test mode signal input from the test mode signal input terminal EX is turned off (L level voltage) (ST31).
[0086]
At this time, in order to activate the scan chain of the instruction register 16 shown in FIG. 6, the scan FF 11 is operated by the setting of the scan mode and the scan clock CLK signal of the control signal generation circuit 17 which is a TAP controller.
[0087]
That is, in ST31, after the test mode signal input from the test mode signal terminal EX is turned off (L level voltage), the scan mode is set in order to activate the scan chain input to the instruction register 16. At the same time, the control signal generation circuit 17 which is a TAP controller is set (ST32).
[0088]
After setting the scan mode and setting the control signal generation circuit 17 as a TAP controller, in order to perform a scan operation of the instruction register 16, an instruction (IR) code is set in the instruction register 16 and the control is performed. A test clock voltage is applied to the A / B clock terminal from the test clock terminal TCK to the signal generation circuit 17 (ST33).
[0089]
After setting the instruction (IR) code in the instruction register 16 and applying the test clock voltage to the A / B clock terminal from the test clock terminal TCK to the control signal generation circuit 17, the scan mode setting and the chain select setting are performed. To activate the scan chain (ST33).
[0090]
After the activation of the scan chain, the scan-in value is set and the A / B clock voltage is applied from the scan A / B clock signal terminal (ST35). Thus, the operation of the external scan circuit block is stopped by operating the internal scan circuit block.
[0091]
That is, in the clock generation circuit 20 shown in FIGS. 1 and 2, the scan A / B clock signal is input to the scan A / B clock signal input terminals A-CLK and B-CLK clock shown in FIG. Input clock signal.
[0092]
On the other hand, in the instruction register 16 shown in FIG. 6 and the like, when a scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.
[0093]
The control signal generation circuit 17 shown in FIG. 5 and the like has a state transition circuit based on a test data in terminal TRST, a test clock terminal TCK, a test data in signal input to a test mode selector terminal TMS, a test clock signal, and a test mode selector signal. (Not shown).
[0094]
For this reason, in the control signal generation circuit 17, a test data in signal, a test clock signal, and a test mode selector signal input from the external device outside the LSI 30 to the test data in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. Is input in a predetermined procedure, a basic operation mode is set.
[0095]
The control signal generation circuit 17 inputs the value of the dedicated scan FF to a pin of the LSI 30 to a state transition circuit (not shown) that operates by switching the mode information.
In this embodiment, in order to operate the LSI 33 of the external scan system by the internal control scan system, FIG. 3 including the JTAG signal suppress circuit 18, the control signal selection circuit 21, and the scan output selection circuit 22 shown in FIGS. A test system circuit 10 shown in FIG. 1 is provided, and a test mode signal is not input to a test mode signal terminal EX, which is a scan mode selection signal from the outside of the LSI 30, and the test mode signal is turned off (L level voltage). Supplies the data to the LSIs 31 to 33 from any of the input terminals of the LSIs 31 to 33.
[0096]
In this embodiment, the test mode signal not input from the test mode signal input terminal EX of the LSI 33 is turned off (L level voltage). The control signal to the control signal generator 16 is set to the operation state, and the register data from the instruction register 16 to the control signal generation circuit 17 is set to the operation state.
[0097]
In the control signal generation circuit 17, when a test mode signal not input from the test mode signal input terminal EX is turned off (L level voltage), a scan clock signal transmitted from outside the LSIs 31 to 33 is gated. The operation mode of the input / output macro circuit 15 is set to the same mode as that of the external scan method by supplying the scan clock to the input / output macro circuit 15 by supplying the scan clock to the input / output macro circuit 15 by the chain select signal supplied to the scan FF 11 via the circuit 23. Can be.
[0098]
By performing the above processing, the test mode EX signal, which is a scan mode selection signal, is not applied from outside the LSIs 31 to 33, thereby preventing input of an external scan mode signal to the test circuit 10. At the same time, the scan clock and the operation mode of the input / output macro circuit 15 are set to values suitable for the internal control scan method, thereby guaranteeing the operation as the JTAG scan method.
[0099]
For this reason, in order to diagnose and test the LSI of the internal control scan system using the internal control scan system (JTAG scan system) based on IEEE, the internal control scan circuit block is switched to be used.
[0100]
As described above, by switching to the internal control scan circuit block and using it, the system can be easily used even in a system scanned by the internal control scan circuit block, and the test and evaluation of the system can be performed quickly.
(Modification 1 of Embodiment 1)
[Overview of Modified Example 1 in Example 1]
As a first modification of the first embodiment, a test of a printed wiring board on which an LSI is mounted is performed. If the test method of the printed wiring board is different, the test is performed by switching the circuit block to either the external scan method or the internal control method. [Contents of Modified Example 1 of Example 1]
1 and 2, when testing a printed wiring board, first, a printed wiring board test voltage is applied to a pin of an LSI, for example, from a printed wiring board test terminal PTM of an operation mode generation circuit 19 of a test circuit 30. Then, perform an insulation test on the printed wiring board.
[0101]
When testing the printed wiring board by the external scanning method, for example, the insulation test of the printed wiring board is performed by operating the external scanning circuit block of FIG. 5 from ST20 to ST22 of FIG.
[0102]
On the other hand, when testing the printed wiring board by the internal control scan method, for example, the internal control scan circuit block in FIG. 6 is operated in ST31 to ST35 in FIG. 4 to perform an insulation test on the printed wiring board.
[0103]
As described above, by switching the circuit block between the external scan method and the internal control method, the printed circuit board operating in the external scan method or the printed circuit board operating in the internal control scan method can operate normally. Can be tested.
(Modification 2 of Embodiment 1)
[Overview of Modified Example 2 in Example 1]
As a modified example 2 of the first example, a test of the entire system is performed.
[0104]
If the test method of the entire system is different, the test is performed by switching the circuit block to either the external scan method or the internal control method.
[Contents of Modified Example 2 of Example 1]
1 and 2, when testing the whole system, first, a whole system test terminal (not shown) is applied to a whole system test terminal provided in the operation mode generation circuit 19 of the test circuit 30 from a whole system test terminal (not shown). I do.
[0105]
Further, for example, when testing whether or not the entire system operates normally by the external scan method, the external scan circuit block in FIG. 5 is operated from ST20 to ST22 in FIG. Do tests such as whether or not.
[0106]
On the other hand, when testing whether the entire system is normally insulated by the internal control scan method or the like, the internal control scan circuit block in FIG. 6 is operated from ST31 to ST35 in FIG. Test that it is.
[0107]
As described above, by switching the circuit block to either the external scan method or the internal control method, a test such as an insulation test can be performed normally even if the system operates according to the external scan method or the system operates according to the internal control scan method. Can be.
[0108]
【The invention's effect】
According to the first aspect of the present invention, by using both the external scan circuit block and the JTAG scan circuit block while switching, the system allows the external scan circuit block to scan in the horizontal or vertical direction. It can also be used in a system that scans horizontally or vertically with the JTAG scan circuit block, so that it is possible to quickly switch between the external scan circuit block and the JTAG scan circuit block according to the target electronic component, and to improve the usability. The effect that it can be obtained can be obtained.
[0109]
According to the second aspect of the present invention, the diagnosis and test of the semiconductor integrated circuit as the target electronic component and the printed wiring board on which the semiconductor integrated circuit is mounted can be quickly diagnosed and performed according to the printed wiring board on which the semiconductor integrated circuit is mounted. The effect that a test can be performed can also be obtained.
[0110]
On the other hand, according to the third aspect, when a voltage corresponding to the test mode is applied to the test mode terminal, the scan range setting unit sets the range in which the target electronic component is scanned in the horizontal direction or the vertical direction. Then, in response to the setting signal set by the scan range setting unit, the external scan circuit block scans the target electronic component horizontally or vertically to diagnose or test the target electronic component. Can be obtained quickly.
[0111]
Further, according to the fourth aspect, when a voltage corresponding to the test mode is not applied to the test mode terminal, the target electronic component is quickly switched to a circuit block adapted to a system employing a so-called internal control scan system. Can be diagnosed and tested.
[0112]
Further, according to the fifth aspect, by providing the printed wiring board test terminal for testing the printed wiring board, the printed wiring board test can be smoothly performed.
[Brief description of the drawings]
FIG. 1 is a circuit diagram showing a circuit outline of an embodiment of the present invention.
FIG. 2 is a detailed circuit diagram of an embodiment of the present invention.
FIG. 3 is a detailed circuit diagram showing a main part of the embodiment of the present invention.
FIG. 4 is a flowchart for explaining the operation of the first embodiment of the present invention.
FIG. 5 is an explanatory diagram of an operation of an external scanning method which is an example of an embodiment of the present invention.
FIG. 6 is an explanatory diagram of an operation of an internal control scanning method which is an example of an embodiment of the present invention.
FIG. 7 is an operation explanatory diagram of the embodiment of the present invention.
FIG. 8 is a circuit diagram of a conventional test circuit.
FIG. 9 is a flowchart of a conventional test circuit.
FIG. 10 is a circuit diagram of a conventional test circuit.
FIG. 11 is a flowchart of a conventional test circuit.
[Explanation of symbols]
10 Test circuit
11 scan FF
15. Input / output macro circuit
16 Instruction Register
17 Control signal generation circuit
18 JTAG signal suppression circuit
19 Operation mode generation circuit
20 Clock generation circuit
21 Control signal selection circuit
22 Scan output selection circuit
23 Gate circuit
30 Switching circuit
31 JTAG Scan LSI
32 JTAG scan LSI
33 JTAG / External Scan LSI

Claims (5)

An external scan circuit block that supplies a clock signal from the external device for testing a target electronic component in accordance with a signal sent from the external device, and controls the inside of the circuit by an internal control signal supplied from a control circuit in the circuit. In an apparatus for diagnosing or testing the target electronic component using an internal control scan circuit block for testing the target electronic component,
Providing a circuit block switching circuit to be used by switching to both the external scan circuit block and the internal control scan circuit block,
When diagnosing or testing the target electronic component using the external scan circuit block, the circuit block switching circuit sets an external scan by an external clock signal for scanning the target electronic component to be diagnosed or tested. Set in the section and switch to the external scan circuit block,
When diagnosing or testing the target electronic component using the internal control scan circuit block, a control signal transmitted from a control circuit inside the circuit for scanning the target electronic component to be diagnosed or tested is used. Test equipment that switches to the internal control scan circuit block that is set by the internal control scan setting unit. The test apparatus according to claim 1, wherein the target electronic component is a semiconductor integrated circuit and a printed wiring board on which the semiconductor integrated circuit is mounted. In the circuit block switching circuit, when a voltage corresponding to a test mode is applied to a test mode terminal, a scan range setting unit sets a scan range of the target electronic component,
Performing the external scan in response to a setting signal set by the scan range setting unit;
The test apparatus according to claim 1. The said circuit block switching circuit, when a voltage corresponding to the test mode the test mode terminal is not applied, by scanning the target electronic component on the basis of the internal control signal sent from the circuit inside the control circuit, the target Diagnose or test electronic components,
The test apparatus according to claim 1. The circuit block switching circuit is provided with a printed wiring board test terminal for testing the printed wiring board,
The test apparatus according to claim 1.

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