JPH08114647A - Tester - Google Patents

Abstract

PURPOSE: To test an LSI or printed wiring board different in scanning system with the same device by changing over an external scanning system and an internal control (JTAG) scanning system in a testing direction. CONSTITUTION: In order to perform a test using both of an external scanning system supplying a clock signal from an external circuit in order to perform external scanning and a JTAG scanning system, an external scanning circuit block and a JTAG scanning circuit block are changed over to be used. That is, in order to operate the LSI 30 of the JTAG scanning system with the external scanning system, a JTAG signal suppressing circuit 18, a control signal selection circuit 21 and a scanning output selecting circuit 22 are provided. By bringing the test mode signal being the scanning system selecting signal from the outside of the LSI 30 to an ON-state on a terminal EX, the signal of the JTAG scanning system is blocked. At the same time, the operation mode of a clock forming circuit 20 becomes the external scanning system.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test apparatus, and particularly to a test for both an external scan method in which a clock signal is supplied from an external circuit to perform an external scan and an IEEE-compliant internal control scan method (JTAG scan method). The present invention relates to a test device that enables the execution of

[0002]

2. Description of the Related Art Generally, in testing semiconductor integrated circuits,
The number of possible states increases with the increase in the scale of the logic circuit, and the control of the logic circuit cannot follow the increased number of states, so that the test cannot be performed.

In particular, in a semiconductor integrated circuit including a logic circuit which is limited in the number of input / output terminals and whose internal structure makes it virtually impossible to directly observe an internal state,
Since the control of the logic circuit and the like cannot follow the number of states further, the test of the semiconductor integrated circuit becomes more difficult.

Therefore, a test circuit in which a sequential circuit is pseudo-combined into a circuit has been used in this type of test apparatus. Such a test apparatus includes, for example, JTAG (that is, Joi) which is an internal control scan method based on IEEE for testing an IC chip mounted on a board.
nt Test Action Group) Some use test ports.

With this JTAG method, the Institute of E
adopted by Electrical and Electronics Engineers, INC. and is currently defined as IEEE Standard 1149.1, IEEE Standard Test Access Port and Boundary Scan Architecture.

An outline of the development, definition and application of this JTAG is given in IEEE Computer SocieityPress, Los Alamito
Test Access Port and Boundary-Scan Architecture, author CM Maunder, published by S., California (1990).
And RETulloss.

FIG. 8 shows an example of a semiconductor integrated circuit testing apparatus adopting such a JTAG scan system. In FIG. 8, control signal generation circuits 50a to 52a including an instruction register (IR) and a scan A / B clock generation circuit that generates a scan A / B phase two-phase clock are provided inside the LSIs 50 to 52, The states of the control circuits inside the LSIs 50 to 52 are set by a sequence signal from an external circuit and scanning is performed.

In FIG. 8, ACK is an input terminal for the A clock signal and BCK is an input terminal for the B clock signal. The scan input terminal SI is an input terminal for inputting a scan signal, and the scan output terminal SO is an output terminal for outputting a scan signal.

Further, the chain select CS is a chain select input terminal for selecting a range to be connected in the same scan chain, and the test mode selection signal input terminal TM is an input terminal for a signal for selecting a test mode.

LSI using this JTAG scan method
In order to perform the tests of 50 to 52, in order to set the flip-flop FF or the like mounted in the LSIs 50 to 52 or the printed wiring board 53 to an arbitrary value, it is necessary to perform the processing according to the flowchart of FIG.

That is, in the flow chart shown in FIG. 9, a group of FFs (Ins) for setting an instruction for a test is set.
In order to activate the chain connection of the instruction register scan system in which the truction resister (called IR register) is connected in series, first, the scan mode is set and the tap TAP controller which is the JTAG test system control circuit is set (ST100). ).

Scan mode setting and tap TAP
After the controller is set, in order to perform the scanning operation of the instruction register IR, the instruction register IR code is set and the input voltage is applied from the test clock terminal TCK to the scan A / B phase clock terminal (ST101). .

After setting the IR code and applying it from the test clock terminal TCK to the scan A / B clock terminal, the scan mode and tap TAP controller are set in order to activate the scan chain connection. ST102).

Setting of this scan mode and tap T
After the AP controller is set, the scan-in value input to the scan input terminal is set and the input voltage is applied from the test clock terminal TCK to the scan A / B clock terminal in order to perform the scan operation (ST10).
1).

When applying the scan-in value setting signal input to the scan input terminal and the input voltage from the test clock terminal TCK to the scan A / B clock terminal,
The process of the flowchart described above ends.

On the other hand, in the test apparatus which employs the external scan method shown in FIG. 10 to perform a test, a signal for scanning is supplied from an external circuit, and the LSI 54-
Arbitrary values are set in the flip-flops FF and the like mounted inside 56 and the printed wiring board 57.

In FIG. 10, the timing clock input terminal TCK indicates a timing clock input terminal, and the timing signal input terminal TMS indicates a timing signal input terminal.

The scan signal input terminal SI is an input terminal for inputting a scan signal, and the scan signal output terminal SO.
Is an output terminal for outputting a scan signal. Further, the test data output terminal TRST is a test data output terminal, and the test mode signal input terminal TM is a test mode signal input terminal.

In the test apparatus of FIG. 10, the LSIs 54 to 56 are used.
When setting an arbitrary value to the flip-flop FF mounted on the board or the board, it is necessary to perform processing according to the flowchart of FIG.

That is, in the flowchart shown in FIG. 11, in order to activate the chain connection of the instruction register IR scan, first, the scan mode and the chain select are set (ST11).
0).

After the scan mode and the loop select are set, in order to perform the scan operation,
Input an input voltage from the scan-in value setting and test clock TCK to the scan A / B clock terminal (ST
101).

After applying the input voltage to the scan A / B clock signal terminal from the scan-in value setting and the test clock TCK to the scan A / B clock terminal,
The process of the flowchart described above ends.

As a result, for example, the LSIs 54 to 56 can be used.
Or a flip-flop FF mounted on the substrate is set to an arbitrary value, and if the set value is not set, the LSIs 54 to 56
Can be tested for abnormalities.

As an example of the test apparatus described above, for example, the one using the internal control system is disclosed in Japanese Patent Laid-Open No. 5-16.
4826 or JP-A-5-180911, and those using an external scanning system include JP-A-64-68843 or JP-A-61-158587.
Some of them are described in Japanese Patent Publication No. 4 and the like.

[0025]

However, in the test apparatus described above, the LSI,
Test the printed wiring board and the entire system,
When these test methods are different, it becomes impossible to test the LSI, the printed wiring board, and the entire system by one device.

For example, the LSI test is internally controlled (JT
AG) system, and when the total test of the printed wiring board and the system is carried out by the external scan system, it becomes difficult to carry out these tests with one test device.

Therefore, the present invention has been made in view of these problems, and by switching between the external scanning method and the JTAG testing method during system development, the scanning method can be changed by one device. LS
It is an object of the present invention to provide a test apparatus capable of testing I, a printed wiring board, and the entire system.

[0028]

The present invention adopts the following means in order to solve the above problems. (1) Summary of the first invention In the first invention, both an external scan method of supplying a clock signal from an external circuit to perform an external scan and a JTAG scan method which is an IEEE-compliant internal control scan method are used. In order to diagnose and test the target electronic component, a switching circuit is provided to switch between external scanning and JTAG scanning for use.

When the external scanning method is selected by this switching circuit, in order to input a clock signal from an external device to diagnose or test the target electronic component, for example, a portion of the target electronic component is set as a set of points. The target electronic component is scanned, for example, in the horizontal direction or the vertical direction to diagnose and test the target electronic component.

Further, when the IEEE compliant JTAG scanning method is selected in the switching circuit, in order to diagnose the target electronic component by the internal control signal input from the internal control circuit, for example, a part of the target electronic component is set as a set of dots. As a result, the target electronic component is scanned, for example, in the horizontal direction or the vertical direction to diagnose and test the target electronic component.

In this test apparatus, by switching between the external scan system and the internal control (JTAG) scan system by using the switching circuit, a system for scanning by the external scan system or a system for scanning by the JTAG scan system is used. Can be used for both.

As a result, the target electronic component used in the system for scanning by the external scan system or the system for scanning by the JTAG scan system can be diagnosed or tested by one test device. Since the external scan method and the JTAG scan method can be switched quickly, system development of different scan methods becomes convenient.

The JTAG system is based on the IEEE (the Institute of Electrical and Elec
tronics Engineers Inc.)
This method uses an AG (that is, Joint Test Action Group) test port.

In this JTAG system, the IEEE standard 1149.1, I
Currently defined as an EEE standard test access port and boundary scan architecture. For an overview of the development, definition and application of this JTAG, see IEEE Computer Sociei.
Test access port and boundary scan architecture published by tyPress, Los Alamitos, California (1990), provided by authors CM Maunder and RETulloss. (2) Summary of the Second Invention In the second invention, the target electronic component is a semiconductor integrated circuit and a printed wiring board on which the semiconductor integrated circuit is mounted. (3) Summary of the third invention In the third invention, in the circuit block switching circuit, when a voltage according to the test mode is applied to the test mode terminal, for example, in the horizontal direction or the vertical direction with respect to the target electronic component. The range to be scanned in the direction is set by the scan range setting section, and in response to the setting signal set by this scan range setting section, by external scanning, for the target electronic component,
For example, scanning is performed in the horizontal direction or the vertical direction to diagnose or test the target electronic component. (4) Summary of the fourth invention In the fourth invention, the circuit block switching circuit is targeted based on the internal control signal sent from the internal control section when the voltage according to the test mode is not applied to the test mode terminal. The electronic component is scanned, for example, in the horizontal direction or the vertical direction to diagnose or test the target electronic component. (5) Summary of the fifth invention In the fourth invention, the circuit block switching circuit is provided with a printed wiring board test terminal for testing the printed wiring board.

[0035]

[Action]

(1) In the first invention, since the target electronic component is scanned by the clock signal sent from the external device,
An external scan circuit block and a JTAG scan circuit block are used to diagnose and test target electronic components using both an external scan method that supplies a clock signal from an external device and an IEEE-compliant internal control scan method (JTAG scan method). Switch to both so that they can be used.

In this way, the external scan circuit block and
By switching to both of the JTAG scan circuit blocks and using them, if this one test device is used, the system for causing the external scan circuit blocks to scan in the horizontal direction or the vertical direction, or in the JTAG scan circuit blocks, for example, in the horizontal direction or Since it can also be used in a system for scanning in the vertical direction, it can be quickly switched to the external scan circuit block and the JTAG scan circuit block according to the target electronic component, and the usability can be improved. (2) In the second invention, the semiconductor integrated circuit that is the target electronic component and the printed wiring board on which the semiconductor integrated circuit is mounted are diagnosed and tested.

Thus, it is possible to quickly diagnose and test according to the semiconductor integrated circuit and the printed wiring board on which the semiconductor integrated circuit is mounted. (3) In the third invention, in the circuit block switching circuit,
When a voltage according to the test mode is applied to the test mode pin, the scan range setting section sets the range for scanning the target electronic component in the horizontal or vertical direction. In response to the set signal that has been set, the external scan circuit block scans the target electronic component in, for example, the horizontal direction or the vertical direction to diagnose or test the target electronic component.

As a result, it is possible to quickly switch to a circuit block suitable for a system adopting a so-called external scan system and diagnose and test the target electronic component. (4) In the fourth invention, the circuit block switching circuit includes
When the voltage according to the test mode is not applied to the test mode terminal, the target electronic component is scanned, for example, in the horizontal direction or the vertical direction based on the internal control signal sent from the internal control unit to scan the target electronic component. Diagnose or test.

Therefore, it is possible to quickly switch to a circuit block suitable for a system adopting the so-called internal control scan system and diagnose and test the target electronic component. (5) In the fourth invention, the circuit block switching circuit includes
By providing a printed wiring board test terminal for testing the printed wiring board, the printed wiring board can be tested smoothly.

[0040]

Embodiments of the present invention will be described below with reference to the drawings. (Embodiment 1) A first embodiment will be described with reference to the circuit diagrams of FIGS.

[Outline of First Embodiment] In the first embodiment, an external scan system in which a clock signal is supplied from an external circuit to perform an external scan and an internal control scan system conforming to the IEEE standard.
LSI and LS using both (JTAG scan method)
In order to diagnose and test a printed circuit board on which I etc. are mounted, it is used by switching to both the external scan circuit block and the JTAG scan circuit block.

In this way, the external scan circuit block
By switching and using both JTAG scan circuit blocks, it can be easily used in a system that scans with an external scan circuit block or a system that scans with a JTAG scan circuit block, allowing quick system testing and evaluation. it can. [Contents of First Embodiment] The configuration of the first embodiment will be described with reference to the circuit diagrams of FIGS. 1 to 3.

FIG. 1 shows an LSI according to the first embodiment of the test apparatus of the present invention.
2 is a specific circuit diagram of FIG. 1, and FIG. 3 is a detailed circuit diagram of a main part. In this example,
The internal control scan (JTAG) method and the external scan method are used to test the LSI 30, the printed wiring board, and the entire system shown in FIGS. 1 to 3, so that the JTAG scan method LSI 30 can be switched to the external scan method. The test mode input terminal EX is provided.

The JTA used in this Example 1 is used.
The G method is based on the Institute of Electrical and Electronics Engineers ((IEEE (the Instit
(ute of Electrical and Electronics Engineers Inc.)
JTAG (that is, Joint Tes
t Action Group) This method uses a test port.

In this JTAG method, the IEEE standard 1149.1, I
Currently defined as an EEE standard test access port and boundary scan architecture. For an overview of the development, definition and application of this JTAG, see IEEE Computer Sociei.
Test access port and boundary scan architecture published by tyPress, Los Alamitos, California (1990), provided by authors CM Maunder and RETulloss.

Now, let us return to the description of the circuits shown in FIGS. 1 to 3, on the LSI 30, an operation mode generation circuit 19 that generates an operation mode, a clock generation circuit 20 that generates a clock, an instruction register 16 that is an instruction register, and a control signal generation circuit that generates a control signal. 17, a test system circuit 1 including a JTAG signal suppress circuit 18 for confirming the signal level of the JTAG signal, a control signal selection circuit 21 for selecting a control signal, and a scan output selection circuit 22 for selecting a scan output.
0, a scan flip-flop 11 that scans the target electronic component in the horizontal and vertical directions according to the value of the flip-flop, and a gate circuit 23 that supplies a gate signal to the scan flip-flop 11 to operate the scan flip-flop 11. Also provided are an input / output macro circuit 15 for supplying a clock signal scanned based on the output signals of the scan selection circuit 22 and the control signal selection circuit.

1 and 2, the test system circuit 10 is surrounded by a chain double-dashed line, and in FIG. 3, the test system circuit 10 is represented by one IC. In the operation mode generation circuit 19 shown in FIGS. 1 and 2, a test signal input terminal TM for inputting a test signal, a test mode signal terminal EX for inputting a test mode signal, or a printed wiring board test signal input for testing a printed wiring board. A test signal, a test mode signal or a printed wiring board test signal is input from the terminal PTM or the like, and an operation mode generation output is input to the scan output selection circuit 22, the JTAG signal suppress circuit 18 or the control signal selection circuit 21.

Clock generation circuit 2 shown in FIGS. 1 and 2.
At 0, the A / B clock generation output is input to the control signal selection circuit 21 from the scan A / B clock signal input terminal for inputting the scan A / B clock signal.

On the other hand, in the instruction register 16 shown in FIGS. 1 and 2, when the scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.

The control signal generation circuit 17 shown in FIGS. 1 and 2 includes a test data-in signal TRST, a test clock terminal TCK, a test data-in signal input to the test mode selector terminal TMS, a test clock signal and a test mode selector. A state transition circuit (not shown) that operates according to signals is provided.

Therefore, in the control signal generating circuit 17, the test data-in signal, the test clock signal, and the test data input from the external device outside the LSI 30 to the test data-in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. By inputting the mode selector signal in a predetermined procedure,
The basic operating mode is set.

The control signal generating circuit 17 includes a state transition circuit (not shown) which operates by switching the mode information.
Input the value of the dedicated scan FF to the SI30 pin and
The control signal generated based on the value input to the pin of I30 is input to the scan output selection circuit 22 and the JTAG signal suppress circuit 19.

In this embodiment, since the JTAG scan type LSI 30 is operated by the external scan type, the JTAG signal suppress circuit 18, the control signal selecting circuit 21 and the scan output selecting circuit 22 shown in FIGS. 1 and 2 are provided. By turning on the test mode signal to the test mode signal terminal EX which is a scan mode selection signal from the outside of the LSI 30 (H level voltage), the JTAG scan system signal is blocked.

Further, in the present embodiment, at the same time, the operation modes of the scan clock generation circuit 20 and the input / output macro circuit 15 are set to values suitable for the external scan system to guarantee the same operation as the external scan system. There is.

That is, in this embodiment, by turning on the test mode signal input from the test mode signal input terminal EX of the LSI 30 (H level voltage),
The JTAG signal suppress circuit 21 uses the control signal generation circuit 18
From the instruction register 16 to the instruction register 16 in the non-operational state,
The register data from the register 16 to the control signal generation circuit 17 is set to the non-operation state.

At this time, in the scan output selection circuit 22,
By turning on the test mode signal input from the test mode signal input terminal EX of the LSI 30 (H level voltage), the scan chain is selected by the chain select signal from the outside of the LSI 30.

Further, in the control signal selection circuit 21, the LSI 3
When the test mode signal input from the 0 test mode signal input terminal EX is turned on (H level voltage),
The scan FF 11 is driven by the scan clock and the chain select signal transmitted from the outside of the LSI 30.
Also, the scan clock is supplied to the input / output macro circuit 15, and the operation mode of the input / output macro circuit 15 is set to the same mode as the external scan method.

On the other hand, inside the LSI 30, an instruction register 16 for defining a test state in the test system circuit 10 and an instruction register 16 for the register 16 are provided.
An input / output macro circuit 15 is provided for decoding a register value, generating a scan clock, selecting a scan path, and selecting an operation mode of an input / output macro.

A dedicated scan FF 11 is connected to the input / output macro circuit 15 so that a scan chain is formed by connecting macros. Further, in the control signal generation circuit 17 described above, the LSI 30 has a state transition circuit (not shown) that operates by switching the mode information.
The value of the dedicated scan FF is input to the pin of, and the control signal generated based on the value input to the pin of the LSI 30 is used as the scan output selection circuit 22 and the JTAG signal suppress circuit 1.
9 can be entered.

In the control signal generation circuit 17, as described above, the test data in signal TRST, the test clock terminal TCK, the test data in signal input to the test mode selector terminal TMS, the test clock signal and the test mode selector signal are input. The basic operation mode can be set by inputting these signals from an external device outside the LSI 30 in a predetermined procedure in the state transition circuit that operates according to.

There is a scan operation mode for the instruction register 16 therein, and this mode is first set to scan a detailed operation mode value into the inside of the instruction register 16.

After that, the state transition circuit of the control signal generation circuit 17 is set to the decoding operation mode for decoding the register value of the instruction register 16,
Performs complex scan operation and mode switching control.

In this embodiment, the JTAG scan type L is used.
Since SI30 is operated by the external scan method, JTA
The G signal suppress circuit 18, the control signal selection circuit 21, and the scan output selection circuit 22 are provided, and the test mode signal EX which is a scan method selection signal from the outside of the LSI 30 is provided.
The signal prevents a JTAG scan type signal from being input.

Further, in the present embodiment, at the same time, the operation modes of the scan clock generation circuit 20 and the input / output macro circuit 15 are set to values suitable for the external scan system to guarantee the same operation as the external scan system. There is.

That is, in this embodiment, by turning on the test mode signal input from the test mode signal input terminal EX of the LSI 30 (H level voltage),
The JTAG signal suppress circuit 21 uses the control signal generation circuit 18
From the instruction register 16 to the instruction register 16 in the non-operational state,
The register data from the register 16 to the control signal generation circuit 17 is set to the non-operation state.

At this time, in the scan output selection circuit 22,
By turning on the test mode signal input from the test mode signal input terminal EX of the LSI 30 (H level voltage), the scan chain is selected by the chain select signal from the outside of the LSI 30.

Further, in the control signal selection circuit 21, the LSI 3
When the test mode signal input from the 0 test mode signal input terminal EX is turned on (H level voltage),
By supplying the scan clock signal sent from the outside of the LSI 30 to the scan FF 11 via the gate circuit 23 and supplying the scan clock to the input / output macro circuit 15 by the chain select signal,
The operation mode of the input / output macro circuit 15 can be set to the same mode as the external scan method. (Operation of First Embodiment) Next, the operation of the first embodiment will be described with reference to FIGS.

In the explanation of this operation, FIG.
1 to 3 will be described with reference to the circuit diagram of FIG. Note that FIG. 7 is an operation explanatory diagram of the JTAG & external scan method.

In the operation explanatory view of FIG. 7, JTAG
Scan LSIs 31, 32 and JTAG / External scan L
SI33 is used. <External Scan Method> FIG. 4 shows the JT method by selecting the circuit block as to whether the LSI 30 operates in the external scan method or the internal control scan method JTAG method.
It is determined whether the AG scan circuit block or the external scan circuit block is selected (ST10).

Here, for example, as described above, J
When changing from the TAG scan method to the external scan method, the external scan method is selected and ST described below is selected.
After performing the setting of ST22 from ST20,
33, the printed wiring board on which the LSIs 31 to 33 are mounted is tested.

FIG. 5 is an explanatory diagram for explaining the operation when switching the circuit block from the JTAG scan circuit block to the external scan circuit block. ST in Figure 4
19, when the external scan circuit block is selected, a test mode signal is input to the test mode terminals EX of the LSIs 31 to 33 shown in FIGS.
Level voltage) (ST20).

In the operation mode generation circuit 19 shown in FIGS. 1 and 2, the test signal input terminal T for inputting the test signal is input.
M, an operation mode by inputting a test signal, a test mode signal or a printed wiring board test signal from a test mode signal terminal EX for inputting a test mode signal or a printed wiring board test signal input terminal PTM for testing a printed wiring board The generated output is input to the scan output selection circuit 22 or the control signal selection circuit 21.

At this time, in the test system circuit 10, the scan mode and the chain select are set,
Activate the scan chain (ST21). After activating this scan chain, set the scan-in value and set the scan A / B clock signal terminal to A /
A B clock voltage is applied (ST22). As a result, the external scan circuit block is operated to stop the operation of the JTAG scan circuit block.

That is, in the clock generation circuit 20 shown in FIGS. 1 and 2, the scan A / B clock signal input terminals A-CLK and B-CLK clocks shown in FIG. The A / B clock generation output is input to the control signal selection circuit 21.

On the other hand, in the instruction register 16 shown in FIG. 5 and the like, when the scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.

The control signal generation circuit 17 shown in FIG.
In addition, a state transition circuit (not shown) is operated by the test data-in signal TRST, the test clock terminal TCK, the test data-in signal input to the test mode selector terminal TMS, the test clock signal, and the test mode selector signal.

Therefore, in the control signal generating circuit 17, the test data-in signal, the test clock signal, and the test data input from the external device outside the LSI 30 to the test data-in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. By inputting the mode selector signal in a predetermined procedure,
The basic operating mode is set.

The control signal generation circuit 17 includes a state transition circuit (not shown) which operates by switching the mode information.
Input the value of the dedicated scan FF to the SI30 pin and
The control signal generated based on the value input to the pin of I30 is input to the scan output selection circuit 22 and the JTAG signal suppress circuit 19.

Further, in the present embodiment, since the JTAG scan type LSI 30 is operated by the external scan type, a diagram including the JTAG signal suppress circuit 18, the control signal selecting circuit 21 and the scan output selecting circuit 22 shown in FIGS. The test system circuit 10 shown in FIG.
By inputting the test mode signal to the test mode signal terminal EX, which is a scan mode selection signal from the outside of 0, and turning it on (H level voltage), the signal of the JTAG scan method is output from any of the input terminals of the LSI 30. LS
It can be prevented from being supplied to I30.

In this embodiment, the JTA is turned on by setting the test mode signal input from the test mode signal input terminal EX of the LSI 30 to the ON state (H level voltage).
The G signal suppress circuit 21 sets the control signal from the control signal generation circuit 18 to the instruction register 16 in a non-operating state, and sets the register data from the instruction register 16 to the control signal generation circuit 17 in a non-operating state. .

At this time, in the scan output selection circuit 22,
By turning on the test mode signal input from the test mode signal input terminal EX of the LSI 30 (H level voltage), the scan chain is selected by the chain select signal from the outside of the LSI 30.

Further, in the control signal selection circuit 21, when the test mode signal input from the test mode signal input terminal EX is turned on (H level voltage), the LSIs 31 to 31.
The clock signal for scanning sent from the outside of 33 is supplied to the scan FF 11 via the gate circuit 23, and the scan clock is supplied to the input / output macro circuit 15 by the chain select signal. The operation mode can be set to the same mode as the external scan method.

By performing the above processing, the LSI 31
33 to 33, a test mode EX signal, which is a scan mode selection signal, prevents a JTAG scan system signal from being input to the test system circuit 10, and externally scans the operation mode of the scan clock and the input / output macro circuit 15. The value suitable for the method is set to guarantee the operation as an external scan method.

For this reason, the external scan method in which a clock signal is supplied from an external circuit to perform an external scan and the IE
It is used by switching to the external scan circuit block in order to diagnose and test the LSI of the external scan system using both the EE-compliant internal control scan system (JTAG scan system).

As described above, by switching to the external scan circuit block for use, the system can be easily used even in a system in which scanning is performed by the external scan circuit block, and the system can be tested and evaluated quickly. <When JTAG scan method is selected> Next, S in FIG.
When the JTAG scan method is selected from the external scan methods at T10, the test mode signal input from the test mode signal input terminal EX is turned off (L level voltage) (ST31).

At this time, in order to activate the scan chain of the instruction register 16 shown in FIG. 6, the scan FF 11 is operated by the scan mode setting and the scan clock CLK signal of the control signal generation circuit 17 which is the TAP controller. Let

That is, in ST31, after the test mode signal input from the test mode signal terminal EX is turned off (L level voltage), the scan mode input to the instruction register 16 is activated to activate the scan mode. And set TAP
The control signal generation circuit 17 which is the controller is set (ST32).

While setting the scan mode, TA
After the control signal generation circuit 17 which is a P controller is set, the instruction register 16 is scanned by the instruction register 16. Therefore, an instruction (IR) code is set in the instruction register 16 and a test clock is generated in the control signal generation circuit 17. Terminal TCK
A test clock voltage is applied to the A / B clock terminal (ST33).

After setting the instruction (IR) code in the instruction register 16 and applying the test clock voltage from the test clock terminal TCK to the control signal generating circuit 17 to the A / B clock terminal, the scan mode is set and the chain is set. Set the select and activate the scan chain (ST3
3).

After the activation of the scan chain, the scan-in value is set and the A / B clock voltage is applied from the scan A / B clock signal terminal (ST3).
5). As a result, the internal scan circuit block is operated to stop the operation of the external scan circuit block.

That is, in the clock generation circuit 20 shown in FIGS. 1 and 2, the scan A / B clock signal input terminals A-CLK and B-CLK clocks shown in FIG. Input A / B clock signal.

On the other hand, in the instruction register 16 shown in FIG. 6 and the like, when the scan-in signal is input from the scan-in SI input terminal, the register output is supplied to the JTAG signal suppress circuit 18.

The control signal generation circuit 17 shown in FIG.
In addition, a state transition circuit (not shown) is operated by the test data-in signal TRST, the test clock terminal TCK, the test data-in signal input to the test mode selector terminal TMS, the test clock signal, and the test mode selector signal.

Therefore, in the control signal generation circuit 17, the test data-in signal, the test clock signal, and the test data input from the external device outside the LSI 30 to the test data-in terminal TRST, the test clock terminal TCK, and the test mode selector terminal TMS. By inputting the mode selector signal in a predetermined procedure,
The basic operating mode is set.

The control signal generating circuit 17 includes a state transition circuit (not shown) which operates by switching the mode information.
Input the value of the dedicated scan FF to the pin of SI30. Further, in the present embodiment, since the external scan type LSI 33 is operated by the internal control scan type, the configuration shown in FIG. 3 including the JTAG signal suppress circuit 18, the control signal selecting circuit 21 and the scan output selecting circuit 22 shown in FIGS. By providing the test system circuit 10 shown, a test mode signal terminal EX which is a scan system selection signal from the outside of the LSI 30
By turning off the test mode signal without inputting the test mode signal (L level voltage), the signal of the JTAG scan system is supplied to the LSI 31 from any of the input terminals of the LSI 31 to 33.
To 33.

In this embodiment, the test mode signal not input from the test mode signal input terminal EX of the LSI 33 is turned off (L level voltage).
The JTAG signal suppress circuit 21 uses the control signal generation circuit 18
The control signal from the instruction register 16 to the instruction register 16 is set to the operating state, and the register data from the instruction register 16 to the control signal generating circuit 17 is set to the operating state.

Further, in the control signal generation circuit 17, when the test mode signal not input from the test mode signal input terminal EX is turned off (L level voltage), the LSI
By supplying a scan clock signal sent from outside 31-33 to the scan FF 11 via the gate circuit 23 and supplying a scan clock to the input / output macro circuit 15 by a chain select signal,
The operation mode of the input / output macro circuit 15 can be set to the same mode as the external scan method.

By performing the above processing, the LSI 31
No. 33 to 33 does not apply the test mode EX signal, which is the scan mode selection signal, to prevent the signal of the external scan system from being input to the test system circuit 10, and the scan clock and the input / output macro circuit. The operation mode of 15 is set to a value suitable for the internal control scan system to guarantee the operation as the JTAG scan system.

Therefore, in order to diagnose and test the LSI of the internal control scan system by using the internal control scan system (JTAG scan system) conforming to IEEE, the internal control scan circuit block is used by switching.

As described above, by switching to the internal control scan circuit block and using it, the system can be easily used even in a system in which the internal control scan circuit block scans, and the system can be tested and evaluated quickly. Modified Example 1 of Example 1 [Outline of Modified Example 1 of Example 1] As a modified example 1 of the first example, a test of a printed wiring board on which an LSI is mounted is tested. When the test method of this printed wiring board is different, the circuit block is switched to either the external scan method or the internal control method to perform the test. [Modifications of First Embodiment] In FIG. 1 and FIG. 2, when the printed wiring board is tested, the printed wiring is first made from the printed wiring board test terminal PTM of the operation mode generation circuit 19 of the test circuit 30. A board test voltage is applied to, for example, an LSI pin to perform an insulation test on the printed wiring board.

When the printed wiring board is tested by the external scan method, for example, the external scan circuit block of FIG. 5 is operated from ST20 to ST22 of FIG. 4 to perform the insulation test of the printed wiring board.

On the other hand, when the printed wiring board is tested by the internal control scan method, for example, the internal control scan circuit block of FIG. 6 is operated from ST31 to ST35 of FIG. 4 to perform the insulation test of the printed wiring board.

As described above, by switching the circuit block to either the external scan system or the internal control system, even a printed wiring board operating in the external scan system or a printed wiring board operating in the internal control scan system can be used. It can be tested whether it works properly. (Modification 2 of Embodiment 1) [Outline of Modification 2 of Embodiment 1] As a modification 2 of the first embodiment, a test of the entire system is performed.

When the test method of the entire system is different, the circuit block is switched to either the external scan method or the internal control method to conduct the test. [Contents of Modified Embodiment 2 of First Embodiment] In FIGS. 1 and 2, when testing the entire system, first, the entire system test terminal provided in the operation mode generation circuit 19 of the test circuit 30 is connected to the entire system test terminal. A test voltage for the entire system is applied from (not shown).

Further, for example, in the case of testing whether or not the entire system operates normally by the external scan method, the case shown in FIG.
The external scan circuit block of ST20 to ST2 in FIG.
Operate up to 2 to test, for example, whether the entire system is properly insulated.

On the other hand, in the case of testing whether the entire system is normally insulated by the internal control scan method, the internal control scan circuit block of FIG.
Test that the entire system is normally insulated by operating from 31 to ST35.

As described above, by switching the circuit block to either the external scan system or the internal control system, the insulation test is normally performed even in the system operating in the external scan system or the system operating in the internal control scan system. You can do such tests.

[0108]

According to the first aspect of the present invention, by switching and using both the external scan circuit block and the JTAG scan circuit block, by using this test device, the external scan circuit block can be moved horizontally or vertically. It can also be used in a system that scans or in a system that scans horizontally or vertically with a JTAG scan circuit block, so you can quickly switch to the external scan circuit block and the JTAG scan circuit block according to the target electronic component, and it is easy to use. It is possible to obtain the effect of being able to improve.

According to the second invention, the semiconductor integrated circuit which is the target electronic component and the printed wiring board on which the semiconductor integrated circuit is mounted can be quickly diagnosed and tested according to the printed wiring board on which the semiconductor integrated circuit is mounted. It is also possible to obtain the effect that diagnosis and testing can be performed.

On the other hand, according to the third aspect of the invention, when the voltage according to the test mode is applied to the test mode terminal, the scan range is set to the range in which the target electronic component is scanned in the horizontal direction or the vertical direction. Section, and in response to the setting signal set by the scan range setting section, the external scan circuit block scans the target electronic component horizontally or vertically to diagnose or test the target electronic component. You can get the effect that you can quickly.

Further, according to the fourth invention, when the voltage according to the test mode is not applied to the test mode terminal, the circuit block adapted to the system adopting the so-called internal control scan system is promptly switched to, It is possible to diagnose and test target electronic components.

Further, according to the fifth invention, by providing the printed wiring board test terminal for testing the printed wiring board, the printed wiring board can be tested smoothly.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a circuit outline of an embodiment of the present invention.

FIG. 2 is a detailed circuit diagram of an embodiment of the present invention.

FIG. 3 is a detailed circuit diagram showing a main part of the embodiment of the present invention.

FIG. 4 is a flow chart for explaining the operation of the first embodiment of the present invention.

FIG. 5 is an operation explanatory diagram of an external scan system that is an example of an embodiment of the present invention.

FIG. 6 is an operation explanatory diagram of an internal control scan method which is an example of an embodiment of the present invention.

FIG. 7 is an operation explanatory diagram of the embodiment of the present invention.

FIG. 8 is a circuit diagram of a conventional test circuit.

FIG. 9 is a flowchart of a conventional test circuit.

FIG. 10 is a circuit diagram of a conventional test circuit.

FIG. 11 is a flowchart of a conventional test circuit.

[Explanation of symbols]

 10 test system circuit 11 scan FF 15 input / output macro circuit 16 instruction register 17 control signal generation circuit 18 JTAG signal suppression circuit 19 operation mode generation circuit 20 clock generation circuit 21 control signal selection circuit 22 scan output selection circuit 23 gate circuit 30 switching Circuit 31 JTAG scan LSI 32 JTAG scan LSI 33 JTAG / external scan LSI

Claims (5)

[Claims] 1. An external scan circuit block for supplying a clock signal for testing a target electronic component in accordance with a signal sent from an external device from the external device, and an internal control signal supplied from a control circuit inside the circuit. In an apparatus for diagnosing and testing the target electronic component by using an internal control scan circuit block that controls the inside of the circuit to test the target electronic component, both the external scan circuit block and the internal control scan circuit block A circuit block switching circuit to be used by switching to, the circuit block switching circuit, when performing the diagnosis or test of the target electronic component using the external scan circuit block, the target electronic component to be diagnosed or tested. To scan, set the external scan setting section according to the external clock signal and set the external scan When the target electronic component is diagnosed or tested using the internal control scan circuit block, the target electronic component to be diagnosed or tested is scanned, and is sent from the internal control unit. A test device that switches to the internal control scan circuit block that is set by the internal control scan setting unit by a control signal. 2. The test apparatus according to claim 1, wherein the target electronic component is a semiconductor integrated circuit and a printed wiring board on which the semiconductor integrated circuit is mounted. 3. In the circuit block switching circuit, when a voltage according to a test mode is applied to a test mode terminal, a scan range setting unit sets a range for scanning the target electronic component, and the scan range setting unit sets the scan range. The test apparatus according to claim 1, wherein the external scan is performed in response to a setting signal set by the unit. 4. The circuit block switching circuit scans the target electronic component based on an internal control signal sent from the internal control section when a voltage according to a test mode is not applied to a test mode terminal. The test apparatus according to claim 1, wherein the target electronic component is diagnosed or tested. 5. The test apparatus according to claim 1, wherein the circuit block switching circuit is provided with a printed wiring board test terminal for testing a printed wiring board.