JP3072718B2 - Test method for an integrated circuit having a large number of I / O signals - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates to a current state of the art test environment and integrated circuit (IC) having a greater number of input / output (I / O) cells than the test head supports. Test method.

[0002]

BACKGROUND OF THE INVENTION Numerous different test methods are known in the art for testing integrated circuits (ICs) of all integration levels, such as LSI, VLSI, ULSI.
For a long list of references in this technical area, VD
"Test Generation for VLSI" by Agrawal, SCSeth
Chips ", IEEE Computer Society Press 1988, must be mentioned, but includes references to many important publications.

[0003] A particular class of test methods, called design for testability, targets the controllability and observability of ICs that are already in the design stage. The following methods can be used. ■ Testability analysis ■ Segmentation ■ Built-in self-test ■ Scan design

For an overview of these methods, see, for example,
W. Williams, KE Parker, "Design for Testability
-A survey ", Proc. Of the IEEE, Vol. 71, No 1, 198
See 3, pp. 98-112. In the scan design approach, the categories of approaches can be further distinguished as follows. ■ Joint Test Actio describes the scanning path technology and the method of extending this technology to the boundary scanning architecture.
IEEE Standard STD11 by n Group (JTAG)
It is standardized as 49.1 and is publicly available as a document from the IEEE. In addition, a thorough and up-to-date discussion of the boundary scan approach is given in CMMo
"The Test Access Port and by RETulloss
Boundar y-Scan Architecture ", IEEE Computer
Provided by Society Press 1992. ■ Level Sensitive Scan Design (LSSD) Level Sensitive Scan Design (LSSD) is described in, for example, "A Logic Design Struct" by EB Eichelberger.
ure for LSI Testabilit y ", Proceedings of
the Design Automation Conference No.14, 20-2
2, June 1977, New Orleans, Lousiana. For a comprehensive list of patents and publications relating to the testing of electronic structures based on this technology, see US Pat. No. 4,591,078, US Pat. No. 4,428,060, and “A Survey of Design f
or Testability ScanTechniques ", VLSI Desig
n, December 1984, pp 38/61. ■ Scan / set technology ■ Random access approach

[0005] All of these approaches can be used alone or in combination with other techniques. The gist common to all of these scanning design approaches is:
The use of multiple controllable / observable points inside the IC. Controllability is controlled by the shift register latch (SR
L) by serially shifting the data to the point constructed by L). Next, execute the test. S
The data stored in the RL is then shifted back to observe it. Thus, control and observation of the IC is independent of the number of pins in the package. Further, since the latch itself is part of the internal circuit, it can be used to break the feedback path of the sequential circuit, thereby automatically testing the combinational circuit during SRL.

In a typical scan design, shift registers are located at specific points required for a design function, but they are linked in a scan chain for test purposes. This scan chain allows any test state to be realized in the register when used for test purposes. Next, a test pattern is generated on a computer. The generated test pattern is
RL, add test vector (selected word or group of digital data) to primary input or pin of chip, apply system clock to perform test, compare primary output pin with expected vector output The data is then scanned out of the SRL and compared to a known good test vector. When performing this test, many test vectors are typically required to shift the SRL, apply the test vectors, and shift the results back.

[0007]

Some difficulties arise with current approaches to testing. The above described approach for testing with the architecture cannot test all possible types of defects. ICs have a very large number of input / output (I / O) cells,
These may also be bidirectional with driver and receiver logic. The test procedure described above provides a complete AC / C to detect a complete list of possible IC defects, such as stack defects, delay defects, floating line defects, bridging defects, short circuits, open leakage currents, impedances, etc.
Does not support DC and parameter test spectrum testing.

Another problem with the current approach to testing is that the number of I / O signals on the IC and the corresponding number of I / O cells that must be analyzed for all types of defects are increasing. Occur. One of the causes of the increase in the number of I / O cells is an improvement in the degree of integration. For example, if the level of integration is from LSI or VLSI to U
By migrating to an LSI, the number of I / O cells easily exceeds 1200. In addition, technology is moving to a multi-chip module (MCM) approach. According to this approach, an MCM with a possibly moderate number of I / O cells is assembled from individual chips. Since these chips are designed for use within the MCM, they utilize a vast number of I / O signal counts, including a wide data bus within the MCM. is necessary. Thus, future ULSI chips designed to take advantage of the MCM will have a much higher number of I / O signals than chips designed for single chip module (SCM) applications.

Before assembling these ULSI chips in an MCM environment or other environment, the chips must be tested for all kinds of defects. Modern test environments currently available are designed to test standard SCM. Therefore, the standard SCM
Is limited to testing chips embedded in the SCM and having an I / O signal count of a range of 400 I / O cells. To enable testing of these ULSI chips, a special purpose SCM supporting a large number of I / O signals has been designed and this new SCM has been designed for testing purposes.
A ULSI chip must be embedded in M. I /
Many difficulties and obstacles are expected due to the mechanical and electronic hurdles associated with the large number of O signals. Also, these new SCMs are expected to support only specific chip family tests and do not provide a solution to common problems. To make matters worse, in the course of technology development due to increased integration density, the rate of increase in the number of I / O cells per chip is less than that of SCM-based test technology, which is limited by macroscopic and mechanical constraints. fast.

As a result, ULSI chip testing and test environments based on current approaches are becoming more and more expensive due to the increased number of I / O signals.

[0011] Objects of the present invention relating to IC testing are:
It is to provide a new kind of test approach for ICs with I / O signal counts that far exceed the number of I / O signals supported by the current SCM test environment. The present invention helps eliminate the need to build special purpose SCMs to test such ICs.

[0012]

The test method of the present invention comprises:
A large number (N) of input / output (I) embedded in a chip module (eg, SCM) supporting M signal lines
/ O) enables testing of one or more integrated circuits (ICs) having signal lines. In particular, the number M of signal lines of the chip module is the number of I / Os to be tested with this IC.
If the number of cells is smaller than N, this test method can be applied. For testing purposes, the above IC is
Assume that it has controllable and observable test latches. The N I / O cells are connected to the internal structure of the IC via the test latch. The test method includes a test latch, and N number of I I's connected to the internal structure of the integrated circuit via the test latch.
/ O cells, and the test method includes the N I / O cells.
Grouping the O signal lines into up to M subgroups, connecting each of the subgroups to one of the M I / O signal lines of the chip module, and analyzing the integrated circuit Storing the test pattern in the test latch or supplying a test signal to one or more I / O signal lines; and the sub-group. Activating one subset of the I / O cells in each of the I / O cells and deactivating the remaining I / O cells; and After transmitting the pattern, the I / O
Comparing the signal received on the / O signal line with the expected signal or comparing the resulting test pattern in the test latch with the expected result test pattern.

All I / O cells of one subgroup are dotted and thus require one I / O signal line to transfer test signals in a test environment. It is this concept that greatly reduces the number of I / O signal lines required. Separate signal lines are only needed for subgroups, and the test requirement to use one signal line for one I / O cell is now obsolete.
Therefore, the larger the subgroup (the larger the number of I / O cells), the smaller the number of signal lines required to exchange I / O signals in the test environment. Another advantage of the present invention is due to the teaching of the activation / deactivation sub-step. This allows I / O to participate in the current test activity at each hour.
The O cell can be selectively controlled. Thus, due to this extensive control capability, all subgroups can be tested and analyzed in parallel, or they can be tested in series. As yet another advantageous feature, the present invention allows for the testing of complete ICs as well as circuits between pins and test latches.

Test all possible test patterns
Another advantage of the present invention is achieved by sequentially applying to the latch and I / O signal lines, and the test method provides a complete IC with I / O cells that fully fulfills functional behavior. It can be tested in state. It is also possible to selectively activate or deactivate any subset of I / O cells within each subgroup for testing purposes. Therefore, a complete test of all I / O cells and the entire IC can be performed.

The test pattern stored in the test latch is used not only for inputting a test input to the I / O cell but also for turning on and off the I / O cell. The procedure is greatly simplified. First,
The available means can be used without having to introduce new physical features. Second, the test method can be simplified because the storage and activation / deactivation sub-steps can be combined.

Existing techniques, such as a scan design architecture, can be used for the new purpose of powering / deactivating I / O cells. Either approach can provide this type of control at a very broad level, and can selectively activate / deactivate each I / O cell within each subgroup.

[0017]

BEST MODE FOR CARRYING OUT THE INVENTION

1 Preface The following description is intended to provide an overview in a multi-chip module (MCM) environment, but as noted above, does not limit the invention in any way.
The MCM environment is just one of the environments in which the present invention can improve testability. Also, according to the present invention, this is achieved in a boundary scan (BS) test environment. The present invention is completely neutral with respect to a particular "design for testability" technology, so it can be applied to any test technology that allows control and observation of a given IC. Thus, where the present invention is described with reference to a scan register, any other type of test latch or test cell may be used instead to implement the present invention. Similarly, while the following description focuses on a particular type of I / O cell having the properties of a bidirectional driver / receiver (BIDI), the present invention is directed to any other type of I / O cell. Can also be used for testing. BIDI is only mentioned as one possible example of an I / O cell. BIDI below
The terms and and the I / O cell are used interchangeably.

The present invention, which is described below, is a method for testing a chip having multiple input / output (I / O) signals. This type of chip is, for example, a ULSI chip that is very important for use in a multi-chip module (MCM). Before assembling the MCM, each chip must undergo a thorough test for its digital and parametric (analog) behavior. In addition, each chip must undergo various stress tests, such as thermal cycling (burn-in) tests, to ensure high chip quality.
Only after all stress cycles and test procedures are the quality of these chips guaranteed and the chips ready for assembly into the MCM.

Due to advances in integration technology, future chips, especially those designed for use in MCMs, will have much more than conventional chips designed for use in single chip modules (SCMs). Indicates an I / O signal. For example, a chip designed for MCM use is M
Use the benefits of large I / O signal counts to achieve a wider data bus within the CM or to communicate with external chips. Another important advantage of these MCM designs is the shorter interconnect length. The result of these approaches is a significant performance improvement over SCM designs with a moderate number of I / O signal counts.

Before incorporation into the MCM, all chips must exhibit the same high quality level. Since the number of chip replacements within an MCM is severely limited, each chip cannot be tested in an MCM collection. Further, for example, it is impossible to access all I / O signal lines in the MCM, and on a wafer, for example, an AC test cannot be performed due to a large number of I / O counts. As such, the complete set of tests described above cannot be performed in an MCM environment. Therefore, each chip must be tested in the SCM environment. Due to the large number of I / O signals in ULSI chips, inexpensive standard SCM technology cannot be used to apply a complete test. In the absence of the present invention, the need to test SCMs with a large number of I / O signals has created a need to upgrade SCM technology to large, expensive and very specialized SCMs.

2 New Test Method In the following description, we will focus on the I / O cell test procedure only. This is because testing a complete I / O cell is not supported by other test methods. Of course, the method of the present invention can also be used to test the internal system logic of a chip.

As an example of a testability design approach,
FIG. 1 schematically shows a state on the IC 100. All ICs according to IEEE Standard 1149.1 have a Boundary Scan Register (BS Cell) 102 as a test latch for testing all interconnects and internal system logic 101.
To 107 must be included. For controllability and observability purposes, test patterns can be written to and read from test latches 102-107 by serially clocking data along scan path 110. These test latches must be located between various types of I / O cells and internal system logic. That is, the test latch corresponds to {between each system input cell (clock or data) 111 and a corresponding input to the on-chip system logic 101} and {each output from the on-chip system logic 101}. Between the system output cell 112,
It must be located between each output from the on-chip system logic 101 and the corresponding three-state system output cell 113 or bidirectional control I / O cell 114.

As mentioned above, the present invention uses any type of test latches 102-107 to implement internal system
Logic 101 and many I / O cells 111 to 114
And how to test it. Testing of internal system logic 101 with test latches is well known in the art, so the focus here will be on testing I / O cells. Of course, the test method proposed here can also test internal system logic. In addition, to handle the most complex cases,
Handles state bidirectional I / O cells. The ability to test such I / O cells also encompasses the ability to test all other types of I / O cells.

The bidirectional driver /
An overall image of the receiver I / O cell (BIDI) is shown as a model in FIG. FIG. 2 shows a BIDI 200 and its various signal lines. On the right side of the block 200, a common input / output line 201 is shown, which connects the IC to an external circuit. On the left, wiring to the internal system logic 101 is shown. This includes a path 202 for data received from outside the IC, a path 203 for data-in from inside the IC, and an I
A path 204 for high impedance (HZ) control from inside C is included.

As mentioned above, each BIDI, including the driver and receiver, must be tested for its AC, DC and parameter characteristics, as well as for the various defects mentioned above, following a full stress test (burn-in, etc.). have to receive. To this end, FIG. 3 shows the configuration circuit of BIDI together with its corresponding test latch in more detail. FIG. 3 shows the same signal line according to FIG. On the left are the lines 202 to 204 already mentioned. On the right side, a common input / output line 201 is shown. Wire 201 is connected to the test environment for BIDI testing purposes.
The actual BIDI cell is indicated by block 300, which includes an I / O cell driver 301 and a receiver 302.
including. FIG. 3 also shows a test latch 30 for the purpose of testing the observability and controllability of this BIDI.
3 to 305. These test latches support BIDI testing using signals on lines 202-204 connected to internal system logic. The test latches 303-305, which are preferably implemented as boundary scan registers (BS cells),
The function of testing the DI driver 301 and the receiver 302 is performed. An arbitrary test pattern can be externally supplied to the test latch, and conversely, an arbitrary test pattern stored in the test latch as a result of a test operation of the IC or its components can be externally supplied. can do. For example, a test latch 303 may be used to supply a signal from the internal system logic of an IC to BIDI 300. Test latch 305 allows BIDI 300 to receive the results of externally collected signals. Finally, test latch 304 can store a test pattern that causes BIDI 300 to operate as a receiver cell by setting driver 301 to HZ mode.

In an actual method of testing an IC including I / O cells, the number of I / O cells and their corresponding I / O connections is supported by standard chip modules (eg, SCM) and test environments. Situations that exceed the number of connected connections. An overview of the test method of the present invention can be summarized in the following main steps, each of which is described in detail in the following sections. (1) The signal lines of the IC are grouped into a plurality of subgroups, and each subgroup is constituted by one, two or more I / O signal lines of the IC. (2) Connect each I / O cell in each subgroup to one I / O signal line of a chip module (for example, SCM) by dotting. (3) IC by performing the following sub-steps
To analyze. (3-1) The test pattern is stored in the latches 303 to 305 of one, two, or more I / O cells. (3-2) Line 2 of 1, 2 or more I / O cells
01 potentially supplies an external signal. (3-3) Driver / receiver configuration of one, two or more I / O cells so that only a subset of I / O cells in each subgroup that do not interfere with test results are enabled for test purposes. Energize the element and the remaining I /
Deactivate the O cell. (3-4) For analysis, transfer the data received in the test latches 303 to 305 after the test cycle of the I / O cell to the outside. (3-5) Receiving a signal generated on an output line 201 by an I / O cell after a test cycle for analysis in a test environment. (4) All test patterns of interest and all subgroups of interest and their constituent I
Repeat analysis step (3) for / O cells.

2.1 Grouping I / O Signal Lines into Subgroups If the IC chip having a large number (N) of I / O signal lines to be tested is a standard chip module (eg, a standard SCM) Embedded in this module
Assuming that only N) signal lines are tested, the present invention proposes to divide the N I / O lines of this chip into subgroups. Each of these subgroups is connected to a separate connection of the M I / O signal lines of the chip module. Thus, for this chip module, each subgroup has one I / O
Because it is treated as an O signal line, this approach allows the IC to be considered as having a much smaller number of I / O cells than it actually is. Of course, the set number of subgroups does not exceed the number M of signal lines supported by the chip module. In the present invention, there is no limit on the number of I / O cells to be combined into a subgroup. However, depending on the test, the subgroup may be 1, 2
Alternatively, the number of I / O cells may be limited to an integer number other than this. As a result of the electrodynamic behavior of the subgroups, certain practical limits are imposed by the I /
It may be added to the number of O cells. For example, as the number of components in a subgroup increases, the total capacity of that subgroup may increase, reaching a limit that is no longer acceptable for testing reasons. As will be apparent from the following description, there is an interest in reducing the number of components in a subgroup, as the test time is reduced by minimizing the number. According to this teaching, each subgroup represents one I / O cell of the chip and is therefore operated on the chip module and the test head of the test environment. Therefore, I in each subgroup
It is necessary to provide a configuration for preventing uncontrolled interference of the / O signal line. These configurations are discussed below in “ICs and their I
/ O cell analysis ".

2.2 I / O in each subgroup
Cell Dotting According to the above description, one chip to be tested is integrated into a chip module (eg, a single chip module (SCM)) for testing purposes. During this procedure, the signal lines of these I / O cells, which are coupled to form individual subgroups, are connected together, and finally each subgroup has its chip module (ie, SCM)
Can be controlled and observed through one of the pins. Realistic I / O dots range from 2 to 4 I / O cells. As a result, a specially customized chip module according to the present invention using standard technology having a standard size that includes a standard number of I / O pins may require a state-of-the-art chip module. Compared to,
More than two to four I / O signals can be supported for test purposes.

This dotting step will be apparent from the example of FIG. The "L" BIDIs 401 to 403 are combined to form one of the subgroups described above. This grouping is realized by dotting the common I / O lines 405 to 407 (shown by broken lines 409) to form one common I / O line 408 for the subgroup.

Thus, for this description, the numbers N, M and L
Has the following meaning. Total number of I / O signal lines of NIC M Total number of I / O signal lines of chip module (M
≦ N) = maximum number of different subgroups L Number of IC I / O signal lines in one subgroup = number of different DI signal lines (“for I / O cell activation / deactivation” The features of this preferred implementation of the dotting process are illustrated more particularly in FIG. 6, which illustrates how the signal lines of the aforementioned sub-group of IC 607 can be modularized. 60
4 are connected to the individual I / O pins.

FIG. 6 shows a module 604, which can be used as a test device to implement the new test method disclosed in this application. The signal lines 601, 602, 603, 6 on the upper side 605, that is, on the internal chip / module surface of the module 604.
The integrated circuit 607 having 14 is attached to the module 604. The signal lines 601, 602, 603, 614 are lines 611, 6 which are electrical I / O lines on the module 604.
12, 613 and 610. In case a) of FIG. 6, the lines 611, 612, 613 are dotting in a "fork-like" configuration and the I / O signal lines 601, 602,
Reference numerals 603 each form one subgroup.
In the case b) of the dotting structure, the I /
Although one I / O signal line 614 of the O cell is connected to one signal line 610 of the module 604, the “fork area” 620 can make another contact with the IC.

Of course, the layout of the fork area can have a great many variations. For electrodynamic reasons, it is advantageous to have the fork area close to the surface 605, but this will reduce, for example, the amount of signal reflection. Further, any number of lines of the IC 607 may be dotted to share a common external line on the external chip module surface 606. For the test method of the present invention, all lines of one fork area on module
It is not necessary to dotting, that is, connecting with the signal line of one I / O cell. In case a) of FIG. 6, line 611,
Only two of 612 and 613 may be connected to the signal line of the integrated circuit to be tested. In that case, the third line is not used. This fact has no negative impact on the test procedure. Which line of the module is to be dotted with the corresponding line of the IC depends on the pin layout (footprint) of the integrated circuit. Based on this background, 611, 612, 613, 609,
610, 615, it is possible to provide a module with a fork area providing an excessive number of possible connection lines, so that not only one type of IC but also a plurality of I
A complete family of C can be supported. Such a module 604 would be suitable for use as a generalized module with a flexible and universal footprint that can hold many different ICs.

2.3 Analysis of the IC and its I / O cells According to the above description, each subgroup of I / O cells of the IC to be tested is external to the chip module (ie, SCM) holding the chip. Are modeled as one I / O connection. Thus, to obtain a clear test result, the test method of the present invention activates the relevant subset of the I / O cells of the individual subgroups according to the individual test objectives and the remaining I / O cells. It requires a control step to deactivate the / O cell. Previously, we emphasized that this description (not the invention) is limited to tests related to the I / O cells of the IC. Repeating our previous position, we point out that this test method itself can also be used to test the internal system logic of an IC. For testing I / O cells, two test modalities must be identified. ◆ Output test mode for I / O cell output behavior ◆ Input test mode for I / O cell input behavior Of course, I / O cells must be tested in all modes in which they operate in the chip. Must.

The description of the test method will be limited to only one subgroup. All other subgroups of the I / O cells of the IC must be tested in a similar procedure. In this regard, two alternative approaches are possible.
That is, all subgroups are tested and analyzed in parallel, or they are tested in series, which requires longer test time. The test method also allows some I / O cells to be tested in an input test mode while others are tested in an output test mode.

2.3.1 Output Test Starting with the description of the output test mode for a subgroup of I / O cells, it is necessary to store a particular test pattern in a test latch in the first test step. is there. The objectives of the steps are manifold. One reason is to generate a constant controlled signal pattern that enters the BIDI. Another reason is that the test latch is reset to a known controlled state, and the data 411, later received by the I / O cell and stored in the test latch,
421 and 431 can be accurately determined. If the test latch is implemented in accordance with a scan design architecture based on the BS architecture, as in the case of the preferred embodiment of the present invention, the test pattern will test the test pattern serially along a scan path, such as 110. Shifting to the latch allows easy storage in the shift test latch. With respect to FIG. 4, this means that the particular signal test pattern is designated as "data in" lines 410, 420, 430, "received data" lines 411, 421, 431 and "HZ control" line 4.
12, 422, 432.

In this output test mode, people respond 405 to 4 of various I / O cells of the same subgroup.
07 is concerned with avoiding the interference, since at the level of the test environment these signals are a single common signal 40
This is because it is interpreted as 8. Thus, for controllability and observability reasons, the test method ensures that only a precisely defined subset of the I / O cells of a subgroup is activated and the remaining I / O cells of that particular subgroup are
The / O cell must be deactivated. Only in such situations can it be deduced which I / O cell is responsible for the signal 408 detected in the test environment. In a standard situation, this means that only one I / O cell is energized, so that the output signal 408 resulting from the test can be identified as being for this particular I / O cell. . On the other hand, test situations are also possible in which a subset of I / O cells, rather than just one, can be activated.

In the output test mode, the activation is BIDI
Disable means to disable the driver 301 and thus operate at the level of the receiver 302. The next step in this test method, the activation / deactivation of subgroup I / O cells, can be easily accomplished by using the "HZ control" signal of the individual I / O cells.
By simply enabling or disabling the "HZ control" signals 412, 422, 432, the BID
I401, 402, 403 can be energized (operate in drive mode) or deactivated (operate in receiver mode). "H" is applied to the activation / deactivation of the I / O cell.
Using the "Z control" input signal achieves the effect of interest. This approach allows the activation / deactivation state to be controlled by the test pattern already stored in the test latch. It should be noted that this approach allows for activation / deactivation control at the coarsest level (based on individual I / O cells).
A further extension of the test method in the output test mode is to use the fact that the deactivated I / O cell acts as a receiver to deactivate the generated output signal 408 of the activated I / O cell. I / O cell that can be used as an input of the
Can be performed together with the activated I / O cell driver 301.

After the required processing operation of the I / O cell, the operation result is analyzed in the next step of the test method. During the output test mode of the test method, a subgroup occurs and the output signal 40 received by the test head of the test environment.
8 must be compared with the expected result of a defect-free I / O cell. After the subgroup test cycle, the resulting test pattern stored in the test latch must optionally be transferred outside the IC. For example, in situations where deactivated I / O cells are to be tested with respect to their receivers 302 as outlined above, the resulting test pattern analysis is important. As mentioned above, if the test latch is implemented according to a scan design architecture as in the preferred embodiment of the present invention based on the BS architecture, the resulting test pattern will be tested along a scan path such as 110. -It can be easily transferred outside the chip and SCM by shifting in series from the latch. In the next step of the test method, the same activated I / O cell can be tested with other possible test patterns. Similarly, in the next step of the test method, all preceding test steps are applied to all other I / O cells that require testing by changing the activation / deactivation pattern in the subgroup. Can be repeated.

2.3.2 Input Test Proceeding to the description of the input test mode of the sub-group of I / O cells, it is necessary to store a specific test pattern in a test latch in the first test step. is there.
The purpose of this step is manifold. One reason is to generate a constant controlled signal pattern, which feeds into BIDI. Another reason is that testing
Resetting the latch to a controlled known state, which allows the I / O cell to later accurately determine the data 411, 421, 431 stored in the test latch. If test latch is BS
If implemented according to a scan design architecture as in the preferred embodiment of the invention based on the architecture,
The test pattern can be easily stored in the shift test latch by serially shifting into the test latch along a scan path such as 110.
With respect to FIG. 4, this means that the particular signal test pattern is designated as "data in" lines 410, 420, 430, "received data" lines 411, 421, 431 and "HZ control" line 4.
12, 422, 432. This test step corresponds to a similar step in the output test mode.

Since external input signals must be processed by the subgroup of I / O cells, such signals are tested via the test head along signal line 408 in the next step of the test method. Must be supplied from the environment. In this input test mode, since all I / O cells receive the same external input signal 408, there is no danger that the responses of the various I / O cells may interfere. Therefore, for the controllability and observability reasons of this test method, it is sufficient, at least in the standard case, to activate all I / O cells in the subgroup. In input test mode, the activation is BI
It has the meaning of disabling the DI driver 301 and thus operating at the level of the receiver 302. On the other hand, test situations are possible where only a subset of the I / O cells are activated and the rest are deactivated. The next step in the test method, the activation / deactivation of subgroup I / O cells, can be easily accomplished by using the "HZ control" signal of the individual I / O cells. The BIDIs 401, 402, 403 can be energized simply by using the "HZ control" signals 412, 422, 432 (operation in receiver mode). I / O
Using the "HZ control" input signal to activate / deactivate the cell achieves an interesting effect. This approach allows the activation / deactivation state to be controlled by the test pattern already stored in the test latch. The coarsest level (individual I
It should be noted that activation / deactivation control (based on / O cells) is possible. After the required processing operation of the I / O cell, the operation result is analyzed in the next step of the test method. The result test pattern stored in the test latch after the subgroup test cycle must be transferred out of the IC and compared with the expected result pattern. As mentioned above, if the test latch is implemented according to a scan design architecture as in the preferred embodiment of the present invention based on the BS architecture, the resulting test pattern will be tested along a scan path such as 110. -It can be easily transferred outside the chip and SCM by shifting in series from the latch. In the next step of the test method, the same activated I / O cell may be tested with other possible external signal patterns 408. Similarly, in the next step of the test method, all the preceding test steps are applied to all other I / O cells that require testing by changing the activation / deactivation pattern in the subgroup. Can be repeated.

2.4 Other Approaches to I / O Cell Activation / Deactivation Typically, BIDI provides another input signal, the so-called "driver inhibit (DI)" signal line. By the DI signal
The BIDI driver 301 can be blocked, or deactivated. Therefore, by using this DI signal, BIDI can be switched between the driver operation mode and the receiver operation mode. The present invention proposes to use the BIDI DI concept for the I / O cell activation / deactivation step in this test method.

The largest subgroup of I / O cells is "L
) Components (in the standard case, all subgroups contain the same number of I / O cell components, but this is not required by the present invention). For example, by using the DI signal to control the activation / deactivation of the BIDI, {by adding n control signal lines for transferring the required DI signal,} each of these control signal lines Connect these control signal lines to the DI input of at most one I / O cell so that none of the I / O cells are connected to more than one of the "L" control signal lines. This can be done by connecting. "L"
This connection makes it possible to control the activation / deactivation state of all I / O cells in all subgroups based on the control signal lines.

"HZ control" of BIDI proposed in the previous section
Compared to an activation / deactivation control mechanism based on the use of an input signal, there are further differences in this new approach. In this new DI approach, the I / O cell activation / deactivation step can be performed independently of loading the test latch with a test pattern, and this is affected by the contents of the test latch. Not done. Further, another control signal line is required to be accessible from the test environment to the outside. Finally, the DI approach is not as coarse as the HZ approach, because typically each control signal line has several I / O cells (at most one I / O cell in each subgroup). / O cell)
Is simultaneously controlled.

FIG. 5 shows an example of the DI approach. M subgroups 501 to 502 of I / O cells
Is controlled by setting a DI signal. In each subgroup, the example of FIG. 5 shows “L” I / O cells 51.
1 to 513 and 521 to 523 are shown. According to the above description, "L" new externally accessible control signal lines 531 to 533 are introduced. Each control signal line is connected to the DI input of exactly one I / O cell of all subgroups, thereby ensuring that no I / O cell is connected to exactly two or more control signals. ing. The first control signal line 531 is connected to the I
/ O cell 521 to I / O cell 5 of subgroup 501
Connect to up to 11 DI inputs. Second control signal line 532
Is connected to DI inputs from the I / O cell 522 of the subgroup 502 to the I / O cell 512 of the subgroup 501. Finally, the n-th control signal line 533 is connected to DI inputs from the I / O cell 523 of the subgroup 502 to the I / O cell 513 of the subgroup 501. clearly,
In this configuration, in each of the subgroups 501 to 502, one I / O cell can be simultaneously and accurately controlled by each of the “L” control signals 531 to 533. In each subgroup, the activation / deactivation pattern of all possible I / O cells can be adjusted. Acronym BIDI Bidirectional Driver / Receiver I / O Cell BS Boundary Scan DI Driver Prohibited HZ High Impedance IC Integrated Circuit I / O I / O MCM Multi-Chip Module SCM Single-Chip Module SR Scan Register SRL Shift Register Latch

In summary, the following is disclosed regarding the configuration of the present invention. (1) A test method for testing at least one integrated circuit having N I / O signal lines embedded in a chip module supporting M signal lines to be tested, wherein the integrated circuit includes a test circuit. A latch and N I / O cells connected to the internal structure of the integrated circuit via the test latch, wherein the test method includes the M I / O signal lines; Grouping each of the subgroups with one of the M I / O signal lines of the chip module, and analyzing the integrated circuit. The analyzing step includes storing a test pattern in the test latch or supplying a test signal to one or more I / O signal lines; Activation-deactivation sub-step of deactivating one subset of I / O cells and deactivating the remaining I / O cells in each of the Comparing the signal received on the I / O signal line of the chip module with the expected signal after transmitting the pattern, or a result test pattern expecting the resulting test pattern in the test latch And a comparing sub-step of comparing with: (2) The test method according to (1), wherein the analyzing step is repeated with a test pattern that can be changed to cover all of the I / O cells. (3) The activation-deactivation sub-step involves activating only one I / O cell and deactivating the remaining I / O cells in each of the subgroups whose output behavior is to be analyzed. The test method according to the above (1) or (2), which is characterized by: (4) The activation-deactivation sub-step activates an arbitrary subset of the I / O cells in each of the subgroups whose input behavior is to be analyzed, and deactivates the remaining I / O cells. The test method according to the above (1), (2) or (3), wherein (5) The test method according to any one of (1) to (4), wherein energization and deactivation of the I / O cell are controlled by the test latch. (6) At least one of the I / O cells is a bidirectional I / O cell whose energization / deactivation can be controlled by a high impedance signal.
The test method according to any one of (1) to (5). (7) At least one of the I / O cells is a bidirectional I / O cell whose energization / deactivation can be controlled by a driver inhibition signal, and is controlled by the driver inhibition signal in each of the subgroups. The test method according to any one of (1) to (5), wherein the number of possible I / O cells is one at most. (8) A chip module (604) holding at least one integrated circuit (607) having N integrated circuit I / O signal lines, which is used to connect the integrated circuit to the chip module. And P (P is N or more) chip module internal I / O signal lines, which are used to connect the internal chip module surface (605) and the chip module and the integrated circuit to an external environment. M
An external chip module surface (606) having one chip module external I / O signal line;
A connection provided between the module surface and the internal chip module surface, wherein each of the M chip module external I / O signal lines is connected to the P chip module internal I / O signal lines. , One or more of them, the N I / O signal lines and the P chips
A connection between a subset of module internal I / O signal lines, wherein said N I / O signal lines are grouped into subgroups, each of said subgroups being the same chip module external I / O signal line Circuit I / O connected to
A connection part constituted by a signal line; and a chip module (604). (9) Arranging the P chip module internal I / O signal lines on the internal chip module surface (605) to support connection to many different types of integrated circuits. (8) The chip module according to the above (8).

[Brief description of the drawings]

FIG. 1 illustrates an I / O with a boundary scan architecture.
FIG. 2 is a diagram showing a schematic organization of an O cell, a test cell, and internal system logic.

FIG. 2 is a diagram showing an entire structure of an I / O cell (BIDI) of a bidirectional driver / receiver on an IC.

FIG. 3 shows more details of a sub-circuit coupling the BIDI with a corresponding test latch of the BIDI.

FIG. 4 schematically illustrates the process of building a BIDI subgroup, where these subgroups are dotted and their energized / deactivated states are controlled by HC control signals.

FIG. 5 schematically illustrates the process of building a BIDI subgroup, where these subgroups are dotted and their energized / deactivated states are separate drive inhibit (DI). Controlled by a signal.

FIG. 6 schematically illustrates an IC embedded in a chip module according to a preferred embodiment.

[Explanation of symbols]

 REFERENCE SIGNS LIST 100 IC 101 Internal system logic 102-107 Boundary scan register (BS cell) 112 System output cell 113 3-state system output cell 114 Bidirectional control I / O cell 200 BIDI 201 Common I / O line 204 High impedance (HZ) control 301 Driver 302 Receiver 303-305 Test latch 401-403 BIDI 410, 420, 430 Data-in line 411, 421, 431 Receive data line 412, 422, 432 HZ control line

──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Bernd Galben, Germany Day-71101 Sheenaich Donauschwabenstraße 13 (72) Inventor Doctor Hubert Harler Germany, Day-71101 Sheenaich Rilkeweg 18 (72) Inventor Erich Krink, Federal Republic of Germany, D-71101 Schenaich Lessingstrasse 16 (72) Inventor Dieter Wendel Der-71101, Deutsche Federal Republic of Germany D-71101 Scheinich Frau Herderlingweg 21 (58) Field of study (Int .Cl. ⁷ , DB name) G01R 31/28-31/3193

Claims (9)

(57) [Claims] 1. A test method for testing at least one integrated circuit having N I / O signal lines embedded in a chip module supporting M signal lines to be tested, said integrated circuit comprising: A test latch, and N I / O cells connected to the internal structure of the integrated circuit via the test latch. The test method includes: Grouping up to M subgroups; connecting each of the subgroups to one of the M I / O signal lines of the chip module; and analyzing the integrated circuit. Analyzing, storing the test pattern in the test latch or
Or a storage sub-step of providing a test signal to one or more I / O signal lines; and energizing one subset of I / O cells and erasing the remaining I / O cells in each of the subgroups. Energizing energizing-deactivating substep; transmitting the test pattern via the energized I / O cell, and then recognizing a signal received on the I / O signal line of the chip module as an expected signal. Comparing or comparing the resulting test pattern in the test latch with the expected result test pattern. 2. The method of claim 1, wherein the step of analyzing is repeated with a test pattern that can be changed to cover all of the I / O cells. 3. The activation-deactivation sub-step activates only one I / O cell in each of the subgroups whose output behavior is to be analyzed and deactivates the remaining I / O cells. 3. The test method according to claim 1, wherein: 4. The activation-deactivation sub-step activates any subset of the I / O cells in each of the subgroups whose input behavior is to be analyzed and deactivates the remaining I / O cells. 4. The test method according to claim 1, wherein the test is performed. 5. The test method according to claim 1, wherein the activation and deactivation of said I / O cell is controlled by said test latch. 6. The I / O cell according to claim 1, wherein at least one of said I / O cells is a bidirectional I / O cell whose energization / deactivation can be controlled by a high impedance signal. Test method described in any of them. 7. At least one of said I / O cells is a bidirectional I / O cell whose activation / deactivation can be controlled by a driver inhibit signal, and said driver inhibit signal in each of said subgroups. 6. The test method according to claim 1, wherein the number of I / O cells that can be controlled by the control is at most one. 8. A chip module (604) holding at least one integrated circuit (607) having N integrated circuit I / O signal lines, said chip module connecting said integrated circuit to said chip module. (P is N or more) chip module internal I / O signal lines used for
5) and M chip module external I used to connect the chip module and the integrated circuit to an external environment.
External chip module surface having the / O signal line (60
6) and the external chip / module surface and the internal chip /
A connection provided between module surfaces, wherein each of the M chip module external I / O signal lines is connected to one or more of the P chip module internal I / O signal lines. A wiring to be connected, and a connection between a subset of the N I / O signal lines and the P chip module internal I / O signal lines,
The N I / O signal lines are grouped into subgroups, each of the subgroups including a connection unit formed by an integrated circuit I / O signal line connected to the same chip module external I / O signal line; A chip module (604), comprising: 9. The internal chip / module surface (605)
9. The connection to a number of different types of integrated circuits by arranging said P chip module internal I / O signal lines thereon.
The described chip module.