JP3072718B2 - Method for testing an integrated circuit having multiple I/O signals - Patents.com - Google Patents

Description

Detailed Description of the Invention

[0001]

FIELD OF THEINVENTION This invention relates to the current state of the art test environment and method for testing integrated circuits (ICs) having a greater number of input/output (I/O) cells than the test head can support.

[0002]

2. Description of the Prior Art Numerous different test methodologies are known in the art for testing integrated circuits (ICs) at all integration levels such as LSI, VLSI and ULSI.
For a long list of references in this field, see VD
Agrawal, SCSeth, "Test Generation for VLSI
Only one must be mentioned: "Chips", IEEE Computer Society Press 1988, which contains references to many important publications.

A particular class of test methodologies, called design for testability, targets the controllability and observability of ICs already in the design stage. Available methods include: Testability analysis Partitioning Built-in self-test Scan design

For an overview of these methods, see, for example, T.
W. Williams, K. E. Parker, “Design for Testability
- A survey", Proc. of the IEEE, Vol. 71, No 1, 198
3, pp 98-112. Within the design-by-scan approach, a further distinction can be made between the following categories of approaches: Scan-path techniques and their extension to boundary-scan architectures. Boundary-scan methods are known as Joint Test Actio
IEEE Standard STD11 by the n Group (JTAG)
The boundary-scan approach has been standardized as IEEE 49.1 and is publicly available as a document from the IEEE. Additionally, a thorough and up-to-date review of the boundary-scan approach is available in CMMo
under, "The Test Access Port and
Boundar y-Scan Architecture", IEEE Computer
This is provided by the Logic Design Society Press 1992. Level-Sensitive Scan Design (LSSD) Level-Sensitive Scan Design (LSSD) is described, for example, in "A Logic Design Structure" by EB Eichelberger.
ure for LSI Testabilit y", Proceedings of
the Design Automation Conference No.14, 20-2
2, June 1977, New Orleans, Louisiana. Also see U.S. Pat. No. 4,590,078, U.S. Pat. No. 4,428,060, and "A Survey of Design Factors" by E. J. McCluskey for a comprehensive listing of patents and publications relating to the testing of electronic structures based on this technique.
or Testability ScanTe chniques", VLSI Desig
n, December 1984, pp 38/61. Scan/set technique Random access approach

All of these approaches can be used alone or in combination with other techniques. The common thread in all of these scan design approaches is:
The use of multiple controllable/observable points inside an IC. Controllability is achieved by using shift register latches (SR
L) to the point that is constructed by serially shifting the data. Then, perform the test.
The data stored in the RL is then shifted back in for observation. Thus, control and observation of the IC is independent of the number of pins in the package. Furthermore, because the latches themselves are part of the internal circuitry, they can be used to break feedback paths in sequential circuits, thereby allowing automated testing of combinational circuits between the SRLs.

In a typical scan design, shift registers are located at specific points required for the functionality of the design, but for testing purposes they are linked in a scan chain. This scan chain allows any test state to be realized within the registers when used for testing purposes. A test pattern is then generated by the computer. The generated test pattern is then fed into the S
The test involves shifting test vectors (selected words or groups of digital data) into the SRL, applying test vectors (selected words or groups of digital data) to the primary inputs or pins of the chip, applying the system clock to perform the test, comparing the primary output pins to the expected vector outputs, and scanning data out of the SRL and comparing it to the known good test vectors. To perform this test, many test vectors are typically required to shift into the SRL, apply the test vectors, and shift the results back out.

[0007]

[0005] Current testing approaches suffer from several difficulties. The architectural testing approaches described above are unable to test for all possible types of defects. ICs have a very large number of input/output (I/O) cells,
They may also be bidirectional with driver and receiver logic. The above test procedure provides a complete AC/DC test to detect a complete list of possible defects in an IC such as stuck-on defects, delay defects, floating line defects, bridging defects, short circuits, open leakage current, impedance, etc.
Does not support DC and parametric test spectrum testing.

Another problem with current testing approaches arises from the increasing number of I/O signals on an IC and the corresponding number of I/O cells that must be analyzed for all types of defects. One of the reasons for the increase in the number of I/O cells is the increasing density of integration. For example, as integration levels move from LSI, VLSI to U-level integration, the number of I/O cells increases.
With the move to LSI, the number of I/O cells will easily exceed 1200. Furthermore, technology is moving to a multi-chip module (MCM) approach where MCMs with perhaps a moderate number of I/O cells are assembled from individual chips. Because these chips are designed for use within MCMs, they utilize a large I/O signal count, which requires wide data buses within the MCM. Thus, future ULSI chips designed to utilize MCMs will have a much larger number of I/O signals than chips designed for single chip module (SCM) use.

Before these ULSI chips can be assembled in an MCM environment or any other environment, they must be tested for all kinds of defects. The most current test environments available today are designed to test standard SCMs.
The current standard is limited to testing chips embedded in SCMs and having I/O signal counts in the range of 400 I/O cells. To enable testing of these ULSI chips, it is necessary to design a special purpose SCM that supports a large number of I/O signals and to integrate this new SCM for testing purposes.
A ULSI chip must be embedded in M.
Many difficulties and obstacles are expected due to the mechanical and electronic hurdles associated with the large number of I/O signals. Also, these new SCMs are expected to support testing only for specific chip families, and do not provide a solution to the general problem. To make matters worse, during the course of technology development due to increased integration density, the rate of increase in the number of I/O cells on a chip is faster than the progress of SCM-based test technology, which is limited by macroscopic and mechanical constraints.

As a result, testing ULSI chips and test environments based on current approaches is becoming increasingly expensive due to the increasing number of I/O signals.

The objectives of the present invention relating to IC testing are:
The present invention provides a new kind of testing approach for ICs that have I/O signal counts that far exceed those supported by current SCM test environments, and helps to eliminate the need to build special purpose SCMs to test such ICs.

[0012]

The test method of the present invention comprises the steps of:
A large number (N) of inputs/outputs (I/Os) embedded in a chip module (e.g., SCM) supporting M signal lines.
In particular, the number M of signal lines in a chip module is determined by the number of I/O lines to be tested together with the IC.
This test method can be applied when the number of cells is smaller than N. For test purposes, the IC is
Assume that the IC has a test latch that is controllable and observable. N I/O cells are connected to the internal structure of the IC through the test latch. The test method includes a test latch and N I/O cells that are connected to the internal structure of the integrated circuit through the test latch.
and the N I/O cells, and the test method
The method includes the steps of grouping the I/O signal lines into up to M subgroups, connecting each of said subgroups to one of said M I/O signal lines of said chip module, and analyzing said integrated circuit, said analyzing step including a storing substep of storing a test pattern in said test latches or providing test signals to one or more I/O signal lines, an enable-disable substep of activating a subset of I/O cells and deactivating the remaining I/O cells in each of said subgroups, and disabling said I/O cells of said chip module after transmitting said test pattern through the activated I/O cells.
/O signal line with an expected signal or a comparing substep of comparing a resulting test pattern in said test latch with an expected resulting test pattern.

All I/O cells in one subgroup are dotted and therefore require one I/O signal line to transfer the test signals in the test environment. It is this concept that greatly reduces the number of I/O signal lines required. Separate signal lines are only required for the subgroups, and the test requirement of using one signal line per I/O cell is now obsolete.
Thus, the larger the subgroup (the more I/O cells), the fewer the number of signal lines required to exchange I/O signals in the test environment. Another advantage of the present invention is due to the teaching of the enable/disable substep, which allows the I/O cells participating in the current test activity at each time to be
O cells can be selectively controlled. This extensive control capability therefore allows all subgroups to be tested and analyzed in parallel, or they can be tested in series. As yet another advantageous feature, the present invention allows testing of the complete IC, and not just the circuitry between the pins and the test latches.

Test all possible test patterns
By applying sequentially to the latches and I/O signal lines, another advantage of the present invention is achieved in that the test methodology allows the complete IC with its I/O cells to be tested while it is in full functional behavior. Also, within each subgroup, any subset of the I/O cells can be selectively enabled or disabled for testing purposes, thus allowing a complete test of all the I/O cells and the entire IC.

The use of test patterns stored in test latches not only for providing test inputs to the I/O cells, but also for enabling/disabling the I/O cells, greatly simplifies the test procedure. First,
Available means can be used without the need to introduce new physical features. Secondly, the test method can be simplified since the storage and energizing/deenergizing sub-steps can be combined.

Existing techniques such as scan design architectures can be used for the new purpose of enabling/disabling I/O cells. Either approach provides a very broad level of control, allowing selective enabling/disabling of each I/O cell within each subgroup.

[0017]

[0023]

1. Introduction The following description is generally presented in a multi-chip module (MCM) environment, but as stated above, this is not intended to limit the invention in any way.
The MCM environment is only one environment in which the present invention may improve testability. Also, as the present invention is described, this is accomplished in a boundary scan (BS) test environment. The present invention is completely neutral with respect to a particular "design for testability" technique, and may be applied to any test technique that allows control and observation of a given IC. Thus, where the present invention is described in terms of scan registers, any other type of test latch or test cell may be used instead to implement the present invention. Similarly, while the following description focuses on a particular type of I/O cell having a bidirectional driver/receiver (BIDI) nature, the present invention may be used to test any other type of I/O cell. BIDI is taken as only one possible example of an I/O cell. In the following, BIDI is described as a test cell having a bidirectional driver/receiver (BIDI) nature.
The terms and I/O cell are used interchangeably.

The present invention, which is going to be described below, is a method for testing chips having a large number of input/output (I/O) signals. Such kind of chips are, for example, ULSI chips, which are very important for use in multi-chip modules (MCMs). Before assembling the MCM, each chip must undergo a complete test regarding its digital and parametric (analog) behavior. Furthermore, each chip must undergo various stress tests, such as thermal cycle (burn-in) tests, to ensure high quality of the chips.
Only after going through all the stress cycles and testing procedures is the high quality of these chips guaranteed and they are ready for assembly into MCMs.

Due to advances in integration technology, future chips, particularly chips designed for use in MCMs, will exhibit many more I/O signals than conventional chips designed for use in Single Chip Modules (SCMs).
The advantages of the large I/O signal count are used to achieve wider data buses for communication within the MCM or with external chips. Another important advantage of these MCM designs is shorter wiring lengths. These approaches result in a huge performance improvement compared to SCM designs with modest I/O signal counts.

Before being assembled into an MCM, all chips must exhibit the same high quality level. Since the number of times chips can be replaced in an MCM is severely limited, each chip cannot be tested within the MCM assembly. Furthermore, the complete set of tests described above cannot be performed within the MCM environment, since, for example, it is not possible to access all I/O signal lines within the MCM, and since, for example, AC tests cannot be performed on a wafer due to the high I/O count. Therefore, one is forced to test each chip within the SCM environment. Due to the high number of I/O signals in ULSI chips, inexpensive standard SCM technology cannot be used to apply complete tests. Without the present invention, the need to test SCMs with a large number of I/O signals would require the technology of SCMs to be upgraded to large, expensive and highly specialized SCMs.

2. New Test Method In the following description, we focus only on the test procedure of the I/O cells, since complete I/O cell testing is not supported by other test methods. Of course, the method of the present invention can also be used to test the internal system logic of the chip.

As an example of a testable design approach,
1 shows the schematic state on an IC 100. All ICs conforming to IEEE Standard 1149.1 include a Boundary Scan Register (BS Cell) 102 as a test latch for testing all interconnects and internal system logic 101.
The on-chip system logic 101 must include test latches 102-107. For controllability and observability purposes, test patterns can be written into or read from the test latches 102-107 by serially clocking data along a scan path 110. These test latches must be located between the various types of I/O cells and the internal system logic. That is, test latches must be located between: each system input cell (clock or data) 111 and a corresponding input to the on-chip system logic 101; each output from the on-chip system logic 101 and a corresponding system output cell 112;
It must be located between each output from the on-chip system logic 101 and a corresponding tri-state system output cell 113 or bidirectional control I/O cell 114 .

As mentioned above, the present invention can be used to test internal system
Logic 101 and a number of I/O cells 111 to 114
This paper deals with a method for testing internal system logic 101 with test latches. Since testing of internal system logic 101 with test latches is well known in the art, we will focus here on testing I/O cells. Of course, the test method proposed here can also test internal system logic. Furthermore, to handle the most complex case, the following discussion focuses on three cases:
It handles bi-directional I/O cells. The ability to test such I/O cells implies the ability to test all other types of I/O cells as well.

The bidirectional driver/
The overall receiver I/O cell (BIDI) is modeled in Figure 2, which shows the BIDI 200 and its various signal lines. On the right side of block 200, common input/output lines 201 are shown, which connect the IC to external circuitry. On the left side, wiring between the internal system logic 101 is shown, including a path 202 for receive data from outside the IC, a path 203 for data in from inside the IC, and an I/O line 204 for controlling the mode of operation of the BIDI.
A path 204 for high impedance (HZ) control from inside C is included.

As mentioned above, each BIDI, including its drivers and receivers, must be subjected to a complete stress test (burn-in, etc.) followed by testing of its AC, DC and parametric characteristics and for the various defects mentioned above. For this purpose, FIG. 3 shows in more detail the constituent circuitry of a BIDI together with its corresponding test latches. FIG. 3 shows the same signal lines according to FIG. 2. On the left side, the already mentioned lines 202 to 204 are shown. On the right side, the common input/output line 201 is shown. For the purpose of testing the BIDI, line 201 is connected to the test environment.
The actual BIDI cell is represented by block 300, which includes an I/O cell driver 301 and receiver 302.
3 further includes a test latch 30 for testing purposes regarding the observability and controllability of this BIDI.
These test latches support testing of the BIDI using signals on lines 202-204 that are connected to the internal system logic. Test latches 303-305, preferably implemented as boundary scan registers (BS cells), support the BIDI testing.
The BIDI 300 functions to test the driver 301 and receiver 302 of the DI. Any test pattern can be externally fed to the test latches, and conversely, any test pattern stored in the test latches can be externally fed as a result of testing the IC or its components. For example, test latch 303 can be used to feed signals from the internal system logic of an IC to the BIDI 300. Test latch 305 allows the BIDI 300 to receive the results of signals collected from the outside. Finally, test latch 304 can store a test pattern that will cause the BIDI 300 to operate as a receiver cell by setting driver 301 in HZ mode.

A practical method for testing an IC containing I/O cells can handle situations where the number of I/O cells and their corresponding I/O connections exceeds the number of connections supported by a standard chip module (e.g., SCM) and test environment. From an overview of the test method of the present invention, it can be summarized into the following major steps, each of which is detailed in the following sections: (1) Grouping the signal lines of the IC into subgroups, each subgroup consisting of one, two or more I/O signal lines of the IC; (2) Connecting each I/O cell in each subgroup to one I/O signal line of the chip module (e.g., SCM) by dotting; (3) Testing the IC by performing the following substeps:
(3-1) Store a test pattern in latches 303 to 305 of one, two or more I/O cells. (3-2) Store a test pattern in lines 2 of one, two or more I/O cells.
(3-3) activating driver/receiver components of one, two, or more I/O cells to enable for test purposes only a subset of I/O cells within each subgroup whose test results do not interfere, and deactivating the remaining I/O cells.
(3-4) Transfer the data received in the test latches 303-305 after the test cycle of the I/O cells to the outside for analysis. (3-5) Receive the signals generated on the output lines 201 by the I/O cells after the test cycle for analysis in the test environment. (4) Transfer all test patterns of interest and all subgroups of interest and their constituent I/O patterns to the outside for analysis.
Repeat analysis step (3) for the /O cell.

2.1 Grouping I/O Signal Lines into Subgroups If an IC chip with a large number (N) of I/O signal lines to be tested is embedded in a standard chip module (e.g., a standard SCM) and the module is divided into M (<
Suppose that a chip module only supports testing of M (N) I/O lines, the present invention proposes dividing the N I/O lines of the chip into subgroups, each of which is connected to a separate connection of the M I/O lines of the chip module. Thus, for the chip module, each subgroup is connected to one I/O line.
Since all I/O cells are treated as 10 signal lines, this approach allows the IC to be considered as having a significantly smaller number of I/O cells than it actually has. Of course, the number of subgroups set cannot exceed the number of signal lines M supported by the chip module. In the present invention, there is no limit to the number of I/O cells that can be combined into a subgroup. However, depending on the test, it may be possible to use a subgroup with only one or two I/O cells.
or some other integer number of I/O cells. As a result of the electromechanical behavior of the subgroups, certain practical limitations are imposed on the number of I/O cells per subgroup.
In some cases, the number of components in a subgroup may be in addition to the number of I/O cells. For example, as the number of components in a subgroup increases, the total capacity of the subgroup increases until it reaches a limit that cannot be tolerated any more for testing reasons. As will become apparent from the following discussion, there is an interest in reducing the number of components in a subgroup, since this number reduces test time. According to this teaching, each subgroup represents one I/O cell of the chip, and is therefore exercised against the chip module and the test head of the test environment. Thus, the I/O cells in each subgroup are
It is necessary to provide mechanisms to prevent uncontrolled interference on the /O signal lines. These mechanisms are described in "An IC and its I/O Signal Lines" below.
This is the assignment for the step "Analysis of /O cells."

2.2 I/O within each subgroup
According to the above description, one chip to be tested is integrated into a chip module (e.g., a single chip module (SCM)) for testing purposes. During this procedure, the signal lines of those I/O cells that are combined to form individual subgroups are connected together, and finally each subgroup is integrated into its chip module (i.e., SCM).
A chip module can be controlled and observed through a single pin of a single I/O cell. Realistic I/O dots range from 2 to 4 I/O cells. As a result, a special customized chip module according to the invention using standard technology with a standard size containing a standard number of I/O pins will require less space than a state-of-the-art chip module would allow.
More than two to four I/O signals can be supported for testing purposes.

This dotting process can be seen in the example of Figure 4. "L" BIDIs 401-403 are combined to form one of the subgroups mentioned above. This grouping is achieved by dotting common I/O lines 405-407 (shown by dashed line 409) to form one common I/O line 408 for the subgroup.

Thus, for this description, the numbers N, M and L
has the following meaning: NIC the total number of I/O signal lines of the IC M the total number of I/O signal lines of the chip module (M
L = number of distinct DI signal lines (see chapter "Other Approaches for Enabling/De-Enabling I/O Cells"). A more detailed feature of a preferred implementation of this dotting process is shown in FIG. 6, which illustrates how the signal lines of the above-mentioned subgroups of IC 607 are connected to module 60.
4 shows how it is connected to each of the I/O pins.

6 shows a module 604 which can be used as a test device to implement the novel test method disclosed in this application. On the top side 605, or inner chip module side of the module 604, signal lines 601, 602, 603, 604 are connected to each other.
An integrated circuit 607 having a 14 is attached to module 604. Signal lines 601, 602, 603, 614 are connected to lines 611, 612, 614 which are electrical I/O lines on module 604.
In case a) of FIG. 6, the lines 611, 612, 613 are dotted in a "fork-like" structure, and the I/O signal lines 601, 602,
Each of the groups 603 forms a subgroup.
In the dotting structure of case b), the I/O of IC607
An I/O signal line 614 of the O cell is connected to one signal line 610 of the module 604, but a "fork region" 620 may make separate contact with the IC.

Of course, many variations in the layout of the fork regions are possible. For electromechanical reasons, it is advantageous to have the fork regions close to surface 605, for example to reduce the amount of signal reflection. Furthermore, any number of lines of IC 607 may be dotted to share a common external line on external chip module surface 606. For the purposes of the test method of the present invention, it is advantageous to dot all the lines of one fork region on module 604 with the IC
In the case of case a) of FIG. 6, the line 611,
Only two of 612 and 613 may be connected to the signal lines of the integrated circuit to be tested. In that case, the third line is not used. This fact does not have any negative impact on the test procedure. Which lines of the module are dotted with the corresponding lines of the IC is determined by the pin layout (footprint) of the integrated circuit. Based on this background, 611, 612, 613, 609,
It is now possible to provide modules with fork regions such as 610, 615 that provide an excessive number of possible connections, thereby allowing the integration of not just one type of IC, but multiple ICs.
C. Such a module 604 would be suitable for use as a generalized module with a flexible and universal footprint capable of holding many different ICs.

2.3 Analysis of an IC and its I/O cells According to the above description, each subgroup of I/O cells of an IC to be tested is modeled as one I/O connection with respect to the outside of the chip module (i.e. SCM) that holds the chip. Therefore, to obtain a clear test result, the test method of the invention requires a control step that activates the subset of I/O cells of each subgroup that is relevant for testing and deactivates the remaining I/O cells according to the respective test goal. We have emphasized before that this description (not the invention) is limited to tests related to the I/O cells of an IC. Reiterating our previous position, we point out that this test method itself can also be used for testing the internal system logic of an IC. With regard to the testing of I/O cells, two test modalities must be distinguished: ◆ Output test mode, which concerns the output behavior of the I/O cells ◆ Input test mode, which concerns the input behavior of the I/O cells Of course, an I/O cell must be tested in all the modes in which it operates in the chip.

The description of the test method will be limited to one subgroup only. All other subgroups of the IC's I/O cells must be tested in a similar manner. Two alternative approaches are possible in this regard.
That is, either test and analyze all the subgroups in parallel, or test them in series, which requires longer test time. This test method also allows some I/O cells to be tested in an input test mode while others are tested in an output test mode.

2.3.1 Output Test Starting with the description of the output test mode for a subgroup of I/O cells, the first test step requires that a particular test pattern be stored in the test latches. The purpose of that step is manifold. One reason is to generate a constant, controlled signal pattern to input to the BIDI. Another reason is to reset the test latches to a controlled, known state and later to read the data 411 received by the I/O cells and stored in the test latches.
4, this allows the user to accurately determine the signal test patterns 421, 431. If the test latches are implemented according to a scan design architecture based on the BS architecture, as is the case in the preferred embodiment of the present invention, then test patterns can be easily stored in the shift test latches by serially shifting the test patterns along scan paths such as 110 into the test latches. With reference to FIG. 4, this allows the user to shift a particular signal test pattern onto the "Data In" lines 410, 420, 430, the "Receive Data" lines 411, 421, 431 and the "HZ Control" lines 421, 431.
This means that it is available at 12, 422, and 432.

In this output test mode, one can check the responses 405-406 of the various I/O cells of the same subgroup.
07, because these signals are treated as a single common signal 40 at the level of the test environment.
8. Thus, for controllability and observability reasons, the test methodology must ensure that only a precisely defined subset of the I/O cells of a subgroup is energized, and that the remaining I/O cells of that particular subgroup are not energized.
In order to achieve this, it is necessary to ensure that all I/O cells are deactivated. Only in this situation can it be deduced which I/O cell is responsible for the signal 408 detected in the test environment. In a typical situation, this means that only one I/O cell is activated, and therefore the output signal 408 resulting from the test can be identified as coming from this particular I/O cell. However, test situations are also possible where a subset of I/O cells, not just one, can be activated.

In output test mode, activation is BIDI
302的马达，而不能够是否应用于该试方法的一种进行。 English: Enable means to enable the driver 301 of the receiver 302, while disabling means to disable the driver 301 and therefore operate at the level of the receiver 302. The next step in the test method, enabling/disabling a subgroup of I/O cells, can be easily achieved by using the "HZ control" signal of the individual I/O cells.
By simply enabling or disabling the "HZ control" signals 412, 422, 432, the BID
I/O cells 401, 402, and 403 can be enabled (operating in drive mode) or disabled (operating in receiver mode).
An interesting effect is achieved by using the "Z control" input signal. This approach allows the enable/disable state to be controlled by the test pattern already stored in the test latches. It is noteworthy that this approach allows enable/disable control at the coarsest level (on an individual I/O cell basis).
A further extension of the test method in the output test mode is to use the fact that the disabled I/O cell acts as a receiver so that the output signal 408 generated by the enabled I/O cell can be used as the input to the disabled I/O cell, and thus the receiver 302 of the disabled I/O cell can be used as the input to the disabled I/O cell.
The test can be performed with the driver 301 of the I/O cell activated.

After the necessary processing operations of the I/O cells, the results of the operations are analyzed in the next step of the test method. During the output test mode of the test method, the output signals 40 generated by the subgroups and received by the test head of the test environment are
8 must be compared with the expected results of a good I/O cell. After the test cycle of the subgroup, the result test pattern stored in the test latches must optionally be transferred outside the IC. This result test pattern analysis is important in situations where, for example, the deactivated I/O cells are tested for their receivers 302 as outlined above. As mentioned above, if the test latches are implemented according to a scan design architecture as in the preferred embodiment of the present invention based on the BS architecture, the result test pattern can be easily transferred outside the chip and the SCM by serially shifting them out of the test latches along the scan paths such as 110. In the next step of the test method, the same activated I/O cells can be tested with other possible test patterns. Similarly, in the next step of the test method, all the previous test steps can be repeated for all other I/O cells requiring testing by changing the activation/deactivation pattern in the subgroup.

2.3.2 Input Test Proceeding to the description of the input test mode for a subgroup of I/O cells, the first test step requires storing a specific test pattern into the test latches.
The purpose of this step is manifold. One reason is to generate a constant, controlled signal pattern, which is input to the BIDI. Another reason is to provide a test
The purpose of this is to reset the test latches to a controlled, known state so that the data 411, 421, 431 received by the I/O cells and stored in the test latches can be accurately determined at a later time.
If implemented according to a scan design architecture, as in the preferred embodiment of the present invention based on this architecture,
Test patterns can be easily stored in the shifted test latches by serially shifting them along a scan path such as 110 into the test latches.
With reference to FIG. 4, this involves applying a particular signal test pattern to the "Data In" lines 410, 420, 430, the "Receive Data" lines 411, 421, 431 and the "HZ Control" lines 440, 442, 444.
This means that the test steps are available at 12, 422, and 432. This test step corresponds to the similar step in the output test mode.

Since an external input signal must be processed by the I/O cells of the subgroup, such signal must be provided from the test environment via the test head along signal line 408 in the next step of the test method. In this input test mode, all I/O cells receive the same external input signal 408, so there is no danger that the responses of the various I/O cells may interfere. Therefore, for reasons of controllability and observability of the test method, it is sufficient, at least in the typical case, to activate all the I/O cells in a subgroup. In the input test mode, the activation is performed by the BI
This means disabling the driver 301 of the BIDI and therefore operating at the receiver 302 level. On the other hand, test situations are possible where only a subset of the I/O cells are enabled and the rest are disabled. The next step in the test method, enabling/disabling a subgroup of I/O cells, can be easily achieved by using the "HZ control" signals of the individual I/O cells. Simply by using the "HZ control" signals 412, 422, 432, the BIDIs 401, 402, 403 can be enabled (operating in receiver mode).
An interesting effect is achieved by using a "HZ control" input signal for cell activation/deactivation. This approach allows the activation/deactivation state to be controlled by the test patterns already stored in the test latches. This approach allows the coarsest level (individual I
It is noteworthy that the I/O cells are enabled for activation/deactivation control (based on the I/O cells). After the necessary processing operations of the I/O cells, the operation results are analyzed in the next step of the test method. The result test pattern stored in the test latches after the test cycle of the subgroup must be transferred outside the IC and compared with the expected result pattern. As mentioned above, if the test latches are implemented according to a scan design architecture as in the preferred embodiment of the present invention based on the BS architecture, the result test pattern can be easily transferred outside the chip and the SCM by serially shifting them out of the test latches along the scan paths such as 110. In the next step of the test method, the same activated I/O cells can be tested with other possible external signal patterns 408. Similarly, in the next step of the test method, all the previous test steps can be repeated for all other I/O cells requiring testing by changing the activation/deactivation patterns in the subgroup.

2.4 Other Approaches to I/O Cell Enablement/Disablement Normally, BIDI provides another input signal, the so-called "Driver Inhibit (DI)" signal line. The DI signal allows:
The DI signal can block or disable the driver 301 of the BIDI. Thus, by using this DI signal, the BIDI can be switched between a driver and a receiver operating mode. The present invention proposes to use the DI concept of the BIDI for the I/O cell enable/disable step in this test method.

The largest subgroup of I/O cells is "L
Assuming that each subgroup contains "L" components (in the standard case, all subgroups contain the same number of I/O cell components, but this is not required by the present invention), the BIDI enable/disable control can be achieved using the DI signals by: ■ adding n control signal lines carrying the necessary DI signals; ■ connecting these control signal lines such that each of these control signal lines is connected to the DI input of at most one I/O cell of each subgroup, and no I/O cell is connected to more than one of the "L" control signal lines.
This connection allows for controlling the enable/disable state of all I/O cells in all subgroups based on one control signal line.

"HZ control" of BIDI proposed in the previous chapter
Compared to the enable/disable control mechanism based on the use of input signals, further differences arise in this new approach: in this new DI approach, the enable/disable step of the I/O cells can be performed independently of the loading of the test pattern into the test latches and is not affected by the contents of the test latches. Furthermore, it requires that separate control signal lines are externally accessible from the test environment. Finally, this DI approach is not as coarse-grained as the HZ approach, since in general each control signal line is connected to several I/O cells (at most one I/O cell in each subgroup).
This is because the energized/deenergized states of the two are controlled simultaneously.

An example of the DI approach is shown in FIG. 5. M subgroups of I/O cells 501-502
Assume that the DI signal is set to control the I/O cells 51.
1 through 513 and 521 through 523. According to the above description, "L" new externally accessible control signal lines 531 through 533 are introduced. Each control signal line is connected to the DI input of exactly one I/O cell of every subgroup, thereby ensuring that no I/O cell is connected to exactly more than one control signal line. The first control signal line 531 is the I/O cell of subgroup 502.
/O cell 521 to I/O cell 5 of subgroup 501
Connects to DI inputs 11 and 2. Second control signal line 532
connects with the DI input of I/O cell 522 in subgroup 502 through I/O cell 512 in subgroup 501. Finally, nth control signal line 533 connects with the DI input of I/O cell 523 in subgroup 502 through I/O cell 513 in subgroup 501. Obviously,
In this configuration, exactly one I/O cell can be controlled simultaneously by each of the "L" control signals 531-533 in each subgroup 501-502. In each subgroup, the activation/deactivation pattern of all possible I/O cells can be coordinated. Acronyms BIDI Bidirectional Driver/Receiver I/O Cell BS Boundary Scan DI Driver Inhibit HZ High Impedance IC Integrated Circuit I/O Input/Output MCM Multi-Chip Module SCM Single Chip Module SR Scan Register SRL Shift Register Latch

In summary, the following items are disclosed regarding the configuration of the present invention: (1) A test method for testing at least one integrated circuit having N I/O signal lines embedded in a chip module supporting M signal lines to be tested, the integrated circuit having a test latch and N I/O cells connected to an internal structure of the integrated circuit via the test latch, the test method comprising the steps of grouping the N I/O signal lines into up to M subgroups, connecting each of the subgroups to one of the M I/O signal lines of the chip module, and analyzing the integrated circuit, the analyzing step a storing substep of storing a test pattern in said test latches or providing test signals to one or more I/O signal lines, an enabling-deactivating substep of activating a subset of I/O cells in each of said subgroups and deactivating the remaining I/O cells, and a comparing substep of comparing signals received on said I/O signal lines of said chip module with expected signals or comparing the resulting test pattern in said test latches with an expected resulting test pattern after transmitting said test pattern through the activated I/O cells. (2) A testing method as claimed in (1) above, characterized in that said analyzing step is repeated with a test pattern which can be modified to cover all of said I/O cells. (3) A testing method as claimed in (1) or (2) above, characterized in that said enabling-deactivating substep activates only one I/O cell in each of the subgroups whose output behaviour is to be analysed and deactivates the remaining I/O cells. (4) The test method according to (1), (2) or (3), characterized in that the enable-disable substep enables an arbitrary subset of the I/O cells in each of the subgroups for which input behavior is to be analyzed and disables the remaining I/O cells. (5) The test method according to any one of (1) to (4), characterized in that the enable and disable of the I/O cells is controlled by the test latch. (6) The test method according to (1), characterized in that at least one of the I/O cells is a bidirectional I/O cell whose enable-disable can be controlled by a high impedance signal.
(7) The test method according to any one of (1) to (5), characterized in that at least one of the I/O cells is a bidirectional I/O cell whose activation/deactivation can be controlled by a driver inhibit signal, and in each of the subgroups there is at most one I/O cell controllable by the driver inhibit signal. (8) A chip module (604) holding at least one integrated circuit (607) having N integrated circuit I/O signal lines, the chip module having an internal chip module surface (605) having P (P is N or more) chip module internal I/O signal lines used to connect the integrated circuit to the chip module, and an internal chip module surface (605) having P (P is N or more) chip module internal I/O signal lines used to connect the chip module and the integrated circuit to an external environment.
an external chip module surface (606) having 10 chip module external I/O signal lines;
a connection provided between the module surface and the internal chip-module surface, the connection comprising wiring for connecting each of the M chip-module external I/O signal lines to one or more of the P chip-module internal I/O signal lines;
a connection between a subset of the module internal I/O signal lines, said N I/O signal lines being grouped into subgroups, each of said subgroups being connected to the same chip module external I/O signal lines;
and a connection portion formed by a signal line. (9) The chip module according to (8) above, characterized in that the P chip module internal I/O signal lines are arranged on the internal chip module surface (605) to support connection to a large number of different types of integrated circuits.

[Brief description of the drawings]

FIG. 1 shows an I/O bus with boundary scan architecture.
FIG. 1 shows a schematic organization of O cells, test cells and internal system logic.

FIG. 2 shows the overall structure of a bidirectional driver/receiver I/O cell (BIDI) on an IC.

FIG. 3 shows in greater detail a subcircuit that combines a BIDI with its corresponding test latch.

FIG. 4 is a schematic diagram illustrating the process of constructing BIDI subgroups, where these subgroups are dotted and their activated/deactivated states are controlled by HC control signals.

FIG. 5 is a schematic diagram illustrating the process of constructing BIDI subgroups, where these subgroups are dotted and their activated/deactivated states are controlled by separate drive inhibit (DI) signals.

FIG. 6 illustrates a schematic of an IC embedded in a chip module according to a preferred embodiment.

[Explanation of symbols]

100 IC 101 Internal system logic 102-107 Boundary scan register (BS cell) 112 System output cell 113 3-state system output cell 114 Bidirectional control I/O cell 200 BIDI 201 Common I/O line 204 High impedance (HZ) control 301 Driver 302 Receiver 303-305 Test latch 401-403 BIDI 410, 420, 430 Data in line 411, 421, 431 Receive data line 412, 422, 432 HZ control line

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Claims (9)

(57) [Claims] [Claim 1] A method of testing at least one integrated circuit having N I/O signal lines embedded in a chip module supporting M signal lines to be tested, said integrated circuit having a test latch and N I/O cells communicating with an internal structure of said integrated circuit through said test latch, said method comprising the steps of: grouping said N I/O signal lines into up to M subgroups; connecting each of said subgroups to one of said M I/O signal lines of said chip module; and analyzing said integrated circuit, said analyzing step comprising: storing a test pattern in said test latch or
or a storing substep of supplying a test signal to one or more I/O signal lines; an enabling-disabling substep of activating a subset of I/O cells in each of said subgroups and disabling the remaining I/O cells; and a comparing substep of comparing the signal received on said I/O signal lines of said chip module with an expected signal after transmitting said test pattern through the activated I/O cells, or comparing the resulting test pattern in said test latch with an expected resulting test pattern. 2. The method of claim 1, further comprising repeating said analyzing step with a test pattern that is modifiable to cover all of said I/O cells. 3. The testing method according to claim 1, wherein the enable-disable substep enables only one I/O cell in each of the subgroups whose output behavior is to be analyzed and disables the remaining I/O cells. [Claim 4] A testing method as described in claim 1, 2 or 3, characterized in that the enable-disable substep enables an arbitrary subset of the I/O cells within each of the subgroups whose input behavior is to be analyzed and disables the remaining I/O cells. 5. The method according to claim 1, wherein the activation and deactivation of said I/O cells is controlled by said test latch. 6. The test method according to claim 1, wherein at least one of said I/O cells is a bidirectional I/O cell whose activation/deactivation can be controlled by a high impedance signal. [Claim 7] A test method as described in any one of claims 1 to 5, characterized in that at least one of the I/O cells is a bidirectional I/O cell whose activation/deactivation can be controlled by a driver inhibit signal, and in each of the subgroups, there is at most one I/O cell controllable by the driver inhibit signal. 8. A chip module (604) holding at least one integrated circuit (607) having N integrated circuit I/O signal lines, the chip module having an internal chip module surface (604) having P chip module internal I/O signal lines (P is equal to or greater than N) used to connect the integrated circuit to the chip module.
5) and M chip module external I/Fs used to connect the chip module and the integrated circuit to the external environment.
/O signal lines on the external chip module surface (60
6) and the external chip module surface and the internal chip
connections between the module faces, the wiring connecting each of the M chip-module external I/O signal lines to one or more of the P chip-module internal I/O signal lines; and connections between the N I/O signal lines and a subset of the P chip-module internal I/O signal lines,
grouping said N I/O signal lines into subgroups, each of said subgroups having a connection portion formed by an integrated circuit I/O signal line connected to the same chip module external I/O signal line (604). 9. The internal chip module surface (605).
9. The method of claim 8, further comprising: disposing said P chip module internal I/O signal lines on said chip module to support connection to a number of different types of integrated circuits.
The chip module described herein.