KR101226963B1 - RFID device, test system thereof, and test method thereof - Google Patents

Abstract

The present invention relates to an RFID device, a test system including the same, and a test method thereof, and discloses a technique for reducing test time and improving test speed by testing respective tag chips using a multi-tag chip test mode. do. The present invention is a tag chip array for simultaneously testing a plurality of tag chips according to the test mode signal, and outputs a test output signal corresponding to the test result to the outside, and the tag chip according to a test control signal applied from the outside in the test mode The test chip outputs a test mode signal for testing the array, and the tag chip array divides the plurality of tag chips into units of a predetermined subgroup according to the test mode signal to perform a test operation.

Description

RFID device, test system including same and test method thereof {RFID device, test system, and test method about}

The present invention relates to an RFID device, a test system including the same, and a test method thereof, wherein an RFID tag chip receives a test signal through a test pad without using a radio frequency signal applied from an antenna at a wafer level. It is a technology to test the performance of the chip.

RFID (Radio Frequency IDentification Tag Chip) is a contactless automatic identification method that communicates with an RFID reader by attaching an RFID tag to an object to be identified and automatically transmitting and receiving it by using a wireless signal. To provide technology. As RFID is used, it is possible to compensate for the disadvantages of the conventional automatic identification technology, barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

Meanwhile, a nonvolatile ferroelectric memory may be used as a memory used for an RFID tag.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is an overall configuration diagram of a general RFID device.

The RFID device according to the related art includes an antenna unit 1, an analog unit 10, a digital unit 20, and a memory unit 30.

Here, the antenna unit 1 serves to receive a radio signal transmitted from an external RFID reader. The wireless signal received through the antenna unit 1 is input to the analog unit 10 through the antenna pads 11 and 12.

The analog unit 10 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 20. In addition, the analog unit 10 senses the output voltage VDD and outputs a power-on reset signal POR and a clock CLK to the digital unit 20 for controlling the reset operation.

The digital unit 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 10, and outputs a response signal RP to the analog unit 10. The digital unit 20 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 30.

In addition, the memory unit 30 reads / writes data using a memory element and stores the data.

Here, the RFID device uses a frequency of several bands, the characteristics of which vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the RFID device operates in a short distance, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

The most preferable method for testing whether the RFID tag is operating normally is as follows. Applying a radio signal through the antenna pad (11, 12) of the individual RFID tag, modulates the response signal RP generated by processing the radio signal by the digital unit 20 inside the RFID tag and transmits to the RFID reader, RFID It is to check whether the signal received from the reader is the desired signal.

However, it is expensive, time-consuming, and inefficient to test by individually applying wireless signals to thousands or more RFID tags per wafer.

The present invention has been made to solve the above problems, and an object thereof is to reduce test time and improve test speed by testing a plurality of tag chips at the same time using a multi tag chip test mode.

In order to achieve the above object, the RFID device of the present invention simultaneously tests a plurality of tag chips according to a test mode signal, outputs a test output signal corresponding to a test result to the outside, and receives a wireless signal received from the outside. And a tag chip array configured to modulate a response signal generated by processing the radio signal and transmit the modulated response signal to the outside through an antenna; And a test chip outputting a test mode signal for testing the tag chip array according to a test control signal applied from the outside in the test mode, wherein the test chip includes a plurality of tag chips in units of a predetermined subgroup according to the test mode signal. The test operation is performed by dividing into, and the tag chip array is characterized in that the number of tag chips included in the subgroup is changed according to the test mode signal.

The test system including the RFID device of the present invention includes: external test equipment for outputting a test mode signal for controlling a test operation; And an RFID device for dividing the plurality of tag chips into units of a predetermined subgroup according to the test mode signal, simultaneously testing tag chips of each subgroup unit, and changing the number of tag chips included in the subgroup according to the test mode signal. Including, but each of the plurality of tag chips receives a wireless signal received from the outside, and modulates the response signal generated by processing the wireless signal, characterized in that for transmitting to the outside through the antenna.

In the test method of the RFID device of the present invention, a test chip formed on a wafer level and a test operation controlled by the test chip receive a radio signal received from the outside, and modulate a response signal generated by processing the radio signal. A test method of an RFID device including a plurality of tag chips transmitted to an outside through an antenna, the method comprising: setting a tag chip to be tested according to a test control signal applied from the outside and performing a test operation by dividing into sub group units ; Determining whether there is a failed tag chip as a result of the test operation; And performing a previous test operation when there is no failed tag chip, and changing the number of tag chips included in a subgroup by changing a test mode according to a test mode signal when there is a failed tag chip. It features.

As described above, the present invention provides an effect of reducing test time and improving test speed by testing several tag chips at the same time using the multi tag chip test mode.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such configuration changes, etc. It should be seen as belonging to a range.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an RFID tag chip 640 in the RFID device according to the present invention.

The present invention does not receive a radio signal applied from the antenna 1 like the above-described conventional RFID device, but directly receives a measurement signal through a common test pad at a wafer level, and generates an RFID tag chip. Test your performance.

The RFID tag chip 640 of the present invention largely includes an analog unit 100, a digital unit 200, a test interface unit 300, a memory unit 400, and a test control unit 500.

First, the analog unit 100 includes a voltage amplifier 110, a modulator 120, a demodulator 130, a power-on reset unit 140, a clock generator 150, and a test input buffer. 160 and a test output driver 170.

Here, the voltage amplifier 110 generates a driving voltage of the RFID according to the power supply voltage VDD applied from the power supply voltage application pad P2.

The modulator 120 modulates the response signal RP input from the digital unit 200. The demodulator 130 generates an operation command signal DEMOD according to the output voltage of the power supply voltage application pad P2, and outputs the generated operation command signal DEMOD to the test input buffer 160.

The power on reset unit 140 detects a voltage applied from the power supply voltage applying pad P2 and outputs a power on reset signal POR for controlling the reset operation to the digital unit 200. The clock generator 150 supplies the clock CLK for controlling the operation of the digital unit 200 according to the output voltage of the power supply voltage application pad P2 to the digital unit 200.

Here, the power-on reset signal POR rises together with the power supply voltage while the power supply voltage transitions from the low level to the high level, and then transitions from the high level to the low level at the moment the power supply is supplied to the power supply voltage level VDD, thereby causing a circuit inside the RFID tag. Means a signal to reset.

The test input buffer 160 commands a command according to a test input signal RXI input through the test signal input pad P4, an operation command signal DEMOD input from the demodulator 130, and a test activation signal TSTEN applied from the test control unit 500. The signal CMD is output to the digital unit 200.

That is, the test input buffer 160 supplies the command signal CMD to the digital unit 200 according to the operation command signal DEMOD applied from the demodulator 130 when the test activation signal TSTEN is deactivated in the normal operation mode.

On the other hand, when the test activation signal TSTEN is activated in the test operation mode, the test input buffer 160 transmits a command signal CMD for testing RFID according to the test input signal RXI applied from the test signal input pad P4 to the digital unit 200. Supply.

In addition, the test output driver 170 drives the test output signal TXO according to the response signal RP input from the digital unit 200, and outputs the command processing result of the RFID to the outside through the test signal output pad P1.

Here, the voltage amplifier 110, the modulator 120, the demodulator 130, the power-on reset unit 140, the clock generator 150, the test input buffer 160 and the test output driver 170 are In the test operation mode for testing the performance of the RFID, it is driven by the power supply voltage VDD applied from the external power supply voltage application pad P2 and the ground voltage GND applied from the external ground voltage application pad P3.

That is, the power supply voltage applying pad P2 indicates a pad to which the power supply voltage VDD is applied when the RFID tag is activated to test a plurality of RFID tags on the wafer. In addition, the ground voltage applying pad P3 represents a pad to which the ground voltage GND is applied when testing a plurality of RFID tags on the wafer.

When the RFID tag communicates with the RFID reader to receive a wireless signal, the voltage amplifier 110 supplies the power supply voltage VDD. However, in the present invention, since the test is performed on the wafer, a separate power supply voltage pad P2 and ground voltage are performed. The supply voltage VDD and the ground voltage GND are supplied through the application pad P3.

The digital unit 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 100 to interpret the command signal CMD and generate control signals and processing signals. The digital unit 200 outputs the response signal RP corresponding to the control signal and the processing signals to the analog unit 100.

In addition, the digital unit 200 outputs the address DADD, the input data DI, the chip enable signal DCE, the write enable signal DWE, and the output enable signal DOE to the test interface unit 300. The digital unit 200 receives the output data DO from the test interface unit 300.

In addition, the test interface unit 300 is activated according to the test activation signal TSTEN applied from the test control unit 500. When the test interface 300 is activated, the memory unit according to the tag selection addresses X0 to X7, the memory addresses XA0 to XA7, the input data XDI0 to XDI7, the control signals DIN_LATP, ADD_LATP, XCE, XWE, XOE, and TACT input from the outside. Test 400.

Among the control signals described above, DIN_LATP represents a data latch activation signal, ADD_LATP represents an address latch activation signal, and XCE represents a chip enable signal. Among the control signals, XWE represents a write enable signal, XOE represents an output enable signal, and TACT represents a test operation signal.

Here, the test interface unit 300 may include tag selection addresses X0 to X7, memory addresses XA0 to XA7, input data XDI0 to XDI7, and control signal input pads P6, P7, P9 to P11 that are input through the common test pad P5. The memory unit 400 is tested by generating the address ADD and the control signals I, CE, WE, and OE according to the control signals DIN_LATP, ADD_LATP, XCE, XWE, XOE, and TACT input through the test input pad P12.

The test interface unit 300 receives the control result signal O and outputs the output data XDO to the outside through the data output pad P8.

Meanwhile, when the test interface unit 300 is activated, the internal circuits included in the RFID tag, that is, the analog unit 100 and the digital unit according to the address DADD and the control signals DI, DCE, DWE, and DOE input from the digital unit 200. The unit 200 and the memory unit 400 are tested.

To test the entire operation of the RFID tag, the digital unit 200 generates the address DADD and the control signals DI, DCE, DWE, and DOE by the command signal CMD generated according to the test input signal RXI.

The test interface 300 generates the address ADD and the control signals I, CE, WE, and OE according to the address DADD and the control signals DI, DCE, DWE, and DOE to test the entire operation of the RFID tag. The test interface 300 receives a control result signal O, which is a test result, from the memory unit 400 and generates a control result signal DO.

The digital unit 200 generates a response signal RP according to the control result signal DO. In addition, the test output driver 170 drives the response signal RP and outputs it through the test signal output pad P1.

The memory unit 400 includes a plurality of memory cells, each memory cell writes data to a storage element, and serves to read data stored in the storage element.

Here, the memory unit 400 may be a nonvolatile ferroelectric memory (FeRAM). FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

The test control unit 500 serves to activate the RFID tag in the test mode. The test control unit 500 receives a test operation signal TACT from the test input pad P12 and a test clock TCLK from the test clock input pad P13. The test controller 500 outputs a test activation signal TSTEN for controlling whether the RFID tag is activated to the test input buffer 160 and the test interface unit 300.

In addition, the test controller 500 controls whether the test activation signal TSTEN is activated according to the test mode signals M1 and M0 applied from the test chip 630 to be described later.

As described above, when the test activation signal TSTEN is activated in the test mode, the present invention outputs a test result of the RFID device through the test signal output pad P1 or externally through the data output pad P8.

That is, when testing the entire operation of the RFID device, the test input signal RXI input through the test signal input pad P4 is transmitted to the digital unit 200, the test interface unit 300, and the memory unit 400, and the test is performed again. The interface unit 300 and the digital unit 200 are output through the test output pad P1 via the test output driver 170. Then, the external test equipment measures the output of the test signal output pad P1 to test the entire operation of the RFID device.

On the other hand, when only testing the memory unit 400 of the RFID device, the address and data input through the common test pad P5 is transferred to the memory unit 400 via the test interface unit 300, and again the test interface unit ( 300 is output via the data output pad P8. Then, the external test equipment measures the output of the data output pad P8 to test the operation of the memory unit 400.

As such, a method of testing the entire operation of the RFID device or testing the memory unit 400 through an external test pad at the wafer level is disclosed in the application number 10-2009-0056372 filed by the same inventor as the present case. Therefore, the detailed operation process will be omitted.

3 is a block diagram of an RFID test system according to the present invention.

The present invention includes an external test equipment 600, a probe card (610) and a wafer level RFID device (620).

In this case, the "RFID device 620" defined in the present invention is a concept including both the test chip 630 and the plurality of RFID tag chips 640 at the wafer level.

The external test equipment 600 transmits a test control signal TC for setting the test mode to the probe card 610. The probe card 610 is connected to each other through a wafer level RFID device 620 and a probe pin 611.

In addition, the test chip 630 and the plurality of RFID tag chips 640 transmit the test mode signals M1 and M0 through an internal test signal bus.

The present invention having such a configuration transmits the test control signal TC to the probe card 610 in the external test equipment 600. The probe card 610 outputs the test control signal TC applied from the external test equipment 600 to the RFID device 620 at the wafer level through the probe pin 611. In addition, the test chip 630 controls the test control signal TC applied through the probe card 610 to transmit the test mode signals M1 and M0 to each RFID tag chip 640.

FIG. 4 is a diagram illustrating an arrangement form of a test chip 630 and a tag chip 640 on a wafer of the RFID device 620 according to the present invention.

According to the present invention, a plurality of tag chips 640 are formed in a row and a column direction on one wafer to form a tag chip array. Each tag chip array includes a plurality of tag chips 640. That is, the tag chip array refers to a set of RFID tag chips in which a plurality of tag chips 640 are connected to each other using a scribe line.

One tag chip array includes one test chip 630 and a plurality of tag chips 640. Here, one test chip 630 is disposed at a center position on the tag chip array. One such test chip 630 will test all tag chips 640 placed on the tag chip array.

The tag chips 640 and the test chip 630 of the present invention exchange input / output signals representing test commands and test results through a scribe line region formed between the tag chips. That is, the test chip 630 and the plurality of tag chips 640 are connected to each other by a plurality of scribe lines arranged in the X and Y axis directions.

Accordingly, the power supply voltage VDD, the ground voltage GND, the control signal, the address, and the data supplied from the outside are tagged through the input / output pads of the tag chip 640 through a plurality of scribe lines arranged in the X and Y axis directions. It is supplied to the chip internal circuit.

The test output signal TXO and the control result signal generated by the tag chip 640 are output to the outside from the tag chip internal circuit through a plurality of scribe lines arranged in the X and Y axis directions through input / output pads.

Here, the test chip 630 is initialized to test the tag chip array. As a method of initializing the test chip 630, various methods may be used. For example, the test chip 630 may be set to be initialized when the power supply voltage VDD is supplied through the input / output pad.

5 is a flowchart illustrating an RFID test method according to the present invention.

First, in the multi-tag chip test mode, the tag chip to be tested next is set (step S1).

Then, the first test mode is set to a full test mode (step S2). Then, the corresponding plurality of tag chips are selected according to the same test signal to simultaneously perform parallel tests. S3)

Subsequently, as a result of parallel test of the tag chip in the full test mode, it is determined whether there is a failed tag chip (step S4).

If the tag chip is tested in parallel in the full test mode and there is no failed tag chip and all selected tag chips are passed, the tag chip to be tested next is set as in step S1.

On the other hand, when the tag chip is tested in parallel in the full test mode, when one or more failed tag chips are generated, the full test mode is terminated.

Then, the second test mode is set to the half test mode (step S5).

Then, the plurality of tag chips selected in the full test mode are divided into two sub groups so that the tag chips of each sub group are selected by the same test signal to perform parallel tests simultaneously (step S6).

After that, the tag chip to be tested next is set. (Step S7)

Then, the third test mode is set to the quarter test mode (step S8).

Then, the plurality of tag chips selected in the half test mode are divided into two subgroups, and the tag chips of each subgroup are selected by the same test signal to perform parallel tests simultaneously (step S9).

Subsequently, as a result of parallel test of the tag chip in the quarter test mode, the quarter test mode is terminated when one or more failed tag chips are generated.

After that, the tag chip to be tested next is set (step S10).

Then, the fourth test mode is set to the item test mode (step S11). Then, a separate test operation is performed on each of the corresponding tag chips (step S12).

Thereafter, the tag chip in which the fail has occurred is binned to distinguish the fail chip (step S13).

6 and 7 are views for explaining the RFID test method according to the present invention. Here, FIG. 6 is a diagram illustrating a test process method when all tag chips are passed, and FIG. 7 is a diagram illustrating a test process method when some tag chips among tag chips are failed.

In the RFID test method of the present invention, the test mode is divided by the bits of the test mode signals M1 and M0.

That is, one test mode among four test modes is set according to the bits of the test mode signals M1 and M0. The method for setting the test mode according to the bits of the test mode signals M1 and M0 is shown in Table 1 below.

Test mode select bit Test mode M1 M0 0 0 Full test mode 0 One Half test mode One 0 Quarter test mode One One Item test mode

First, when the test mode signals M1 and M0 are all '0' bits, the test mode is set to the 'full test mode'.

When the test mode signal M1 is the '0' bit and the test mode signal M0 is the '1' bit, the test mode is set to the 'half test mode'.

When the test mode signal M1 is the '1' bit and the test mode signal M0 is the '0' bit, the test mode is set to the 'quarter test mode'.

In addition, when the test mode signals M1 and M0 are both '1' bits, the test mode is set to the 'item test mode'.

It is preferable that the bit combination of the test mode signals M1 and M0 is changed according to the test control signal TC applied from the external test equipment 600.

For example, when the full test mode is set because the test mode signals M1 and M0 are all '0' bits, the plurality of tag chips receive the same test signal at the same time and perform parallel test operations.

That is, as shown in FIG. 6, all 16 tag chips selected in the first test operation are simultaneously tested.

When the failed tag chip is passed without generating in the first test operation, the next 16 selected tag chips are simultaneously tested in parallel by setting the tag chips to be tested next in the second test operation.

Subsequently, if the failed tag chip is passed without being generated in the second test operation, the next 16 selected tag chips are simultaneously tested by setting the tag chips to be tested next in the third test operation.

In this way, when all the selected tag chips pass without the fail chip in the corresponding tag chips in the full test operation mode, the parallel test operation according to the full test mode continues.

On the other hand, as shown in FIG. 7, when one or more failed tag chips are generated during the parallel test operation according to the full test mode, the test mode is changed.

That is, when the full test mode is set because the test mode signals M1 and M0 are all '0' bits, 16 tag chips are simultaneously tested in parallel during the first test operation.

That is, a plurality of selected tag chips (eg, 16 tags) receive the same test signal at the same time and perform parallel test operation.

In this case, when a test result for all selected tag chips is passed, a full test mode for testing the next tag chips is continuously performed. However, if a failure occurs in one or more tag chips during the full test mode, the full test mode is terminated.

That is, when a failed tag chip is generated during parallel test operation according to the full test mode, the test mode signal M1 becomes a '0' bit, and the test mode signal M0 becomes a '1' bit. Is set.

Accordingly, when the half test mode is set, the 16 tag chips selected in the full test mode are divided into two subgroups.

In addition, tag chips of each subgroup divided into two subgroups perform parallel tests simultaneously according to the same test signal.

That is, in the second test operation, eight tag chips of the first group including the tag chip failed in the first test operation are selected and simultaneously tested in parallel.

In the third test operation, eight tag chips of the second group of normal tag chips are simultaneously tested in parallel.

Next, when one or more failed tag chips are generated in the tag chips of the selected subgroup during the parallel test operation according to the half test mode, the half test mode is terminated.

Then, the test mode signal M1 becomes the '1' bit, the test mode signal M0 becomes the '0' bit, and the test mode is set to the quarter test mode.

Accordingly, when the quarter test mode is set, eight tag chips selected in the half test mode are divided into two subgroups.

In addition, tag chips of each subgroup divided into two subgroups perform parallel tests simultaneously according to the same test signal.

That is, in the fourth test operation, four tag chips of the first group including the tag chip failed in the second test operation are selected and simultaneously tested in parallel.

In the fifth test operation, four tag chips of the second group of normal tag chips are simultaneously tested in parallel.

Subsequently, if one or more failed tag chips are generated in the tag chips of the selected subgroup during the parallel test operation according to the quarter test mode, the quarter test mode is terminated.

The test mode signals M1 and M0 both become '1' bits, and the test mode is set to the item test mode.

Accordingly, when the item test mode is set, each of the four tag chips selected in the quarter test mode performs an individual test.

That is, during the sixth test operation, the failed tag chip is selected in the fourth test operation and individual tests are performed.

In the seventh, eighth and ninth test operations, the remaining three normal tag chips receive individual test signals and perform a test operation in a single chip unit.

1 is an overall configuration diagram of a conventional RFID tag chip.

2 is an overall configuration diagram of an RFID tag chip according to the present invention.

3 is an overall configuration diagram of a test system including the RFID device according to the present invention.

4 is a view showing the arrangement of the test chip and the tag chip on the wafer of the RFID device according to the present invention.

5 is a flow chart for explaining a test method of the RFID device according to the present invention.

6 and 7 are views for explaining a test method of the RFID device according to the present invention.

Claims (37)

Simultaneously test a plurality of tag chips according to a test mode signal, output a test output signal corresponding to a test result to the outside, receive a radio signal received from the outside, and modulate the response signal generated by processing the radio signal. Tag chip array for transmitting to the outside via the antenna; And And a test chip outputting the test mode signal for testing the tag chip array according to a test control signal applied from an external device in a test mode. The test chip performs a test operation by dividing the plurality of tag chips into units of a predetermined subgroup according to the test mode signal, and the tag chip array includes a tag chip included in the subgroup according to the test mode signal. RFID device characterized in that the number is changed. delete Claim 3 has been abandoned due to the setting registration fee. The RFID device of claim 1, wherein the test chip changes a bit combination of the test mode signal according to the test control signal. Claim 4 has been abandoned due to the setting registration fee. The RFID device of claim 1, wherein the tag chip array changes a test mode according to the test mode signal when one or more failed chips are generated in the plurality of tag chips. Claim 5 was abandoned upon payment of a set-up fee. The RFID device of claim 4, wherein the test mode comprises a full test mode, a half test mode, a quarter test mode, and an item test mode. Claim 6 has been abandoned due to the setting registration fee. The RFID device of claim 5, wherein the plurality of tag chips are simultaneously tested when the test mode is the full test mode. Claim 7 has been abandoned due to the setting registration fee. The RFID device of claim 5, wherein when the test mode is the half test mode, the plurality of tag chips are divided into two subgroup units to test each subgroup simultaneously. Claim 8 was abandoned when the registration fee was paid. The RFID device of claim 5, wherein when the test mode is the quarter test mode, each subgroup is simultaneously tested by dividing one subgroup selected in the half test mode into two subgroup units. Claim 9 has been abandoned due to the setting registration fee. 9. The RFID device of claim 8, wherein the selected one subgroup has at least one tag tag failed. Claim 10 has been abandoned due to the setting registration fee. Claim 11 was abandoned upon payment of a setup registration fee. The RFID device according to claim 10, wherein the selected one subgroup has at least one tag tag failed. Claim 12 is abandoned in setting registration fee. The RFID device of claim 1, wherein each of the tag chip arrays includes a test controller configured to receive the test mode signal and control whether each tag chip is activated. External test equipment for outputting a test mode signal for controlling a test operation; And According to the test mode signal, a plurality of tag chips are divided into units of a predetermined subgroup, tag tags of each subgroup unit are simultaneously tested, and the number of tag chips included in the subgroup is changed according to the test mode signal. Including RFID devices, Each of the plurality of tag chips Receiving a radio signal received from the outside, the test system comprising an RFID device characterized in that for modulating the response signal generated by processing the radio signal transmitted to the outside via an antenna. delete Claim 15 is abandoned in the setting registration fee payment. The method of claim 13, wherein the RFID device is A test chip transferring the test mode signal applied from the external test equipment in a test mode; And And a tag chip array configured to simultaneously test the tag chips of the subgroup unit selected according to the test mode signal, and output a test output signal corresponding to a test result to the test chip. system. Claim 16 has been abandoned due to the setting registration fee. The test system of claim 15, further comprising a probe card connecting the external test equipment and the test chip. delete Claim 18 has been abandoned due to the setting registration fee. The test system of claim 15, wherein the RFID device changes a test mode according to a bit combination of the test mode signals. Claim 19 is abandoned in setting registration fee. 16. The test system of claim 15, wherein the RFID device changes a test mode according to the test mode signal when one or more failed chips are generated in the plurality of tag chips. Claim 20 has been abandoned due to the setting registration fee. 20. The test system of claim 19, wherein the test mode comprises a full test mode, a half test mode, a quarter test mode, and an item test mode. Claim 21 has been abandoned due to the setting registration fee. The test system of claim 20, wherein the plurality of tag chips are simultaneously tested when the test mode is the full test mode. Claim 22 is abandoned in setting registration fee. 21. The test system of claim 20, wherein when the test mode is the half test mode, the plurality of tag chips are divided into two sub group units to simultaneously test each sub group. Claim 23 has been abandoned due to the setting registration fee. 21. The method of claim 20, wherein when the test mode is the quarter test mode, the RFID device comprises simultaneously testing each subgroup by dividing one subgroup selected in the half test mode into two subgroup units. Testing system. Claim 24 is abandoned in setting registration fee. 24. The test system of claim 23, wherein the selected one subgroup has at least one failed tag chip. Claim 25 is abandoned in setting registration fee. 21. The test method of claim 20, wherein when the test mode is the item test mode, a test is performed by separately classifying one subgroup selected in the quarter test mode into units of a single tag chip. system. Claim 26 is abandoned in setting registration fee. 27. The test system of claim 25, wherein the selected one subgroup has at least one failed tag chip. Claim 27 was abandoned upon payment of a registration fee. The test system of claim 15, wherein the RFID device comprises a test controller configured to receive the test mode signal and control whether or not each tag chip is activated. Claim 28 has been abandoned due to the set registration fee. The test system of claim 15 wherein the RFID device is formed on a wafer level. A plurality of test chips formed on a wafer level and a test operation controlled by the test chips to receive a radio signal received from the outside, modulate a response signal generated by processing the radio signal, and transmit the modulated response signal to the outside through an antenna In a test method of an RFID device comprising two tag chips, Setting a tag chip to be tested according to a test control signal applied from the outside and dividing the tag chips into subgroup units to perform a test operation; Determining whether there is a failed tag chip as a result of performing the test operation; And Performing a previous test operation when there is no failed tag chip, and changing the number of tag chips included in the subgroup by changing a test mode according to a test mode signal when the failed tag chip exists. The test method of the RFID device, characterized in that. Claim 30 has been abandoned due to the set registration fee. 30. The method of claim 29, wherein the performing of the test operation comprises selecting the plurality of tag chips at the same time and performing a test operation. Claim 31 has been abandoned due to the setting registration fee. 30. The method of claim 29, wherein changing the test mode Setting the test mode to a half test mode; Setting the test mode to a quarter test mode; And And setting the test mode to an item test mode. Claim 32 is abandoned due to the set registration fee. The method of claim 31, wherein the setting to the half test mode And testing the tag chips of each subgroup unit at the same time. Claim 33 was abandoned upon payment of a registration fee. 32. The method of claim 31, wherein setting to the quarter test mode Dividing one subgroup selected in the half test mode into two subgroup units according to the test mode signal; And And testing the tag chips of each subgroup unit at the same time. Claim 34 was abandoned upon payment of a registration fee. 34. The test method of claim 33, wherein the selected one subgroup has at least one failed tag chip. Claim 35 was abandoned upon payment of a registration fee. 32. The method of claim 31, wherein setting to the item test mode Dividing one subgroup selected in the quarter test mode into each single tag chip unit according to the test mode signal; And Testing each single tag chip individually. Claim 36 is abandoned in setting registration fee. Claim 37 is abandoned in setting registration fee. 30. The method of claim 29, further comprising binning the failed tag chip.

Images