KR101068351B1 - RFID device and test method thereof - Google Patents

Abstract

The present invention relates to an RFID device and a test method thereof, and discloses a technique for testing an RFID tag by receiving different types of tag selection addresses and memory addresses in time division through a common test pad. According to the present invention, a test is performed according to a test input signal applied from the outside, and an tag chip for outputting a test output signal corresponding to the test result to the outside and an address applied from the outside through one common test pad in the test mode. And a test chip for testing the tag chip according to the data.

Description

RGB device and test method {RFID device and test method

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an RFID device and a test method thereof, wherein an RFID tag receives different types of tag selection addresses and memory addresses in time divisions through a common test pad without using radio frequency signals applied from an antenna at a wafer level. It is a technology to test the performance of the chip (Radio Frequency IDentification Tag Chip).

RFID (Radio Frequency IDentification Tag Chip) is a contactless automatic identification method that communicates with an RFID reader by attaching an RFID tag to an object to be identified and automatically transmitting and receiving it by using a wireless signal. To provide technology. As RFID is used, it is possible to compensate for the disadvantages of the conventional automatic identification technology, barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

Meanwhile, a nonvolatile ferroelectric memory may be used as a memory used for an RFID tag.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is an overall configuration diagram of a general RFID device.

The RFID device according to the related art includes an antenna unit 1, an analog unit 10, a digital unit 20, and a memory unit 30.

Here, the antenna unit 1 serves to receive a radio signal transmitted from an external RFID reader. The wireless signal received through the antenna unit 1 is input to the analog unit 10 through the antenna pads 11 and 12.

The analog unit 10 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 20. In addition, the analog unit 10 senses the output voltage VDD and outputs a power-on reset signal POR and a clock CLK to the digital unit 20 for controlling the reset operation.

The digital unit 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 10, and outputs a response signal RP to the analog unit 10. The digital unit 20 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 30.

In addition, the memory unit 30 reads / writes data using a memory element and stores the data.

Here, the RFID device uses a frequency of several bands, the characteristics of which vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the RFID device operates in a short distance, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

The most preferable method for testing whether the RFID tag is operating normally is as follows. Applying a radio signal through the antenna pad (11, 12) of the individual RFID tag, modulates the response signal RP generated by processing the radio signal by the digital unit 20 inside the RFID tag and transmits to the RFID reader, RFID It is to check whether the signal received from the reader is the desired signal.

However, it is expensive and inefficient to test by individually applying radio signals to thousands or more RFID tags per wafer.

The present invention has been made to solve the above problems, and has the following object.

First, the purpose of the present invention is to test the performance of an RFID tag chip by directly applying a measurement signal through a test pad without using a wireless signal applied from an antenna at a wafer level.

Second, the purpose is to test the performance of the RFID tag chip by receiving different types of tag selection addresses and memory addresses in time division through a common test pad.

Third, one test chip is placed in a tag chip array, and all tag chips on the tag chip array can be tested through one test chip.

Fourth, the purpose is to reduce the number of pads of the test chip and reduce the layout area of the test chip by receiving all the tag selection address, memory address and input / output data for selecting the tag chip using the common test pad. .

In order to achieve the above object, the RFID device of the present invention receives a radio signal received from the outside through an antenna, modulates a response signal generated by processing the radio signal, and transmits the modulated response signal to the outside through an antenna and is applied from the outside. A tag chip configured to perform a test according to the test input signal, and output a test output signal corresponding to the test result to the outside; And a test chip for testing a tag chip according to an address and data applied from the outside through one common test pad in the test mode, wherein the test chip receives the address and data through the common test pad in a time-division manner. It is characterized by.

The present invention may further include an analog unit configured to output a command signal according to a test input signal applied from the outside and output a test output signal corresponding to the response signal to the outside; A digital unit outputting operation control signals according to the command signal and outputting a response signal to the analog unit; A memory unit for reading / writing data to the cell array according to an internal control signal; A test interface unit configured to generate internal control signals according to an address and data applied from the outside when the test activation signal is activated, perform a test of the memory unit, and output a response signal corresponding to a result of the test to the outside; And a common test pad receiving an address and data from an external source in a time division manner.

In addition, a test method of an RFID device according to the present invention includes an analog unit, a digital unit, a memory unit, and a test interface unit for testing a memory unit according to an address and data applied from the outside through one common test pad in a test mode. A test method of an RFID device, the method comprising: sequentially receiving an address and data through a common test pad; Performing a test operation of the memory unit according to an address and data applied through a common test pad; And outputting a test result of the memory unit to the outside through a common test pad.

As described above, the present invention has the following effects.

First, the present invention facilitates the test of the performance of an RFID tag chip by directly applying a measurement signal through a test pad at the wafer level.

Second, different types of tag selection addresses and memory addresses are inputted in time division through common test pads, so that the performance of the RFID tag chip can be easily tested.

Third, one test chip may be placed on the tag chip array, and all tag chips on the tag chip array may be tested through one test chip, thereby reducing the time and cost required for the test.

Fourth, by using a common test pad, the tag selection address, memory address, and input / output data for selecting a tag chip are all input, thereby reducing the number of pads of the test chip and reducing the layout area of the test chip. .

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such configuration changes, etc. It should be seen as belonging to a range.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an RFID tag chip in the RFID device according to the present invention.

The present invention does not receive a radio signal applied from the antenna 1 like the above-described conventional RFID device, but directly receives a measurement signal through a common test pad at a wafer level, and generates an RFID tag chip. To test the performance of

The RFID device of the present invention largely includes an analog unit 100, a digital unit 200, a test interface unit 300, a memory unit 400, and a test control unit 500.

First, the analog unit 100 includes a voltage amplifier 110, a modulator 120, a demodulator 130, a power-on reset unit 140, a clock generator 150, and a test input buffer. 160 and a test output driver 170.

Here, the voltage amplifier 110 generates a driving voltage of the RFID according to the power supply voltage VDD applied from the power supply voltage application pad P2.

The modulator 120 modulates the response signal RP input from the digital unit 200. The demodulator 130 generates an operation command signal DEMOD according to the output voltage of the power supply voltage application pad P2, and outputs the generated operation command signal DEMOD to the test input buffer 160.

The power on reset unit 140 detects a voltage applied from the power supply voltage applying pad P2 and outputs a power on reset signal POR for controlling the reset operation to the digital unit 200. The clock generator 150 supplies the clock CLK for controlling the operation of the digital unit 200 according to the output voltage of the power supply voltage application pad P2 to the digital unit 200.

Here, the power-on reset signal POR rises together with the power supply voltage while the power supply voltage transitions from the low level to the high level, and then transitions from the high level to the low level at the moment the power supply is supplied to the power supply voltage level VDD, thereby causing a circuit inside the RFID tag. Means a signal to reset.

The test input buffer 160 commands a command according to a test input signal RXI input through the test signal input pad P4, an operation command signal DEMOD input from the demodulator 130, and a test activation signal TSTEN applied from the test control unit 500. The signal CMD is output to the digital unit 200.

That is, the test input buffer 160 supplies the command signal CMD to the digital unit 200 according to the operation command signal DEMOD applied from the demodulator 130 when the test activation signal TSTEN is deactivated in the normal operation mode.

On the other hand, when the test activation signal TSTEN is activated in the test operation mode, the test input buffer 160 transmits a command signal CMD for testing RFID according to the test input signal RXI applied from the test signal input pad P4 to the digital unit 200. Supply.

In addition, the test output driver 170 drives the test output signal TXO according to the response signal RP input from the digital unit 200, and outputs the command processing result of the RFID to the outside through the test signal output pad P1.

Here, the voltage amplifier 110, the modulator 120, the demodulator 130, the power-on reset unit 140, the clock generator 150, the test input buffer 160 and the test output driver 170 are In the test operation mode for testing the performance of the RFID, it is driven by the power supply voltage VDD applied from the external power supply voltage application pad P2 and the ground voltage GND applied from the external ground voltage application pad P3.

That is, the power supply voltage applying pad P2 indicates a pad to which the power supply voltage VDD is applied when the RFID tag is activated to test a plurality of RFID tags on the wafer. The ground voltage applying pad P3 represents a pad to which the ground voltage GND is applied when the plurality of RFID tags are tested on the wafer.

When the RFID tag communicates with the RFID reader to receive a wireless signal, the voltage amplifier 110 supplies the power supply voltage VDD. However, in the present invention, since the test is performed on the wafer, a separate power supply voltage pad P2 and ground voltage are performed. The supply voltage VDD and the ground voltage GND are supplied through the application pad P3.

The digital unit 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 100 to interpret the command signal CMD and generate control signals and processing signals. The digital unit 200 outputs the response signal RP corresponding to the control signal and the processing signals to the analog unit 100.

In addition, the digital unit 200 outputs the address DADD, the input data DI, the chip enable signal DCE, the write enable signal DWE, and the output enable signal DOE to the test interface unit 300. The digital unit 200 receives the output data DO from the test interface unit 300.

In addition, the test interface unit 300 is activated according to the test activation signal TSTEN applied from the test control unit 500. When the test interface 300 is activated, the memory unit according to the tag selection addresses X0 to X7, the memory addresses XA0 to XA7, the input data XDI0 to XDI7, the control signals DIN_LATP, ADD_LATP, XCE, XWE, XOE, and TACT input from the outside. Test 400.

Among the control signals described above, DIN_LATP represents a data latch enable signal, ADD_LATP represents an address latch enable signal, and XCE represents a chip enable signal. Among the control signals, XWE represents a write enable signal, XOE represents an output enable signal, and TACT represents a test operation signal.

Here, the test interface unit 300 may include tag selection addresses X0 to X7, memory addresses XA0 to XA7, input data XDI0 to XDI7, and control signal input pads P6, P7, P9 to P11 that are input through the common test pad P5. The memory unit 400 is tested by generating the address ADD and the control signals I, CE, WE, and OE according to the control signals DIN_LATP, ADD_LATP, XCE, XWE, XOE, and TACT input through the test input pad P12.

The test interface unit 300 receives the control result signal O and outputs the output data XDO to the outside through the data output pad P8.

Meanwhile, when the test interface unit 300 is activated, the internal circuits included in the RFID tag, that is, the analog unit 100 and the digital unit according to the address DADD and the control signals DI, DCE, DWE, and DOE input from the digital unit 200. The unit 200 and the memory unit 400 are tested.

To test the entire operation of the RFID tag, the digital unit 200 generates the address DADD and the control signals DI, DCE, DWE, and DOE by the command signal CMD generated according to the test input signal RXI.

The test interface 300 generates the address ADD and the control signals I, CE, WE, and OE according to the address DADD and the control signals DI, DCE, DWE, and DOE to test the entire operation of the RFID tag. In addition, the test interface unit 300 receives the control result signal O which is a test result from the memory unit 400 and generates the control result signal DO.

The digital unit 200 generates a response signal RP according to the control result signal DO. In addition, the test output driver 170 drives the response signal RP and outputs it through the test signal output pad P1.

The memory unit 400 includes a plurality of memory cells, each memory cell writes data to a storage element, and serves to read data stored in the storage element.

Here, the memory unit 400 may be a nonvolatile ferroelectric memory (FeRAM). FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

The test control unit 500 serves to activate the RFID tag in the test mode. The test control unit 500 receives a test operation signal TACT from the test input pad P12 and a test clock TCLK from the test clock input pad P13. The test controller 500 outputs a test activation signal TSTEN for controlling whether the RFID tag is activated to the test input buffer 160 and the test interface unit 300.

As described above, when the test activation signal TSTEN is activated in the test mode, the present invention outputs a test result of the RFID device through the test signal output pad P1 or externally through the data output pad P8.

That is, when testing the entire operation of the RFID device, the test input signal RXI input through the test signal input pad P4 is transmitted to the digital unit 200, the test interface unit 300, and the memory unit 400, and the test is performed again. The interface unit 300 and the digital unit 200 are output through the test output pad P1 via the test output driver 170. Then, the external test equipment measures the output of the test signal output pad P1 to test the entire operation of the RFID device.

On the other hand, when only testing the memory unit 400 of the RFID device, the address and data input through the common test pad P5 is transferred to the memory unit 400 via the test interface unit 300, and again the test interface unit ( 300 is output via the data output pad P8. Then, the external test equipment measures the output of the data output pad P8 to test the operation of the memory unit 400.

3 is a flowchart illustrating a test method of an RFID device according to the present invention.

First, the tag selection address X is applied through the common test pad P5, and the corresponding tag chip is activated. (Step S1) Next, the memory address XA is applied through the common test pad P5, and the corresponding address is applied. (Step S2) After that, input data is applied through the common test pad P5, and the corresponding input data is activated (Step S3).

The present invention controls the different tag selection addresses X, the memory addresses XA, and the input data XDI through the common test pad P5 so that they can be input at different time points. .

4 is a flowchart illustrating a test operation process of a tag chip through the test interface unit 300 in the RFID device according to the present invention.

First, when the power supply voltage VDD is applied, the test chip is initialized and activated first (step S11). Then, the tag selection address X for selecting the first tag chip through the common test pad P5 is provided in the test interface unit 300. (Step S12).

Thereafter, when the first test operation signal TACT and the test clock TCLK are applied with a high pulse, the test activation signal TSTEN is activated (step S13).

Then, when the test activation signal TSTEN is activated to a high level, the corresponding tag chip is activated (step S14).

Next, memory addresses XA0 to XA7 for selecting a corresponding address through the common test pad P5 are applied to the test interface unit 300 (step S15).

Thereafter, the address latch activation signal ADD_LATP is applied to the test interface unit 300 through the pad P7 (step S16).

Subsequently, input data XDI0 to XDI7 are applied to the test interface unit 300 through the common test pad P5. (Step S17) At this time, the output data XDO is output through the data output pad P8.

Next, the data latch activation signal DIN_LATP is applied to the test interface unit 300 via the pad P6 (step S18).

Thereafter, the memory test signal is applied through the input pads P9 to P11 of the chip enable signal XCE, the write enable signal XWE, and the output enable signal XOE (step S19).

Subsequently, it is determined whether the test operation of the first tag chip is terminated (step S20), and when the test is terminated, the tag selection address X for selecting the second tag chip through the common test pad P5 is determined by the test interface unit ( 300) (step S21).

Next, the second test operation signal TACT and the test clock TCLK are applied with a high pulse (step S22).

Thereafter, the steps of performing the above-described test operation are repeated until the last tag chip is activated to complete the test operation.

5 is a view showing the arrangement of the test chip and the tag chip on the wafer of the RFID device according to the present invention.

The present invention forms a tag chip array by forming a plurality of tag chips in a row and column direction on one wafer. Each tag chip array includes a plurality of tag chips. That is, the tag chip array refers to a set of RFID tag chips in which a plurality of tag chips are connected to each other using a scribe line.

One tag chip array includes one test chip and a plurality of tag chips. Here, one test chip is placed at a center position on the tag chip array. One such test chip will test all tag chips placed on the tag chip array.

The "RFID device" defined in the name of the present invention is a concept including both a test chip and a plurality of tag chips at the wafer level.

FIG. 6 is a diagram illustrating a configuration in which a test chip and a tag chip are connected through a scribe line in an RFID device according to the present invention.

The tag chip array according to the present invention includes one test chip and a plurality of tag chips.

The tag chips and the test chip of the present invention allow input / output signals representing test commands and test results to be interchanged through scribe line regions formed between the tag chips. That is, the test chip and the plurality of tag chips are connected to each other by a plurality of scribe lines arranged in the X and Y axis directions.

Accordingly, the power supply voltage VDD, the ground voltage GND, the control signal, the address, and the data supplied from the outside pass through a plurality of scribe lines arranged in the X and Y-axis directions, and the tag chip internal circuit through the input / output pad of the tag chip. Is supplied.

The test output signal TXO and the control result signal generated by the tag chip are output to the outside from the tag chip internal circuit through a plurality of scribe lines arranged in the X and Y axis directions through input / output pads.

Here, in order to test the tag chip array, the test chip is initialized first. Various methods may be used to initialize the test chip. For example, the test chip can be set to initialize when the supply voltage VDD begins to supply through the input / output pads.

7 is a diagram illustrating a pad configuration of a test chip in the RFID device according to the present invention.

The test chip includes a common test pad P5 to which tag selection addresses X0 to X7, memory addresses XA0 to XA7, and input data XDI0 to XDI7 are commonly inputted in time division. The common test pad P5 includes common input pads P50 to P57 for applying tag selection addresses X0 to X7, memory addresses XA0 to XA7, and input data XDI0 to XDI7, respectively.

The test signal output pad P1 outputs the test output signal TXO to the outside, a power supply voltage applying pad P2 to which the power supply voltage VDD is applied, and a ground voltage application pad P3 to which the ground voltage GND is applied.

Also, a test signal input pad P4 to which the test input signal RXI is applied, a pad P6 to which the data latch activation signal DIN_LATP is applied, and a pad P7 to which the address latch activation signal ADD_LATP is applied.

In addition, a data output pad P8 for outputting the output data XDO which is a control result signal, a pad P9 to which the chip enable signal XCE is applied, a pad P10 to which the write enable signal XWE is applied, and an output enable signal XOE are applied. Pad P11.

And a test input pad P12 to which a test operation signal TACT is applied and a test clock input pad P13 to which a test clock TCLK is applied.

8 is a detailed block diagram of the test interface unit 300 associated with the address latch operation in the RFID device according to the present invention. In the present invention, the case where the tag selection addresses X0 to X7 are input will be described in the embodiment.

The test interface unit 300 includes an address latch unit 310 and an address combiner 320.

Here, the address latch unit 310 receives tag selection addresses X0 to X7 applied from the common test pad P5 when the test activation signal TSTEN is activated. The tag selection addresses X0 to X7 are latched in response to the activation of the address latch activation signal ADD_LATP to output the latched addresses XA0_LAT to XA7_LAT.

The address synthesizing unit 320 synthesizes the latched addresses XA0_LAT to XA7_LAT and the addresses DADD0 to DADD7 applied from the digital unit 200, and outputs the addresses ADD0 to ADD7 to the memory unit 400.

9 is a detailed circuit diagram illustrating the address latch unit 310 of FIG. 8.

The address latch unit 310 includes the transfer gates T1 and T2, the NAND gate ND1, and the inverters IV1 and IV2.

Here, the transfer gate T1 outputs a tag selection address X0 when the address latch activation signal ADD_LATP is activated. On the other hand, the transfer gate T2 latches the tag selection address X0 when the address latch activation signal ADD_LATP is inactivated.

In addition, the NAND gate ND1 and the inverter IV2 output the latched address XA0_LAT when the test activation signal TSTEN is activated. If the test activation signal TSTEN is deactivated to the low level, the latched address XA0_LAT becomes the low level.

FIG. 10 is a detailed circuit diagram illustrating the address synthesizing unit 320 of FIG. 8.

The address synthesizing unit 320 includes a NOA gate NOR1 and an inverter IV3. Here, the NOR gate NOR1 performs a NO operation on the address DADD0 applied from the digital unit 200 and the latched address XA0_LAT and outputs the result. Inverter IV3 inverts the output of NOR gate NOR1 and outputs address ADD0.

The address synthesizing unit 320 having such a configuration performs an OR operation on the address DADD0 and the latched address XA0_LAT to activate the address ADD0 when at least one of the two addresses is activated.

That is, when the test input signal RXI is activated during the test operation of the entire RFID, the internal address ADD0 is generated according to the internal address DADD0 applied through the digital unit 200. In this case, the test interface unit 300 generates the internal control signals CE, WE, and OE according to the control signals DCE, DWE, and DOE applied through the digital unit 200.

On the other hand, when the tag selection address X0 applied through the common test pad P5 is activated during the test operation of the memory unit 400, the internal address ADD0 is generated according to the latched address XA0_LAT. In this case, the test interface unit 300 generates the internal control signals CE, WE, and OE according to external control signals XCE, XWE, and XOE applied through the pads P9 to P11.

FIG. 11 is an operational waveform diagram of the test interface unit 300 of FIG. 8 related to an address latch operation.

First, tag selection addresses X0 to X7 are input to the test interface unit 300 through the common test pad P5. At this time, the test activation signal TSTEN is maintained at a high level for testing the memory unit 400. When the address latch activation signal ADD_LATP is activated to a high level, the address latch unit 310 latches the tag selection addresses X0 to X7 to output the latched addresses XA0_LAT to XA7_LAT.

If the digital unit 200 does not operate, since the addresses DADD0 to DADD7 are set low, the latched addresses XA0_LAT to XA7_LAT are output as they are to the addresses ADD0 to ADD7.

12 is a detailed configuration diagram of the test interface unit 300 associated with the input data latch in the RFID device according to the present invention. In the present invention, a case where input data XDI0 to XDI7 is input will be described as an embodiment.

The test interface unit 300 includes a data latch unit 330 and a data synthesizing unit 340.

Here, the data latch unit 330 receives input data XDI0 to XDI7 applied from the common test pad P5 when the test activation signal TSTEN is activated. Then, in response to the activation of the data latch activation signal DIN_LATP, the input data XDI0 to XDI7 are latched to output the latched data DIN0_LAT to DIN7_LAT.

The data synthesizing unit 340 synthesizes the latched data DIN0_LAT to DIN7_LAT and the data DI0 to DI7 applied from the digital unit 200 and outputs the input data I0 to I7 to the memory unit 400.

FIG. 13 is a detailed circuit diagram illustrating the data latch unit 330 of FIG. 12.

The data latch unit 330 includes transfer gates T3 and T4, NAND gates ND2, and inverters IV4 and IV5.

Here, the transfer gate T3 outputs input data XDI0 upon activation of the data latch activation signal DIN_LATP. On the other hand, the transfer gate T4 latches the input data XDI0 when the data latch activation signal DIN_LATP is inactivated.

In addition, the NAND gate ND2 and the inverter IV5 output the latched data DIN0_LAT upon activation of the test activation signal TSTEN. If the test enable signal TSTEN is deactivated to the low level, the latched data DIN0_LAT goes to the low level.

FIG. 14 is a detailed circuit diagram illustrating the data synthesizing unit 340 of FIG. 12.

The data synthesizing unit 340 includes a NOA gate NOR2 and an inverter IV6. Here, the NOR gate NOR2 performs a NO operation on the data DI0 applied from the digital unit 200 and the latched data DIN0_LAT, and outputs the result. Inverter IV6 inverts the output of NOR gate NOR2 and outputs data I0.

The data synthesizing unit 340 having such a configuration performs OR operation on the data XDI0 and the latched data DIN0_LAT to activate the input data I0 when at least one of the two data is activated.

That is, when the test input signal RXI is activated during the test operation of the entire RFID, the input data I0 is generated according to the internal data DI0 applied through the digital unit 200. On the other hand, when the input data XDI0 applied through the common test pad P5 is activated during the test operation of the memory unit 400, the internal input data I0 is generated according to the latched data DIN0_LAT.

15 is an operation waveform diagram illustrating the test interface unit 300 of FIG. 12.

Input data XDI0 to XDI7 are input to the test interface unit 300 through the common test pad P5. At this time, the test activation signal TSTEN is maintained at a high level. When the data latch activation signal DIN_LATP is activated to a high level, the data latch unit 330 latches the input data XDI0 to XDI7 to output the latched addresses DIN0_LAT to DIN7_LAT.

If the digital unit 200 does not operate, since the data DI0 to DI7 are set low, the latched data DIN0_LAT to DIN7_LAT are output as data I0 to I7 as they are.

1 is an overall configuration diagram of a conventional RFID device.

2 is an overall configuration diagram of an RFID device according to the present invention.

3 is a flowchart illustrating a test method of an RFID device according to the present invention;

4 is a flowchart illustrating an operation process of a test interface unit in the RFID device according to the present invention.

5 is a view showing the arrangement of the test chip and the tag chip on the wafer of the RFID device according to the present invention.

FIG. 6 is a diagram illustrating a configuration in which a test chip and a tag chip are connected through a scribe line in an RFID device according to the present invention. FIG.

7 is a diagram illustrating a pad configuration of a test chip in the RFID device according to the present invention.

8 is a detailed configuration diagram of a test interface unit in the RFID device according to the present invention.

9 is a detailed circuit diagram related to the address latch unit of FIG. 8;

FIG. 10 is a detailed circuit diagram related to the address synthesizing section of FIG. 8; FIG.

FIG. 11 is an operational waveform diagram relating to the test interface unit of FIG. 8. FIG.

12 is a detailed configuration diagram of a data latch unit in the RFID device according to the present invention.

FIG. 13 is a detailed circuit diagram of the data latch unit of FIG. 12; FIG.

14 is a detailed circuit diagram related to the data synthesizing section of FIG.

FIG. 15 is an operational waveform diagram relating to the test interface unit of FIG. 12; FIG.

Claims (32)

Receives a radio signal received from the outside through an antenna, modulates the response signal generated by processing the radio signal and transmits it to the outside through the antenna, the test is performed according to a test input signal applied from the outside, the test A tag chip outputting a test output signal corresponding to a result to the outside; And A test chip for testing the tag chip according to an address and data applied from the outside through one common test pad in a test mode, And the test chip receives the address and the data through the common test pad in a time division manner, respectively. delete The RFID device of claim 1, wherein the address includes a tag selection address and a memory address. The RFID device of claim 3, wherein the tag selection address, the memory address, and the data are sequentially input. The RFID device of claim 1, wherein a plurality of tag chips are arranged in column and row directions to form a tag chip array, and the tag chip array is controlled by a test chip. The RFID device of claim 5, wherein the tag chip and the test chip are interconnected through a scribe line. The RFID device of claim 5, wherein the test chip is disposed at a center position on the tag chip array. The RFID device of claim 1, further comprising a memory unit including a nonvolatile ferroelectric element to perform a read / write operation of data. The method of claim 1, wherein the test chip A test signal output pad outputting the test output signal to the outside; A power supply voltage applying pad to which a power supply voltage is applied; A ground voltage applying pad to which a ground voltage is applied; And a test signal input pad to which the test input signal is applied. 10. The method of claim 1 or 9, wherein the test chip A first pad to which a data latch activation signal is applied to control a latch operation of the data; A second pad to which an address latch activation signal is applied to control the latch operation of the address; A data output pad configured to output a test result of a memory unit from the tag chip to the outside; A third pad to which a chip enable signal from the outside is applied; A fourth pad to which a write enable signal from the outside is applied; A fifth pad to which an output enable signal from the outside is applied; And And a test input pad to which a test operation signal for activating a test mode is applied. 11. The RFID device of claim 10, further comprising a test clock input pad to which a test clock for controlling the operation of the test mode is applied. An analog unit for outputting a command signal according to a test input signal applied from the outside and outputting a test output signal corresponding to the response signal to the outside; A digital unit outputting operation control signals according to the command signal, and outputting the response signal to the analog unit; A memory unit for reading / writing data to the cell array according to an internal control signal; A test interface unit configured to generate the internal control signals according to an address and data applied from the outside when the test activation signal is activated, perform a test of the memory unit, and output the response signal corresponding to a result of the test to the outside; And And a common test pad receiving the address and the data from an external source in a time division manner. The RFID device of claim 12, further comprising a test controller configured to generate the test activation signal according to a test operation signal and a test clock applied from the outside. The method of claim 13, wherein the test control unit A test input pad to which the test operation signal is applied; And And a test clock input pad to which the test clock is applied. delete The RFID device of claim 12, wherein the address comprises a tag selection address and a memory address. 17. The RFID device of claim 16, wherein the tag selection address, the memory address, and the data are sequentially input. The method of claim 12, wherein the test interface unit An address latch unit configured to latch the address according to an address latch activation signal applied from the outside when the test activation signal is activated; And And an address synthesizing unit for synthesizing an output address of the address latch unit and an output address of the digital unit and outputting the synthesized output unit to the memory unit. The method of claim 18, wherein the address latch unit And the output of the address latch unit is at a low level when the test activation signal is at a low level, and latches the address when the address latch activation signal is applied with a high pulse when the test activation signal is activated. 19. The apparatus of claim 18, wherein the address synthesizing unit And at least one of an output address of the address latch unit and an output address of the digital unit outputs a high level address to the memory unit. The method of claim 12, wherein the test interface unit A data latch unit configured to latch the data according to a data latch activation signal applied from the outside when the test activation signal is activated; And And a data synthesizing unit for synthesizing the output address of the data latch unit and the output data of the digital unit and outputting the combined data to the memory unit. 22. The method of claim 21, wherein the data latch unit And the output of the data latch unit is at a low level when the test activation signal is at a low level, and latches the data when the data latch activation signal is applied at a high pulse when the test activation signal is activated. The data synthesizer of claim 21, wherein the data synthesizing unit is used. And at least one of output data of the data latch unit and output data of the digital unit outputs high level data to the memory unit. The method of claim 12, wherein the analog unit A test signal input pad to which the test input signal is applied; A test signal output pad outputting the test output signal to the outside; A power supply voltage applying pad to which a power supply voltage is applied; And And a ground voltage applying pad to which a ground voltage is applied. The method of claim 12, wherein the test interface unit A first pad to which a data latch activation signal is applied to control a latch operation of the data; A second pad to which an address latch activation signal is applied to control the latch operation of the address; A data output pad configured to output a result of performing the test to the outside; A third pad to which a chip enable signal from the outside is applied; A fourth pad to which a write enable signal from the outside is applied; And And a fifth pad to which an output enable signal from the outside is applied. The RFID device of claim 12, wherein the memory unit comprises a nonvolatile ferroelectric element to perform a read / write operation of data. In the test method of the RFID device comprising an analog unit, a digital unit, a memory unit, and a test interface unit for testing the memory unit according to the address and data applied from the outside through one common test pad in the test mode, Sequentially receiving the address and the data through the common test pad; Performing a test operation of a memory unit according to the address and the data applied through the common test pad; And And outputting a test result of the memory unit to the outside through the common test pad. 28. The method of claim 27, wherein receiving the address and the data sequentially Activating a corresponding tag chip by applying a tag selection address for selecting a tag chip through the common test pad; Applying a memory address through the common test pad to activate a corresponding address; And And inputting the input data through the common test pad to activate the corresponding data. The method of claim 28, wherein the tag chip is activated Applying a power supply voltage from the outside; Applying the tag selection address; Applying a test operation signal in synchronization with the test clock; And And the tag chip is activated according to a test activation signal. 29. The method of claim 28, wherein the address is activated Applying the memory address; And And latching the memory address in accordance with an address latch activation signal. 29. The method of claim 28, wherein activating the data Applying the input data; And And latching the input data in response to a data latch activation signal. The method of claim 27, wherein performing the test operation The control method of the RFID device further comprises the step of applying the control signals for testing the tag chip through the control signal input pad from the outside.

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