KR101068313B1 - Rfid tag being tested on the wafer and method thereof - Google Patents

Abstract

The present invention relates to an RFID tag and a test method for performing a test by sequentially activating a plurality of RFID tags by applying a test signal and a power supply voltage directly to an RFID tag on a wafer.

Specifically, the present invention is activated by a shift register for receiving a test serial input signal and a test clock and generating and outputting a test serial output signal, a test serial output signal, i) a test input signal input from the outside during the activation period, or ii) a test circuit unit which performs a test according to an address signal and a control signal, and receives a power supply voltage and a ground voltage from an external source, and receives a test serial input signal, a test clock, a test input signal, an address signal, and a control signal, and tests Disclosed is an RFID tag including an input / output pad unit for outputting a serial output signal.

RFID, tag, test, sequential, serial, active, input, output

Description

RDF tag that can be tested on wafer and test method {RFID TAG BEING TESTED ON THE WAFER AND METHOD THEREOF}

The present invention relates to an RFID tag and a test method for performing a test by sequentially activating a plurality of RFID tags by applying a test signal and a power supply voltage directly to an RFID tag on a wafer.

More specifically, the present invention is activated by a shift register, a test serial output signal that receives a test serial input signal and a test clock and generates and outputs a test serial output signal, and i) a test input input from the outside during the activation period. Signal or ii) a test circuit unit for performing a test according to an address signal and a control signal, and receiving a power supply voltage and a ground voltage from an external source, and receiving a test serial input signal, a test clock, a test input signal, an address signal and a control signal. The present invention relates to an RFID tag including an input / output pad unit for outputting a test serial output signal.

RFID is a technology that provides a contactless automatic identification method that attaches an RFID tag to an object to be identified and communicates with an RFID reader through transmission and reception using a wireless signal to automatically identify the object using a wireless signal. It is a technology that can compensate for the shortcomings of barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

In general, a nonvolatile ferroelectric memory may be used for an RFID tag.

Non-volatile ferroelectric memory, or FeRAM (Ferroelectric Random Access Memory), has a data processing speed of about DRAM (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

RFID uses several bands of frequency, and its characteristics vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the shorter the distance operation, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

1 is an overall configuration diagram of an RFID tag according to the prior art.

Referring to FIG. 1, the RFID tag according to the related art largely includes an antenna unit 10, an analog unit 100, a digital unit 200, and a memory 300.

The antenna unit 10 serves to receive a radio signal transmitted from the RFID reader. The received radio signal is input to the analog unit 100 through the antenna pads 11 and 12.

The analog unit 100 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 200. In addition, the analog unit 100 senses the output voltage VDD and outputs a power-on reset signal POR and a clock signal CLK for controlling the reset operation to the digital unit 200.

The digital unit 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock signal CLK, and the command signal CMD from the analog unit 100, and the address ADD, input / output data I / O, control signal CTR, and clock CLK. Is output to the memory 300.

The memory 300 reads / writes data using a memory device and stores data.

The most preferable method for testing whether the RFID tag operates normally is to apply a radio signal through the antenna pads 11 and 12 of the individual RFID tag, and process the radio signal by the digital unit 200 inside the RFID tag. The response signal RP generated is modulated and transmitted to the RFID reader, and the received signal from the RFID reader is checked to see if it is a desired signal.

However, it is expensive and inefficient to test thousands of RFID tags per wafer individually by applying wireless signals.

In order to solve the above problems, the present invention by applying a test signal, a power supply voltage and a control signal directly to the RFID tag internal circuit through the input / output pad containing the RFID tag on the wafer to sequentially activate the plurality of RFID tags Disclosed is an RFID tag and a test method for performing the method.

The present invention is activated by a shift register for receiving and receiving a test serial input signal and a test clock to generate and output a test serial output signal, and performing a test according to a test input signal input from the outside during the activation period. An RFID tag includes a test circuit unit and an input / output pad unit configured to receive a power supply voltage and a ground voltage from an external source, receive a test serial input signal, a test clock, and a test input signal, and output a test serial output signal.

Additionally, the present invention is activated by a shift register for receiving a test serial input signal and a test clock and generating and outputting a test serial output signal, and being activated by a test serial output signal, according to an address signal and a control signal input from the outside during the activation period. And an input / output pad unit configured to receive a power supply voltage and a ground voltage from an external source, receive a test serial input signal, a test clock and an address signal, and a control signal, and output a test serial output signal. An RFID tag is disclosed.

In addition, the present invention is activated by a test register and a shift register for receiving a test serial input signal and a test clock and generating and outputting a test serial output signal, and performing a test according to a test input signal input from the outside during the activation period. Test an RFID tag including a test circuit unit to perform a power supply, a ground voltage, a test serial input signal, a test clock and a test input signal, and outputs a test serial output signal. The method may include: activating a test circuit unit by a test serial output signal, inputting a test input signal through an input / output pad unit, and performing a test operation and generating a test output signal according to the test input signal. only It discloses, outputting a test output signal to the outside, and the test input signal and an RFID tag test comprises comparing the test output signal.

Finally, the present invention is activated by a shift register that receives the test serial input signal and the test clock and generates and outputs a test serial output signal, and is activated by a test serial output signal. A test circuit unit for performing a test according to the present invention, and an input / output pad unit for receiving a power supply voltage and a ground voltage from an external device, receiving a test serial input signal, a test clock, an address signal, and a control signal, and outputting a test serial output signal. A method of testing an RFID tag, the method comprising: activating a test circuit unit by a test serial output signal, inputting an address signal and a control signal through an input / output pad unit, and testing the test circuit unit according to the address signal and the control signal To perform an action A method of testing an RFID tag comprising generating a high test output signal, outputting a test output signal to the outside, and comparing the test input signal with the test output signal.

First, the present invention has the advantage of reducing the time required for testing by setting a plurality of RFID tags as one RFID tag array and testing a plurality of RFID tags included in the RFID tag array. For example, suppose you are testing 100,000 RFID tags. If you test 100,000 each, it will take 100,000 seconds each. However, if you test in an RFID tag array unit containing 1000 RFID tags, 100 RFID tags will be tested. Since the array can be tested at the same time, it takes 1000 seconds to reduce test time.

Second, the present invention does not need to activate all RFID tags on a wafer because one test chip is set for each tag array, and only the test chip is initialized, a plurality of RFID tags connected to the test chip are sequentially activated to perform a test. Therefore, a test on a plurality of RFID tags can be easily performed.

Third, in the present invention, one test chip is set for each tag array, and if only the test chip is initialized, test output signals are sequentially transmitted between serially connected RFID tags to activate the RFID tag and perform a test. If all the RFID tags are simultaneously input / output with the test input / output signals, then an additional scribe line is required for input / output of the test input / output signals. However, since the present invention only needs to connect a plurality of RFID tags in series without additional scribe lines, the layout is reduced and the circuit configuration is simplified.

Hereinafter, with reference to the accompanying drawings will be described an embodiment of the present invention;

2 is a block diagram illustrating a wafer including a plurality of RFID tag arrays according to the present invention.

Referring to FIG. 2, a plurality of RFID tag arrays are arranged on one wafer. Each RFID tag array includes a plurality of RFID tags (not shown). That is, the RFID tag array refers to a set of RFID tags in which a plurality of RFID tags are connected to each other using a scribe line.

3 is a block diagram showing the configuration of one RFID tag array according to the present invention.

Referring to FIG. 3, one RFID tag array includes one test chip and a plurality of RFID tags. The test chip is initialized and activated first when the power supply voltage is supplied, and the RFID tags TAG01 to RFID tags TAGN are sequentially activated.

4 is a block diagram illustrating a process of sequentially activating a plurality of RFID tags in the RFID tag array according to the present invention.

Referring to FIG. 4, when the test chip is initialized, the RFID tags TAG01 to TAG09 are sequentially activated in the positive direction of the X axis in the first row to perform a test operation on each RFID tag in the first row. In the second row, the RFID tags TAG10 to TAG19 are sequentially activated in the negative direction of the X axis to perform a test operation on each of the RFID tags in the second row. In the third row, the RFID tags TAG20 to TAG29 are sequentially activated in the positive direction of the X axis to perform a test operation on the RFID tag of the third row. In this manner, all RFID tags included in the RFID tag array are sequentially activated to perform a test operation.

The order is exemplary, and the order of activating the plurality of RFID tags can be changed by changing the arrangement of the scribe lines according to the user's intention. For example, i) after activating the RFID tag in the negative direction of the Y axis for the first column, and activating the RFID tag in the positive direction of the Y axis for the second column, or ii) diagonally, that is, the RFID tag TAG01, The RFID tag may be activated in the order of the RFID tag TAG19, the RFID tag TAG20, and the RFID tag TAG18.

5 is a circuit diagram illustrating an RFID tag array according to the present invention.

Referring to FIG. 5, an RFID tag array according to the present invention includes one test chip and a plurality of RFID tags.

The power supply voltage VDD and ground voltage GND supplied from the outside are supplied to the RFID tag internal circuit through the input / output pad of the RFID tag via a plurality of scribe lines arranged in the X and Y axis directions.

Test input signals TI, test clock TCLK, control signals, and address signals input from the outside are input to the RFID tag internal circuit through the RFID tag input / output pads through a plurality of scribe lines arranged in the X and Y axis directions. do.

The test output signal TO and the control result signal generated from the RFID tag are output to the outside from the RFID tag internal circuit through a plurality of scribe lines arranged in the X and Y-axis directions through the input / output pad of the RFID tag.

The test chip and the RFID tag TAG01 and each of the RFID tags TAG02 to TAGN are connected to each other by a plurality of scribe lines arranged in the X and Y axis directions. Through this scribe line, test serial input signals and test serial output signals are sequentially transmitted between RFID tags.

6 is a circuit diagram illustrating a process of sequentially activating a plurality of RFID tags included in an RFID tag array according to the present invention and testing them during an activation period.

Referring to FIG. 6, in order to test an RFID tag array, a test chip is initialized first. Various methods may be used to initialize the test chip. For example, the test chip can be set to initialize when the supply voltage VDD begins to supply through the input / output pads.

When the test chip is initialized, the test serial input signal is input from the input terminal TS000 to the input terminal TSI01 of the RFID tag TAG01.

The RFID tag TAG01 is activated in synchronization with the test clock TCLK with the supply voltage VDD and ground voltage GND supplied and a test serial input signal. When the RFID tag TAG01 is activated, the test input signal TI is input to the RFID tag TAG01 through the input / output pad to perform a test operation.

When the test operation for the RFID tag TAG01 ends, a test serial output signal is generated in synchronization with the test clock TCLK. The test serial output signal is then sent from the output terminal TS001 to the input terminal TSI02.

7 is a circuit diagram illustrating a process of sequentially activating a plurality of RFID tags included in an RFID tag array according to the present invention and testing them during an activation period.

Referring to FIG. 7, the RFID tag TAG02 is activated in synchronization with the test clock TCLK while a power supply voltage VDD and a ground voltage GND are supplied and a test serial output signal is input. When the RFID tag TAG02 is activated, the test input signal TI is input to the RFID tag TAG02 through the input / output pad to perform a test operation.

When the test operation for the RFID tag TAG02 ends, a test serial output signal is generated in synchronization with the test clock TCLK. The test serial output signal is then sent from the output terminal TS002 to the input terminal TSI03.

Similarly, as the test serial output signal is transmitted to the RFID tags TAG03 to TAGN, each RFID tag is activated and a test operation can be performed during the activation period.

8 is a circuit diagram illustrating a configuration in which each RFID tag is connected through a scribe line in the RFID tag array according to the present invention.

Referring to FIG. 8, an RFID tag array according to the present invention includes one test chip and a plurality of RFID tags. The plurality of scribe lines arranged in the X and Y axis directions may be formed in different layers such as the M1 and M2 layers.

The scribe lines are formed in the M1 layer in the X axis direction, and the scribe lines are formed in the M2 layer in the Y axis direction. The scribe line of the M1 layer and the scribe line of the M2 layer are connected to each other through a contact.

The power supply voltage and ground voltage supplied from the outside pass through the scribe lines arranged in the X-axis direction of the M1 layer, the contacts, and the scribe lines arranged in the Y-axis direction of the M2 layer. Supplied to the circuit.

The test input signal, test clock, control signal, and address signal input from the outside are input / received through the scribe lines arranged in the X axis direction of the M1 layer, the contacts, and the scribe lines arranged in the Y axis direction of the M2 layer. The output pad is input into the RFID tag internal circuit.

The test output signal, test serial output signal, and control output signal generated from the RFID tag can be read from the scribe lines, contacts, and M1 layer arranged in the Y-axis direction of the M2 layer from the RFID tag internal circuit through the input / output pad of the RFID tag. It is output to the outside via the scribe lines arranged in the X axis direction in order.

The test serial input signal and the test serial output signal are scribe lines arranged in the Y axis direction of the M2 layer, contacts, scribe lines arranged in the X axis direction of the M1 layer, contacts, scribe lines arranged in the Y axis direction of the M2 layer. Through the test chip, the RFID tag TAG01 is transmitted between each RFID tag TAG02 to TAGN.

9 is an overall configuration diagram of an RFID tag according to a first embodiment of the present invention.

Referring to FIG. 9, the RFID tag according to the first embodiment of the present invention includes an antenna unit 10, an analog unit 100, a digital unit 200, and a memory 300.

The antenna unit 10 serves to receive a radio signal transmitted from the RFID reader. The received radio signal is input to the analog unit 100 through the antenna pads 11 and 12.

The analog unit 100 includes a voltage amplifier 110, a demodulator 120, a clock generator 130, a power-on reset unit 140, a test input buffer 150, a modulator 160, and a test output driver. And 170.

The voltage amplifying unit 110 rectifies and boosts a radio signal applied from the antenna unit 10 to generate a power supply voltage which is a driving voltage of the RFID tag.

The demodulator 120 demodulates a radio signal input from the antenna unit 10 according to the output voltage of the voltage amplifier 110 to generate a demodulated signal DEMOD, and converts the generated demodulated signal DEMOD into the test input buffer 150. Output

The clock generator 130 supplies the clock CLK for controlling the operation of the digital unit 200 according to the power voltage generated by the voltage amplifier 110 to the digital unit 200.

The power on reset unit 140 detects a power supply voltage generated by the voltage amplifier 110 and outputs a power on reset signal POR for controlling the reset operation to the voltage adjusting unit 120 and the digital unit 200.

The power-on reset signal POR rises together with the power supply voltage while the power supply voltage transitions from the low level to the high level, and then transitions from the high level to the low level as soon as the power supply voltage is supplied to the power supply voltage level VDD to break the circuit inside the RFID tag. It means the signal to reset.

The test input buffer 150 detects an operation command signal from the test input signal TI input through the test signal input pad 13 and the demodulation signal DEMOD input from the demodulator 120 to generate a command signal CMD.

The modulator 160 modulates the response signal RP input from the digital unit 200 and transmits the modulated response signal RP to the antenna unit 10.

The power supply voltage application pad 15 represents a pad to which the power supply voltage VDD is applied when the RFID tag is activated to test the plurality of RFID tags on the wafer, and the ground voltage application pad 16 is used to test the plurality of RFID tags on the wafer. When the ground voltage GND is applied to the pad.

That is, when the RFID tag communicates with the RFID reader to receive the radio signal, the voltage amplifier 110 supplies the power supply voltage VDD. However, in the present invention, since the test is performed on the wafer, a separate power supply voltage application pad 15 is provided. And a power supply voltage VDD and a ground voltage GND are supplied through the ground voltage applying pad 16.

The test output driver 170 drives the test output signal TO according to the response signal RP input from the digital unit 200 and outputs the test output signal TO through the test signal output pad 14.

The digital unit 200 receives a power supply voltage, a power-on reset signal POR, a clock CLK, and a command signal CMD from the analog unit 100 to interpret the command signal CMD and generate control signals and processing signals. The response signal RP corresponding to the control signal and the processing signal is output to the analog unit 100.

The digital unit 200 includes a slot counter controller 210 for activating an RFID tag. The slot counter controller 210 receives a test clock TCLK from the test clock input pad 201, a test serial input signal or a test serial output signal from the test serial signal input pad 202, and the power-on reset unit 140. ) Receives the power-on reset signal POR. The slot counter controller 210 generates slot counter bits to control whether the RFID tag is activated, and generates a test serial output signal and outputs the test serial signal to another RFID tag through the test serial signal output pad 203.

Finally, the digital unit 200 outputs the address ADD, the input / output data I / O, the control signal CTR, and the clock CLK to the memory 300. The memory 300 writes data to the storage device and reads data stored in the storage device.

As the memory 300, a nonvolatile ferroelectric memory (FeRAM) may be used. FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

10 is an overall configuration diagram of an RFID tag according to a second embodiment of the present invention.

Referring to FIG. 10, the RFID tag according to the second embodiment of the present invention includes an antenna unit 10, an analog unit 100, a digital unit 200, and a memory 300.

The configuration of the antenna unit, the digital unit 200 and the memory 300 of the second embodiment is the same as that of the first embodiment, and the analog unit 100 of the second embodiment further includes a voltage limiter 180. The voltage limiter 180 has a voltage at a constant voltage level to prevent the voltage amplified by the voltage amplifier 110 or the power supply voltage supplied from the outside from being momentarily higher than the power supply voltage level VDD, thereby damaging the internal circuit of the RFID tag. Limit the magnitude of the voltage so that it does not rise.

11 is a block diagram showing a slot counter controller 210 according to the first and second embodiments of the present invention.

Referring to FIG. 11, the slot counter controller 210 of the present invention includes a slot counter 211 and a shift register 212.

The test clock TCLK is input to the slot counter 211 and the shift register 212 through the test clock input pad 201. The pad resistor Rpd is connected in parallel between the test clock input pad 201 and the ground terminal.

The pad resistor Rpd is input so that noise is not input to the slot counter 211 when the test clock TCLK is not input at the high level, that is, when noise is generated in the test clock TCLK and is input at a level between the low level and the high level. Bias the signal to low level. However, when the test clock TCLK is input at the high level, the input signal itself is capable of driving so that the input signal is not biased to the low level by the pad resistor Rpd.

The test serial input signal input from the test chip or the test serial output signal input from another RFID tag is input to the shift register 212 through the test serial signal input pad 202. The pad resistor Rpd is connected in parallel between the test serial signal input pad 202 and the ground terminal.

The pad resistance Rpd is the shift register when the test serial input (output) signal is not input at a high level, that is, when noise is generated in the test serial input (output) signal and is input at a level between a low level and a high level. The input signal is biased to a low level so as not to be input to 212. However, when the test serial input (output) signal is input at the high level, the signal input by the pad resistor Rpd is not biased to the low level because there is a driving capability of the input signal itself.

The slot counter 211 is set by the test clock TCLK to output the slot counter bits at a low level, and is reset by the test serial output signal output from the shift register 212 to output the slot counter bits at a high level. When the slot counter bit is output at the low level, the RFID tag is activated. When the output is at the high level, the RFID tag is deactivated.

The shift register 212 stores a value of a test serial input signal input from the test chip or a test serial output signal input from another RFID tag, and then, when the shift register 212 is activated by the test clock TCLK, the test serial input signal. Alternatively, the value of the test serial output signal input from another RFID tag is output as the test serial output signal. The test serial output signal is output to the slot counter 211 and the test serial signal output pad 203. The shift register 212 is reset by receiving the power-on reset signal POR from the power-on reset unit 140.

12 is a configuration diagram showing an input / output pad used for testing an RFID tag according to the first and second embodiments of the present invention.

Referring to FIG. 12, the input / output pad of the RFID tag according to the present invention includes a test signal input pad 13, a test signal output pad 14, a power voltage applying pad 15, a ground voltage applying pad 16, and a test. A clock input pad 201, a test serial signal input pad 202, and a test serial signal output pad 203 are included.

The test input signal TI is input through the test signal input pad 13, the test output signal TO is output through the test signal output pad 14, and the power supply voltage VDD is applied through the power supply voltage applying pad 15. The ground voltage GND is applied through the ground voltage applying pad 16, the test clock TCLK is input through the test clock input pad 201, and the test serial input (output) signal is input through the test serial signal input pad 202. The test serial output signal is output through the test serial signal output pad 203.

13 is a timing diagram showing an operation timing of the slot counter controller 210 included in the RFID tag TAG01 according to the first and second embodiments of the present invention.

Referring to FIG. 13, when ti starts to supply the supply voltage VDD through the supply voltage applying pad 15, the test chip is initialized. At the same time, the power-on reset signal POR is also initialized from low level to high level. Since the power on reset signal POR is also input to the shift register 212, the shift register 212 is also initialized by the power on reset signal POR.

At t0, the test serial input signal transitions from low level to high level. That is, the test serial input signal is input from the test chip to the test serial signal input pad TSI01 of the RFID tag TAG01. The test serial input signal input to the RFID tag TAG01 is input to the shift register 212 of the slot counter control unit 210.

Since the shift register 212 is activated when the test clock TCLK is at the low level, at t1, the shift register 212 is deactivated when the test clock TCLK transitions from the low level to the high level. Thus, the shift register 212 outputs the test serial output signal at a low level in an initialized state until activated.

At t1, since the test clock TCLK is input to the set terminal of the slot counter 211, when the test clock TCLK is input from the low level to the high level, the slot counter 211 is set so that the slot counter bit of " 111 ... " Outputs When the slot counter bit is output as "111 ...", the RFID tag is deactivated. Therefore, the test operation cannot be performed.

At t2, shift register 212 is activated when test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores the test serial input signal value at t2 and outputs it as a test serial output signal.

The shift register 212 stores the input signal when activated and continues to output until deactivated. Thus, even if the test serial output signal transitions to a low level at t3, the test serial output signal is output at a high level while the test clock TCLK remains at a low level and the shift register 212 remains active. The test serial input signal is preferably input at the low level before t4 at which the test clock TCLK transitions to the high level.

The test serial output signal is also input to the reset terminal of the slot counter 211. If the test serial output signal is at a high level, the slot counter 211 is reset to output a slot counter bit of "000 ...". The RFID tag is activated when the slot counter bit is output as "000 ...".

That is, the slot counter 211 maintains the reset state until the test clock TCLK is input at a high level and the shift register 212 is deactivated. Therefore, the slot counter bit is output as "000 ..." until t4 at which the test clock TCLK is input at the high level, so that the RFID tag can be activated and perform a test operation during this activation period.

The test operation may be performed on the analog unit 100, the digital unit 200, or the memory 300 according to the intention of the user of the RFID tag. For example, when performing a test operation on the memory 300, reset data is written to each memory cell of the memory 300. The test input signal TI is input through the input / output pads. The test input signal TI is input to the test input buffer 150 to generate a command signal CMD. The command signal CMD includes a signal operative to read data written to the RFID tag.

The digital unit 200 reads the data written to the memory 300 using the control signal CTR according to the command signal CMD. The response signal RP generated by the digital unit 200 includes information about the read data. The response signal RP is driven by the test output driver 170 and output through the test signal output pad 14 in the form of the test output signal TO. Obtaining information about the data read from the test output signal TO, test equipment (not shown) outside the RFID tag compares the read data with the written data or not. If the read data and the written data match, it is determined to be normal, and if not, the test operation is completed by determining as bad.

At t4, the shift register 212 is deactivated when the test clock TCLK transitions from low level to high level. The shift register 212 outputs a test serial output signal at a high level until the next test clock TCLK is input low and the shift register 212 is activated. When the test serial output signal is output at a high level, the slot counter 212 is reset to output a slot counter bit of "000 ...". When the slot counter bit is output as "000 ...", the RFID tag TAG01 is activated.

At t5, the shift register 212 of the RFID tag TAG01 is activated again when the test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores a test serial input signal value input to the RFID tag TAG01 at t5 and outputs the test serial input signal. Therefore, at t5, the test serial input signal is input at the low level, so the test serial output signal transitions from the high level to the low level. Since the test serial output signal is also input to the reset terminal of the slot counter 211, when the test serial output signal maintains a low level, the slot counter 211 remains set to clear the slot counter bit of "111 ...". Output If the slot counter bit is output as "111 ...", the RFID tag TAG01 remains inactive.

14 is a timing diagram illustrating an operation timing of sequentially activating a plurality of RFID tags according to the first and second embodiments of the present invention.

Referring to FIG. 14, when the power supply voltage VDD starts to be supplied at ti, the test chip is initialized. At the same time, the power-on reset signal POR is also initialized from low level to high level. Since the power on reset signal POR is also input to the shift register 212, the shift register 212 is also initialized by the power on reset signal POR.

At t0, the test serial input signal transitions from low level to high level. That is, the test serial input signal is input from the test chip to the test serial signal input pad TSI01 of the RFID tag TAG01. The test serial input signal input to the RFID tag TAG01 is input to the shift register 212 of the slot counter control unit 210.

Since the shift register 212 is activated when the test clock TCLK is at the low level, the shift register 212 is deactivated when the test clock TCLK transitions from the low level to the high level at t1. Accordingly, the shift register 212 of the RFID tag TAG01 outputs the test serial output signal at a low level in the initialized state until it is activated.

At t1, since the test clock TCLK is input to the set terminal of the slot counter 211, when the test clock TCLK is input from the low level to the high level, the slot counter 211 is set so that the slot counter bit of " 111 ... " Outputs When the slot counter bit is output as "111 ...", the RFID tag is deactivated. Therefore, the test operation cannot be performed.

At t2, shift register 212 is activated when test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores the test serial input signal value at t2 and outputs it as a test serial output signal.

At t2, the test serial input signal is input at high level, so the test serial output signal also transitions from low level to high level. The test serial output signal is also input to the reset terminal of the slot counter 211. If the test serial output signal is at a high level, the slot counter 211 is reset to output a slot counter bit of "000 ...". As a result, the RFID tag TAG01 is activated.

The shift register 212 stores the input signal when activated and continues to output until deactivated. Thus, even if the test serial output signal transitions to a low level at t3, the test serial output signal is output at a high level while the test clock TCLK remains at a low level and the shift register 212 remains active. The test serial input signal is preferably input at the low level before t4 at which the test clock TCLK transitions to the high level.

The test serial output signal is also input to the reset terminal of the slot counter 211. If the test serial output signal is at a high level, the slot counter 211 is reset to output a slot counter bit of "000 ...". The RFID tag is activated when the slot counter bit is output as "000 ...".

At t4, the shift register 212 is deactivated when the test clock TCLK transitions from low level to high level. The shift register 212 outputs a test serial output signal at a high level until the next test clock TCLK is input low and the shift register 212 is activated. When the test serial output signal is output at a high level, the slot counter 212 is reset to output a slot counter bit of "000 ...". When the slot counter bit is output as "000 ...", the RFID tag TAG01 is activated.

At t5, the shift register 212 of the RFID tag TAG01 is activated again when the test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores a test serial input signal value input to the RFID tag TAG01 at t5 and outputs the test serial input signal. Therefore, at t5, the test serial input signal is input at the low level, so the test serial output signal transitions from the high level to the low level. Since the test serial output signal is also input to the reset terminal of the slot counter 211, when the test serial output signal maintains a low level, the slot counter 211 remains set to clear the slot counter bit of "111 ...". Output If the slot counter bit is output as "111 ...", the RFID tag TAG01 is deactivated.

On the other hand, the test serial output signal of the RFID tag TAG01 is input to the test serial signal input pad TSI02 of the RFID tag TAG02.

At t5, the shift register 212 of the RFID tag TAG02 is activated when the test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores a test serial output signal value input to the RFID tag TAG02 at t5 and outputs the test serial output signal.

In real circuits, there is a slight delay between the transition of the test clock TCLK and the transition of the test serial output signal. In other words, at t5, the test clock TCLK transitions from the high level to the low level, and after a slight delay, the test serial output signal value input to the RFID tag TAG02 transitions from the high level to the low level. Therefore, since the test serial output signal value input to the RFID tag TAG02 at t5 is at the high level, the shift register 212 of the RFID tag TAG02 outputs the test serial output signal at the high level.

Since the test serial output signal is also input to the reset terminal of the slot counter 211, when the test serial output signal is at a high level, the slot counter 211 is reset to output a slot counter bit of "000 ...". When the slot counter bit is output as "000 ...", the RFID tag TAG02 is activated.

At t6, the shift register 212 is deactivated when the test clock TCLK transitions from low level to high level. The shift register 212 outputs a test serial output signal at a high level until the next test clock TCLK is input low and the shift register 212 is activated. When the test serial output signal is output at a high level, the slot counter 212 is reset to output a slot counter bit of "000 ...". Therefore, the RFID counter TAG02 remains active because the slot counter bit is output as "000 ...".

At t7, the shift register 212 of the RFID tag TAG02 is activated again when the test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores a test serial output signal value input to the RFID tag TAG02 at t7 and outputs the test serial output signal as a test serial output signal. Therefore, the test serial output signal is input at the low level at t7, so the test serial output signal transitions from the high level to the low level. Since the test serial output signal is also input to the reset terminal of the slot counter 211, when the test serial output signal maintains a low level, the slot counter 211 remains set to clear the slot counter bit of "111 ...". Output If the slot counter bit is output as "111 ...", the RFID tag TAG02 is deactivated.

Similarly, the test serial output signal of the RFID tag TAG02 is input to the test serial signal input pad TSI03 of the RFID tag TAG03.

At t7, the shift register 212 of the RFID tag TAG03 is activated when the test clock TCLK transitions from high level to low level. When the shift register 212 is activated, the shift register 212 stores the test serial output signal value input to the RFID tag TAG03 at t7 and outputs the test serial output signal.

In real circuits, there is a slight delay between the transition of the test clock TCLK and the transition of the test serial output signal. That is, at t7, the test clock TCLK transitions from the high level to the low level, and after a slight delay, the test serial output signal value input to the RFID tag TAG03 transitions from the high level to the low level. Therefore, since the test serial output signal value input to the RFID tag TAG02 at t7 is at the high level, the shift register 212 of the RFID tag TAG03 outputs the test serial output signal at the high level.

Since the test serial output signal is also input to the reset terminal of the slot counter 211, when the test serial output signal is at a high level, the slot counter 211 is reset to output a slot counter bit of "000 ...". When the slot counter bit is output as "000 ...", the RFID tag TAG03 is activated.

At t8, the shift register 212 is disabled when the test clock TCLK transitions from low level to high level. The shift register 212 outputs a test serial output signal at a high level until the next test clock TCLK is input low and the shift register 212 is activated. When the test serial output signal is output at a high level, the slot counter 212 is reset to output a slot counter bit of "000 ...". Therefore, the RFID counter TAG02 remains active because the slot counter bit is output as "000 ...".

As described above, the RFID tags TAG04 to TAGN may be sequentially activated for each RFID tag, and a test operation may be performed during the activation period. 15 is a flowchart illustrating a method of sequentially testing a plurality of RFID tags according to the first and second embodiments of the present invention.

Referring to FIG. 15, the test chip is initialized by supplying a power voltage to the test chip included in the RFID tag array (S101).

The plurality of RFID tags included in the RFID tag array are reset using the power on reset signal (S102).

When the test chip is initialized, the test chip generates a test serial input signal and outputs the test serial input signal to the RFID tag TAG01 (S103).

When the RFID tag TAG01 receives the test serial input signal, the RFID tag TAG01 is activated in synchronization with the test clock TCLK, and performs a test operation during the activation period until it is deactivated (S104).

The RFID tag TAG01 outputs the test serial output signal to the RFID tag TAG02 (S105).

The step of outputting the test serial signal to the next RFID tag and performing the test operation is repeated until the last RFID tag is activated to complete the test operation (S106).

16 is a circuit diagram showing a test input buffer 150 according to the first and second embodiments of the present invention.

Referring to FIG. 16, in the test input buffer 150 according to the present invention, a test input signal TI and a demodulation signal DEMOD are input to a logic element OR.

The pad resistor Rpd is connected in parallel between the input terminal of the logic element OR to which the test input signal TI is input and the ground terminal.

The pad resistor Rpd may not be input to the test input buffer 150 when the test input signal TI is not input at the high level, that is, when noise is generated in the test input signal and is input at a level between the low level and the high level. Bias the input signal to a low level. However, when the test input signal TI is input at the high level, the input signal is not driven to the low level by the pad resistor Rpd because of the driving capability of the input signal itself.

The logic terminal OR ORs the input test input signal TI and the demodulation signal DEMOD. That is, when one of the test input signal TI or the demodulation signal DEMOD is activated, the command signal CMD is activated and output to the digital block 200.

FIG. 17 is a timing diagram illustrating an operation of the test input buffer 150 in a state in which an RFID tag according to the first and second embodiments of the present invention is inactivated.

Referring to FIG. 17, a test operation cannot be performed since the test input signal TI is input at a low level. When the demodulation signal DEMOD is input, the command signal CMD is activated in synchronization with the demodulation signal DEMOD. That is, when the demodulation signal DEMOD is input at the high level, the command signal CMD is output at the high level, and when the demodulation signal DEMOD is input at the low level, the command signal CMD is output at the low level.

18 is a timing diagram illustrating an operation of the test input buffer 150 in a state in which an RFID tag according to the first and second embodiments of the present invention is activated.

Referring to FIG. 18, a power supply voltage VDD and a ground voltage GND are supplied to an RFID tag.

When the test operation is performed, the demodulation signal DEMOD is input at a low level because it is preferable not to receive the radio signal. The command signal CMD is output in synchronization with the test input signal TI. That is, when the test input signal TI is input at the high level, the command signal CMD is output at the high level, and when the test input signal TI is input at the low level, the command signal CMD is output at the low level.

19 is a circuit diagram illustrating a test output driver 170 according to the present invention.

Referring to FIG. 19, the test output driver 170 according to the present invention includes an NMOS transistor N having an open drain structure. The NMOS transistor N is gated with a response signal RP, a source is connected to the ground terminal, and a drain is connected to the test signal output pad 14.

Since the NMOS transistor N is turned on when the response signal RP is input at high level and the source and drain are conducted, the test output signal TO is driven at a low level, and when the response signal RP is input at the low level, the NMOS transistor N is turned off. Since the source and drain are shut off, the test output signal TO is driven to a high level.

20 is a timing diagram illustrating an operation of the test output driver 170 according to the first and second embodiments of the present invention.

Referring to FIG. 20, the test output driver 170 according to the present invention is supplied with a power supply voltage VDD and a ground voltage GND to an RFID tag.

When the response signal RP is input at the low level, the NMOS transistor N is turned off to output the test output signal TO at a high level. When the response signal RP is input at the high level, the NMOS transistor N is turned on to bring the test output signal TO to a low level. Will output That is, the test output driver 170 outputs the test output signal TO having the phase opposite to the response signal RP to the test signal output pad 14.

21 is an overall configuration diagram of an RFID tag according to a third embodiment of the present invention.

Referring to FIG. 21, an RFID tag according to a third embodiment of the present invention includes an antenna unit 10, an analog unit 100, a digital unit 200, a test circuit 300, and a memory 400. .

The antenna unit 10 serves to receive a radio signal transmitted from the RFID reader. The received radio signal is input to the analog unit 100 through the antenna pads 11 and 12.

The analog unit 100 includes a voltage amplifier 110, a demodulator 120, a clock generator 130, a power-on reset unit 140, a test input buffer 150, a modulator 160, and a test output driver. 170 and shift register 180.

The voltage amplifying unit 110 rectifies and boosts a radio signal applied from the antenna unit 10 to generate a power supply voltage which is a driving voltage of the RFID tag.

The demodulator 120 demodulates a radio signal input from the antenna unit 10 according to the output voltage of the voltage amplifier 110 to generate a demodulated signal DEMOD, and converts the generated demodulated signal DEMOD into the test input buffer 150. Output

The clock generator 130 supplies the clock CLK for controlling the operation of the digital unit 200 according to the power voltage generated by the voltage amplifier 110 to the digital unit 200.

The power on reset unit 140 detects a power supply voltage generated by the voltage amplifier 110 and outputs a power on reset signal POR for controlling the reset operation to the shift register 180 and the digital unit 200.

The power-on reset signal POR rises together with the power supply voltage while the power supply voltage transitions from the low level to the high level, and then transitions from the high level to the low level as soon as the power supply voltage is supplied to the power supply voltage level VDD to break the circuit inside the RFID tag. It means the signal to reset.

The test input buffer 150 detects an operation command signal from the test input signal TI input through the test signal input pad 13 and the demodulation signal DEMOD input from the demodulator 120 to generate a command signal CMD.

The modulator 160 modulates the response signal RP output from the digital unit 200 and transmits the modulated response signal RP to the RFID reader through the antenna unit 10.

The power supply voltage application pad 15 represents a pad to which a power supply voltage VDD is applied when testing a plurality of RFID tags on a wafer, and the ground voltage application pad 16 shows a ground voltage GND when testing a plurality of RFID tags on a wafer. Indicates the pad being applied.

That is, when the RFID tag communicates with the RFID reader to receive a radio signal, the voltage amplifier 110 supplies the power supply voltage VDD. However, when the RFID tag is tested on the wafer according to the present invention, a separate power supply voltage application pad is provided. The power supply voltage VDD and the ground voltage GND are supplied through the 15 and the ground voltage application pad 16.

The test output driver 170 drives the response signal RP input from the digital unit 200 to generate the test output signal TO.

The digital unit 200 receives a power supply voltage, a power-on reset signal POR, a clock CLK, and a command signal CMD from the analog unit 100 to interpret the command signal CMD and generate control signals and processing signals. The response signal RP corresponding to the control signal and the processing signal is output to the analog unit 100.

The test circuit 300 is activated by the test serial output signal generated by the shift register 180 being activated. When the test circuit 300 is activated, the address signal XADD, XBANK and the control signal XDD, XCE, XWE, XOE or the control signal XADD, DBANK and the control signal DI, DCE, DWE input from the outside are input. According to the DOE, the internal circuits included in the RFID tag, that is, the analog unit 100, the digital unit 200, and the memory 400 are tested.

The digital unit 200 generates the address signals DADD, DBANK and the control signals DI, DCE, DWE, DOE by the command signal CMD generated according to the test input signal TI input through the test signal input pad 13. The test circuit 300 generates the address signals ADD, BANK and the control signals I, CE, WE, and OE according to the address signals DADD, DBANK and the control signals DI, DCE, DWE, and DOE to test the memory 400. The test circuit 300 receives a control result signal O which is a test result from the memory 400 and generates a control result signal DO. The digital unit 200 generates a response signal RP according to the control result signal DO, and drives the response signal RP by the test signal output driver 170 to output the test signal through the test signal output pad 14.

The test circuit 300 includes the address signals ADD, XBANK and the control signals XDD, XCE, XWE, and XOE inputted through the address signal input pad 301 and the control signals XDD, XCE, XWE, and XOE inputted through the control signal input pads 302, 303, 304, and 305. And control signals I, CE, WE, and OE to test the memory 400. The test circuit 300 receives a control result signal O which is a test result from the memory 400 and generates a control result signal XDO. The test circuit 300 outputs the control result signal XDO, and drives the control result signal XDO through the control signal output pad 306.

The memory 400 includes a plurality of memory cells, each of which serves to write data to the storage device and to read data stored in the storage device.

The memory 400 may be a nonvolatile ferroelectric memory. FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

22 is an overall configuration diagram of an RFID tag according to a fourth embodiment of the present invention.

Referring to FIG. 22, an RFID tag according to a fourth embodiment of the present invention includes an antenna unit 10, an analog unit 100, a digital unit 200, a test circuit 300, and a memory 400. .

The configuration of the antenna unit, the digital unit 200, the test circuit 300 and the memory 400 of the fourth embodiment is the same as that of the third embodiment, and the analog unit 100 of the fourth embodiment has a voltage limiter 190. It further includes. The voltage limiter 190 prevents the voltage amplified by the voltage amplification unit 110 or the power supply voltage supplied from the outside from being temporarily higher than the power supply voltage level VDD to damage the internal circuit of the RFID tag. Limit the magnitude of the voltage so that it does not rise.

23 is a block diagram showing a shift register 180 according to the third and fourth embodiments of the present invention.

Referring to FIG. 23, the shift register 180 of the present invention includes a shift register circuit 185, an antistatic unit 186, and an input buffer 187.

The shift register circuit 185 stores a value of a test serial input signal input from a test chip or a test serial output signal input from another RFID tag, and then when the shift register circuit 185 is activated by the test clock TCLK, the test serial input Outputs the value of the test serial output signal input from the signal or another RFID tag as a test serial output signal.

The shift register circuit 185 is reset by the power on reset signal POR input from the power on reset unit 140 or the test reset signal TRST input through the test reset signal input pad 184 from the outside. When the shift register circuit 185 is reset, the test serial output signal is output at a low level regardless of the input signal.

The test clock TCLK is input to the shift register 180 through the test clock input pad 181. An antistatic unit 186 is connected in parallel between the test clock input pad 181 and the ground terminal.

The antistatic part 186 includes an NMOS transistor ND. The NMOS transistor ND has a gate and a source connected to the ground terminal and a drain connected to the test clock input pad 181. The NMOS transistor ND remains turned off because its gate is connected to the ground terminal. However, when static electricity is generated in the test clock input pad 181 and a high voltage is momentarily applied, the NMOS transistor ND is turned on so that current flows through the ground terminal. Therefore, high current can be prevented from flowing to the shift register circuit 185.

The input buffer 187 receives the power-on reset signal POR and the test reset signal TRST and outputs a reset signal to the reset terminal of the shift register circuit 185. The input buffer 187 may be implemented with a OR logic element.

When the power-on reset signal POR is input at a high level, that is, when the power-on reset signal is input at a high level when a power supply voltage is supplied to the RFID tag, the logic element OR outputs a reset signal at a high level so that the shift register circuit is output. Reset (185). Accordingly, the shift register circuit 185 outputs the test serial output signal at a low level regardless of the input signal.

If the test reset signal TRST is input to the high level from the outside to reset the shift register circuit 185 after the power supply voltage is supplied, the logic element OR outputs the reset signal to the high level to reset the shift register circuit 185. do. Accordingly, the shift register circuit 185 outputs the test serial output signal at a low level regardless of the input signal.

24 is a configuration diagram showing the configuration of the input / output pad 500 of the RFID tag according to the third and fourth embodiments of the present invention.

Referring to FIG. 24, the input / output pad 500 according to the present invention includes an input / output circuit unit 510 at a central portion, and a test signal input pad 13 and a test signal output pad 14 at a central peripheral area. , Power supply voltage applying pad 15, ground voltage applying pad 16, test clock input pad 181, test serial signal input pad 182, test serial signal output pad 183, test reset signal input pad 184 ), An address signal input pad 301, control signal input pads 302, 303, 304, and 305 and a control signal output pad 306 are arranged. An antistatic portion 520 is formed between the central portion and the peripheral region so that the input / output circuit portion 510 in the central portion is not damaged by the static electricity generated from the input pad.

FIG. 25 is a timing chart showing an operation timing of the shift register 180 included in the RFID tag TAG01 according to the third and fourth embodiments of the present invention.

Referring to FIG. 25, the test chip is initialized when the power voltage VDD starts to be supplied through the power voltage applying pad 15 at ti. At the same time, the power-on reset signal POR is also initialized from low level to high level. The power on reset signal POR is input to the shift register circuit 185 to reset the shift register circuit 185.

At ti, the shift register circuit 185 is reset even when the test reset signal TRST is input at the high level.

At t0, the test serial input signal transitions from low level to high level. That is, the test serial input signal is input from the test chip to the test serial signal input pad TSI01 of the RFID tag TAG01. The test serial input signal input to the RFID tag TAG01 is input to the shift register circuit 185 of the shift register 180.

At t1, when test clock TCLK is input at a high level, shift register circuit 185 stores the test serial input signal value at t1 and outputs it as a test serial output signal. Since the test serial input signal at t1 is input at a high level, the test serial output signal is output at a high level.

Since the shift register circuit 185 is set by the test clock TCLK, the test serial output signal is continuously output at a high level until the test clock TCLK is input at a high level at t1 and again at a high level at t4. . Thus, even if the test clock TCLK transitions to low level at t2 or at test t3, the test serial output signal is output at high level even if the test serial input signal transitions to low level.

In order to deactivate the RFID tag TAG01, the test serial input signal is preferably set to the low level before the next test clock TCLK is output to the high level. That is, in the present invention, the test serial input signal starts to be input at the low level at t3, but in order to achieve the object of the present invention, the test serial input signal may be input at the low level in the interval between t1 and t4.

When the test serial output signal is output at the high level, the test circuit 300 is activated, so that the test operation may be performed while the test serial output signal is output at the high level.

At t4, when the test clock TCLK is input at the high level, the shift register circuit 185 stores the test serial input signal value at t4 and outputs it as a test serial output signal. Since the test serial input signal is input at the low level at t4, the test serial output signal is output at the low level.

When the test serial output signal is output at a low level, the test circuit 300 is inactivated, and thus a test operation cannot be performed.

26 is a timing diagram illustrating an operation timing of sequentially activating a plurality of RFID tags according to the third and fourth embodiments of the present invention.

Referring to FIG. 26, the test chip is initialized when the power voltage VDD starts to be supplied at ti. At the same time, the power-on reset signal POR is also initialized from low level to high level. Since the power on reset signal PRO is also input to the shift register circuit 185, the shift register circuit 185 is also initialized by the power on reset signal POR.

At ti, the shift register circuit 185 is reset even when the test reset signal TRST is input at the high level.

At t0, the test serial input signal transitions from low level to high level. That is, the test serial input signal is input from the test chip to the test serial signal input pad TSI01 of the RFID tag TAG01. The test serial input signal input to the RFID tag TAG01 is input to the shift register circuit 185 of the shift register 180.

At t1, when test clock TCLK is input at high level, shift register circuit 185 stores the test serial input signal value at t1 and outputs it as a test serial output signal. Since the test serial input signal at t1 is input at a high level, the test serial output signal is output at a high level.

Since the shift register circuit 185 is set by the test clock TCLK, the test serial output signal is continuously output at a high level until the test clock TCLK is input at a high level at t1 and again at a high level at t4. . Thus, even if the test clock TCLK transitions to low level at t2 or at test t3, the test serial output signal is output at high level even if the test serial input signal transitions to low level.

In order to deactivate the RFID tag TAG01, the test serial input signal is preferably set to the low level before the next test clock TCLK is output to the high level. That is, in the present invention, the test serial input signal starts to be input at the low level at t3, but in order to achieve the object of the present invention, the test serial input signal may be input at the low level in the interval between t1 and t4.

When the test serial output signal of the RFID tag TAG01 is output at the high level, the test circuit 300 is activated, so that the test operation may be performed while the test serial output signal is output at the high level.

At t4, when the test clock TCLK is input at the high level, the shift register circuit 185 of the RFID tag TAG01 stores the test serial input signal value at t4 and outputs it as a test serial output signal. Since the test serial input signal is input at the low level at t4, the test serial output signal is output at the low level. When the test serial output signal of the RFID tag TAG01 is output at a low level, the test circuit 300 is inactivated, and thus the RFID tag TAG01 is inactivated.

The test serial output signal of the RFID tag TAG01 is input to the test serial signal input pad TSI02 of the RFID tag TAG02.

At t4, when the test clock TCLK is input to the RFID tag TAG02 at a high level, the shift register circuit of the RFID tag TAG02 stores the test serial output signal value input at t4 and then tests it with the test serial signal output pad TSO02 of the RFID tag TAG02. Output via serial output signal.

At t4, when the test clock TCLK is input at the high level, the test serial output signal of the RFID tag TAG01 is output from the high level to the low level. In a real circuit, there will be a slight delay between the instant the test clock TCLK transitions and the test serial output signal transitions. Since the test serial output signal value input to the RFID tag TAG02 at t4 is high level, the shift register circuit of the RFID tag TAG02 stores the high level value and outputs the high level test output signal through the output pad TSO02 of the RFID tag TAG02. do.

When the test serial output signal output from the shift register of the RFID tag TAG02 is output at the high level, the test circuit of the RFID tag TAG02 is activated, so that the test operation may be performed while the test serial output signal is output at the high level.

Since the shift register circuit of the RFID tag TAG02 is set by the test clock TCLK, the test serial output signal continues to the high level until the test clock TCLK is input at high level at t4 and again at the high level at t6. Output Thus, even when the test clock TCLK transitions to a low level at t5, the test serial output signal output from the shift register of the RFID tag TAG02 remains at a high level until t6.

At t6, when the test clock TCLK is input at the high level, the shift register circuit of the RFID tag TAG02 stores the test serial output signal value input to the RFID tag TAG02 at t6 and outputs it as a test serial output signal. Since the test serial input signal is input at the low level at t6, the test serial output signal is output at the low level.

When the test serial output signal is output at a low level from the shift register circuit of the RFID tag TAG02, the test circuit 300 is inactivated, so that the RFID tag TAG02 is inactivated.

The test serial output signal of the RFID tag TAG02 is also input to the test serial signal input pad TSI02 of the RFID tag TAG03.

At t6, when the test clock TCLK is input to the RFID tag TAG03 at a high level, the shift register circuit of the RFID tag TAG03 stores the test serial output signal value input at t6 and then tests it with the test serial signal output pad TSO03 of the RFID tag TAG03. Output via serial output signal.

At t6, when the test clock TCLK is input at the high level, the test serial output signal of the RFID tag TAG02 is output from the high level to the low level. In a real circuit, there will be a slight delay between the instant the test clock TCLK transitions and the test serial output signal transitions. Since the test serial output signal value input to the RFID tag TAG03 at t6 is high level, the shift register circuit of the RFID tag TAG03 stores the high level value and outputs a high level test output signal through the output pad TSO03 of the RFID tag TAG03. do.

When the test serial output signal output from the shift register of the RFID tag TAG03 is output at the high level, the test circuit of the RFID tag TAG03 is activated, so that the test operation may be performed while the test serial output signal is output at the high level.

The shift register circuit of the RFID tag TAG03 is set by the test clock TCLK, so the test serial output signal continues to be at a high level until the test clock TCLK is input at high level at t6 and again at high level at t8. do. Thus, even when the test clock TCLK transitions to a low level at t7, the test serial output signal output from the shift register of the RFID tag TAG03 remains at a high level until t8.

At t8, when the test clock TCLK is input at the high level, the shift register circuit of the RFID tag TAG03 stores the test serial output signal value input to the RFID tag TAG03 at t8 and outputs it as a test serial output signal. Since the test serial input signal is input at the low level at t8, the test serial output signal is output at the low level.

When the test serial output signal is output at a low level from the shift register circuit of the RFID tag TAG03, the test circuit 300 is inactivated, and thus the RFID tag TAG03 is inactivated.

Similarly, the test serial output signal of the RFID tag TAG03 is input to the test serial signal input pad TSI04 of the RFID tag TAG04. As described above, the RFID tags TAG04 to TAGN may be sequentially activated, and a test operation may be performed during the activation period.

The test operation during the activation interval is performed as follows.

The test operation may be performed on the analog unit 100, the digital unit 200, or the memory 400 according to the intention of the user of the RFID tag. For example, when performing a test operation on the memory 400, reset data is written to the memory 400. The test input signal TI is input through the input / output pads. The test input signal TI is input to the test input buffer 150 to generate a command signal CMD. The command signal CMD includes a signal operative to read data written to the RFID tag.

The test circuit 300 reads the data written to the memory 400 using the control signal CTR according to the command signal CMD. The response signal RP generated by the test circuit 300 includes information about the read data. The response signal RP is driven by the test output driver 170 and output through the test signal output pad 14 in the form of the test output signal TO. Obtaining information about the data read from the test output signal TO, test equipment (not shown) outside the RFID tag compares the read data with the written data or not. If the read data and the written data match, it is determined to be normal, and if not, the test operation is completed by determining as bad.

FIG. 27 is a flowchart illustrating a method of sequentially testing a plurality of RFID tags included in an RFID tag array according to third and fourth embodiments of the present invention.

Referring to FIG. 27, the test chip is initialized by supplying a power voltage to the test chip included in the RFID tag array (S101).

The plurality of RFID tags included in the RFID tag array are reset using the power on reset signal (S102).

When the test chip is initialized, the test chip generates a test serial input signal and outputs the test serial input signal to the RFID tag TAG01 (S103).

When the RFID tag TAG01 receives the test serial input signal, the RFID tag TAG01 is activated in synchronization with the test clock TCLK, and performs a test operation during the activation period until it is deactivated (S104).

The RFID tag TAG01 outputs the test serial output signal to the RFID tag TAG02 (S105).

The step of outputting the test serial signal to the next RFID tag and performing the test operation is repeated until the last RFID tag is activated to complete the test operation (S106).

28 is a flowchart illustrating a first embodiment in which each of the plurality of RFID tags included in the RFID tag array according to the present invention is tested.

Referring to FIG. 28, the detailed test operation of step S104 in the state where the RFID tag is activated may be performed as follows.

When the RFID tag is activated, the test input signal TI is input through the test signal input pad 13 of the RFID tag (S104-1).

The test circuit 300 performs a test operation by the test input signal TI, and outputs the test result signal TXO to the test output driver 170 (S104-2).

The test output driver 170 generates a test output signal TO by driving the test result signal TXO and outputs the test output signal TO to the outside through the test signal output pad 14 (S104-3).

The external test apparatus compares the test input signal TI and the test output signal TO to check whether the RFID tag operates normally (S104-4).

29 is a flowchart illustrating a second embodiment of testing each of a plurality of RFID tags included in an RFID tag array according to the present invention.

Referring to FIG. 29, a detailed test operation of step S104 in the state where the RFID tag is activated may be performed as follows.

When the RFID tag is activated, the address signals XADD, XBANK and the control signals XDD, XCE, XWE, and XOE are input through the address signal input pad 301 and the control signal input pads 302, 303, 304 and 305 of the RFID tag (S104-1).

The test circuit 300 performs a test operation according to the address signals XADD, XBANK and the control signals XDD, XCE, XWE, and XOE, and outputs the control result signal XDO to the control signal output driver 171 (S104-2).

The control signal output driver 171 drives the control result signal XDO to generate the control output signal XO and then outputs the result to the outside through the control signal output pad 306 (S104-3).

The external test apparatus compares the address signals XADD, XBANK and the control signals XDD, XCE, XWE, XOE with the control output signal XO to check whether the RFID tag is normally operated (S104-4).

30 is a circuit diagram showing a test input buffer 150 according to the third and fourth embodiments of the present invention.

Referring to FIG. 30, in the test input buffer 150 of the present invention, a demodulation signal DEMOD is input from the demodulator 120, a test input signal TI is input from the outside, and a test serial output signal is output from the shift register 180. Is entered.

The test input signal TI and the test output signal are input to the logic element AND. The logic element AND performs an AND operation on the test input signal TI and the test output signal.

The logic element OR receives a signal input from the demodulation signal DEMOD and the logic element AND and performs an OR operation to generate a command signal CMD. The command signal CMD is output to the digital unit 200.

FIG. 31 is a timing diagram illustrating an operation of the test input buffer 150 in a state where an RFID tag is inactivated according to the third and fourth embodiments of the present invention.

Referring to FIG. 31, the RFID tag is inactive and thus cannot perform a test operation. Since the test operation cannot be performed, the test input signal TI is also input at the low level.

When the test input signal TI is input at the low level, the logic element AND performs an AND operation to output a low level signal.

The logic element OR performs an OR operation and generates a command signal CMD according to the demodulation signal DEMOD since the signal input from the logic element AND is at a low level. That is, when the demodulation signal DEMOD is input at a high level, the command signal CMD is output at a high level, and when the demodulation signal DEMOD is input at a low level, the command signal CMD is output at a low level.

32 is a timing diagram illustrating an operation of the test input buffer 150 in the state where the RFID tag according to the third and fourth embodiments of the present invention is activated.

Referring to FIG. 32, since an RFID tag is activated, a test may be performed by a test input signal. Since the RFID tag is activated, the power supply voltage is supplied to the power supply voltage level VDD, and the ground voltage is supplied to the ground voltage level GND.

When the test input signal TI is input at the low level, the logic element AND performs an AND operation to output a low level signal.

Since the RFID tag is activated, the test output signal is input to the logic element AND at a high level, and the logic element AND performs an AND operation, so that a signal synchronized with the test input signal TI is output from the logic element AND.

During the test operation, the demodulation signal DEMOD is input at a low level, and the logic element OR generates a command signal CMD by performing a round operation on the demodulation signal DEMOD and an output signal of the logic element AND. That is, when the test input signal TI is input at a high level, the command signal CMD is output at a high level, and when the test input signal TI is input at a low level, the command signal CMD is output at a low level.

33 is a circuit diagram illustrating the input / output circuit unit 510 according to the third and fourth embodiments of the present invention.

Referring to FIG. 33, the input / output circuit unit 510 includes a test output driver 170, a control output driver 171, an address signal input / output unit 172, and a control signal input / output unit 173, 174, 175. .

The test output driver 170 includes a pull-up driver PU_T and a driver DRV_T. The pull-up driving unit PU_T is connected to the ground terminal to pull up the response signal RP input from the digital unit 200. The driver DRV_T generates the test output signal TO by driving the response signal RP input from the digital unit 200 and outputs the test output signal TO to the outside through the test signal output pad 14.

The control output driver 171 includes a pull-up driver PU_X and a driver DRV_X. The pull-up driver PU_X selectively pulls-up the control result signal XDO according to the control signal XOE input through the control signal input pad 305. The driver DRV_X drives the control result signal XDO output from the control signal input / output unit 174 to generate the control output signal XO and then outputs the result to the outside through the control signal output pad 306.

In the address signal input / output unit 172, a plurality of logic elements OR are connected in parallel, and each logic element OR receives an address signal XADD from the outside, an address signal DADD from the digital unit 200, and a shift register 180. In response to the test serial output signal, the address signal ADD is generated and the address signal ADD is output to the memory 400.

The control signal input / output unit 173 has a plurality of logic elements OR connected in parallel, and each logic element OR connects the control signal XDI from the outside, the control signal DI from the digital unit 200, and the shift register 180. The test serial output signal is received from the control signal I, and the control signal I is output to the memory 400.

The control signal input / output unit 174 has a plurality of logic elements XOR connected in parallel, and each logic element XOR receives a control signal O from the memory 400 and a test serial output signal from the shift register 180. The control result signal XDO is generated, and the control result signal XDO is output to the control output driver 171.

The control signal input / output unit 175 has a plurality of logic elements OR connected in parallel, and receives a control signal DCE, DWE, DOE from the digital unit 200, and a control signal XCE, XWE, XOE from the outside. The CE, WE, OE are generated and the control signals CE, WE, OE are output to the memory 400.

34 is a circuit diagram illustrating the test output driver 170 according to the third and fourth embodiments of the present invention.

Referring to FIG. 34, the test output driver 170 according to the present invention includes a pull-up driver PU_T and a driver DRV_T.

The pull-up driver PU_T consists of a PMOS transistor. The PMOS transistor is applied with a ground voltage GND through a gate low ground voltage applying pad 16, a power supply voltage VDD is supplied through a power supply voltage applying pad 15 as a drain, and a source is connected to an input terminal of the driver DRV_T. Since the ground voltage is applied to the gate of the PMOS transistor, the PMOS transistor remains turned on. Accordingly, the pull-up driver PU_T pulls up the response signal RP input to the driver DRV_T.

Since the pull-up driver PU_T is always activated, the driver DRV_T generates a test output signal TO by driving the response signal RP input from the digital unit 200 and outputs the test output signal TO through the test signal output pad 14.

35 is a timing diagram illustrating an operation of the test output driver 170 according to the third and fourth embodiments of the present invention.

Referring to FIG. 35, the test output driver 170 according to the present invention is supplied with the pull-up voltage of the power supply voltage level VDD to the input terminal of the driver DRV_T by the pull-up driver PU_T. Therefore, using the pull-up voltage, the driver DRV_T drives the response signal RP input from the digital unit 200 as the test output signal TO.

The driver DRV_T drives the test output signal TO to a low level when the response signal RP input from the digital unit 200 is input at a low level, and drives the test output signal TO to a high level when the response signal RP is input to a high level. .

36 is a circuit diagram showing the control output driver 171 according to the third and fourth embodiments of the present invention.

Referring to FIG. 36, the control output driver 171 according to the present invention includes a pull-up driver PU_X and a driver DRV_X.

The pull-up driver PU_X is composed of a PMOS transistor. The PMOS transistor is inputted with a control signal XOE through a control signal input pad 305 to a gate, a power supply voltage VDD is supplied to a drain, and a source is connected to an input terminal of the driver DRV_X.

When the control signal XOE is input at the high level, the PMOS transistor is turned off and the supply of the power supply voltage VDD is cut off, so the pull-up driver PU_X does not pull-up the control result signal XDO input to the driver DRV_X.

When the control signal XOE is input at the low level, since the PMOS transistor is turned on, the power supply voltage VDD is supplied to the input terminal of the driver DRV_X to pull up the control result signal XDO. Therefore, even when the control result signal XDO is input at the low level, when the control signal XOE is input at the low level, the control result signal XDO is pulled up and reset to the high level.

The driver DRV_X drives the control result signal XDO input from the digital unit 200 to generate the control output signal XO, and outputs the control output signal XO to the outside through the control signal output pad 306.

When the control signal XOE is input at the low level, the pull-up driver PU_X is activated and the control result signal XDO is reset to the high level. Therefore, the driver DRV_X drives the control result signal XDO. When the control signal XOE is input at the high level, the pull-up driver PU_X is deactivated. Therefore, the driver DRV_X does not pull up the control result signal XDO.

37 is a timing diagram showing the operation of the control output driver 171 according to the third and fourth embodiments of the present invention.

Referring to FIG. 37, in the control output driver 171, the control signal XOE is input at a low level in the period t1 to activate the pull-up driver PU_X. When the pull-up driver PU_X is activated, the power supply voltage VDD is supplied to an input terminal of the driver DRV_X. Therefore, the control result signal XDO input to the driver DRV_X is pulled up and reset to the high level.

When the control signal XOE transitions from the low level to the high level in the t2 section, the pull-up driver PU_X is inactivated. When the pull-up driver PU_X is deactivated, the power supply voltage VDD is not supplied to the input terminal of the driver DRV_X. Therefore, the control result signal XDO input to the driver DRV_X is driven at the level input from the digital unit 200. That is, when the control result signal XDO is input at the low level, the driver DRV_X drives the control output signal XO at the low level. When the control result signal XDO is input at the high level, the driver DRV_X drives the control output signal XO at the high level.

When the control signal XOE transitions from the high level to the low level again in the period t3, the pull-up driving unit PU_X is activated to pull up the control result signal XDO to the high level. Therefore, the driver DRV_X drives the control result signal XDO to a high level.

38 is a circuit diagram showing an address signal input / output unit 172 according to the third and fourth embodiments of the present invention.

Referring to FIG. 38, in the address signal input / output unit 172, a plurality of logic elements OR are connected in parallel, and each logic element OR receives an address signal XADD from the outside and an address signal DADD from the digital unit 200. The test serial output signal is input from the shift register 180 to generate an address signal ADD, and outputs the address signal ADD to the memory 400.

The address signal XADD input from the outside is a signal used to test the RFID tag by the control signals XCE, XWE, and XOE, and the address signal DADD input from the digital unit 200 tests the RFID tag by the test input signal TI. Is the signal used to

The address signal input / output unit 172 receives the address signals XADD and DADD, generates an address signal ADD according to how to perform the test, and outputs the address signal ADD to the memory 400. The address signal ADD is information on the location of the memory cell included in the memory 400 and may selectively perform a test operation on all memory cells or a specific memory cell included in the memory 400.

In the address signal input unit 172, a plurality of logic elements OR are connected in parallel, and each logic element OR performs an operation by performing an AND operation on an address signal XADD and a test output signal and an address signal DADD.

The logic element OR outputs the address signal ADD only when a test operation is performed and the test output signal is output at a high level. When the test output signal is output at the high level and the address signal DADD or the address signal XADD is input at the high level, the address signal ADD is output at the high level. When both the address signal XADD and the address signal DADD are input at the low level, the address signal ADD is output at the low level.

That is, when the test is performed by the test input signal TI, the address signal ADD is generated according to the address signal XADD. When the test is performed by the control signals XCE, XWE, and XOE, the address signal ADD is generated by the address signal DADD. do.

39 is a circuit diagram showing a control signal input / output unit 173 according to the third and fourth embodiments of the present invention.

Referring to FIG. 39, in the control signal input / output unit 173, a plurality of logic elements OR are connected in parallel, and each logic element OR receives a control signal XDI from the outside and a control signal DI from the digital unit 200. The test serial output signal is received from the shift register 180 to generate a control signal I, and output the control signal I to the memory 400.

The control signal XDI input from the outside is a signal used to test the RFID tag together with the control signals XCE, XWE, and XOE, and the control signal DI input from the digital unit 200 tests the RFID tag by the test input signal TI. Is the signal used to

In the control signal input / output unit 173, a plurality of logic elements OR are connected in parallel, and each logic element OR performs calculation by ANDing the control signal XDI and the test output signal and the control signal DI. In the present embodiment, two control signals XDI <0> and XDI <1> are branched and input to four logic elements OR. However, the number of control signals XDI can be changed as desired by the user.

The logic element OR outputs the control signal I only when a test operation is performed to output the test output signal at a high level. When the test output signal is output at the high level and the control signal XDI or the control signal DI is input at the high level, the control signal I is output at the high level. When both the control signal XDI and the control signal DI are input at the low level, the control signal I is output at the low level.

Table 1 shows the input / output relationship of the control signal input / output unit 173 according to the third and fourth embodiments of the present invention.
TABLE 1
External test input Of the internal digital unit 200
Default output Of the effective memory unit 400
input Output detection of the memory unit 400 External test output XDI
<0> XDI
<1> DI
<0> DI
<1> DI
<2> DI
<3> DI
<4> DI
<5> DI <6> DI
<7> I
<0> I
<1> I
<2> I
<3> I
<4> I
<5> I
<6> I
<7> XOR
OUT XDO 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 One 0 One 0 0 0 0 0 0 0 0 0 One 0 One 0 One 0 One 0 One One 0 0 0 0 0 0 0 0 0 One 0 One 0 One 0 One 0 0 One One One 0 0 0 0 0 0 0 0 One One One One One One One One 0 One
Referring to [Table 1], the test circuit 300 tests the memory 400 by the control signal I according to the control signals XDI <0> and XDI <1>, and shows the result of the control result signal XDO.

delete

For example, when the control signal XDI <0> is input at the low level, the control signal XDI <1> is input at the high level, and the control signals DI <0> to <7> are input at the low level, the control signal I <1>, I <3> I <5> I <7> are output at a high level to test the corresponding memory cells. The control result signal XDO, which is a test result, is output at a high level.

As another example, when both the control signal XDI <0> and the control signal XDI <1> are input at the high level, and the control signals DI <0> to <7> are input at the low level, the control signals I <0> to < 7> are all output at a high level to test all memory cells. The control result signal XDO, which is a test result, is output at a high level.

40 is a circuit diagram illustrating a control signal input / output unit 174 according to the third and fourth embodiments of the present invention.

Referring to FIG. 40, the control signal input / output unit 174 has a plurality of logic elements XOR connected in parallel, and each logic element XOR tests the control signal O from the memory 400 from the shift register 180. The control output signal XDO is generated by receiving the serial output signal and outputs the control result signal XDO to the control output driver 171.

The control result signal O is a signal indicating a result of performing a test on the memory 400. The control signal input / output unit 174 XORs the control result signals O <0> to <7> output from the memory 400. Control result signals O <0>, O <1>, control result signals O <2>, O <3>, control result signals O <4>, O <5>, control result signals O <6>, O < 7> are each XOA, the four output signals are XO2 again, and the two output signals are XOOUT last to generate the control result signal XOROUT.

The output terminal of the control signal input / output section 174 includes two NMOS transistors connected in series. The NMOS transistor ND1 is gated with the control result signal XOROUT, the drain with the control result signal XDO, and the source is connected to the source of the NMOS transistor ND2. The NMOS transistor ND2 has its gate connected to the test output signal, its drain is connected to the source of the NMOS transistor ND1, and the source is connected to the ground terminal.

The control signal input / output unit 174 is driven to the ground level when the NMOS transistors ND1 and ND2 are both turned on when the control result signal XOROUT and the test output signal are both at the same time.

41 is a circuit diagram showing a control result signal output unit 175 according to the third and fourth embodiments of the present invention.

Referring to FIG. 41, the control signal input / output unit 175 includes a plurality of logic elements OR connected in parallel, the control signals DCE, DWE, DOE from the digital unit 200, the control signals XCE, XWE, The control signal CE, WE, OE is generated by receiving the XOE, and the control signals CE, WE, OE are output to the memory 400.

The control signal XDI input from the outside is a signal used to test the RFID tag together with the control signals XCE, XWE, and XOE, and the control signal DI input from the digital unit 200 tests the RFID tag by the test input signal TI. Is the signal used to

In the control signal input / output unit 173, a plurality of logic elements OR are connected in parallel. The logic element OR1 performs an operation on the AND signal of the control signal XCE, the test output signal, and the control signal DCE, and outputs the control signal CE. The logic element OR2 performs an operation on the AND signal of the control signal XWE, the test output signal, and the control signal DWE, and outputs the control signal WE. The logic element OR3 outputs the control signal OE by performing calculation on the AND signal of the control signal XOE, the test output signal, and the control signal DOE.

42 is a circuit diagram illustrating the antistatic part 520 according to the third and fourth embodiments of the present invention.

Referring to FIG. 42, the test serial signal input pad 182 receives a test serial input signal or a test serial output signal from an external source and transfers the test serial signal to the shift register 180. The antistatic unit 520 is connected in parallel between the test serial signal input pad 182 and the ground terminal.

The antistatic part 520 includes an NMOS transistor ND. The NMOS transistor ND has a gate and a source connected to the ground terminal and a drain connected to the test serial signal input pad 182. The NMOS transistor ND remains turned off because its gate is connected to the ground terminal. However, when static electricity is generated in the test serial signal input pad 182 and a high voltage is momentarily applied, the NMOS transistor ND is turned on so that current flows through the ground terminal. Therefore, high current can be prevented from flowing to the shift register 180 inside the RFID tag.

1 is an overall configuration diagram of an RFID tag according to the prior art.

2 is a block diagram illustrating a wafer including a plurality of RFID tag arrays according to the present invention.

3 is a block diagram showing the configuration of one RFID tag array according to the present invention.

4 is a block diagram illustrating a process of sequentially activating a plurality of RFID tags in the RFID tag array according to the present invention.

5 is a circuit diagram illustrating an RFID tag array according to the present invention.

6 is a circuit diagram illustrating a process of sequentially activating a plurality of RFID tags included in an RFID tag array according to the present invention and testing them during an activation period.

7 is a circuit diagram illustrating a process of sequentially activating a plurality of RFID tags included in an RFID tag array according to the present invention and testing them during an activation period.

8 is a circuit diagram illustrating a configuration in which each RFID tag is connected through a scribe line in the RFID tag array according to the present invention.

9 is an overall configuration diagram of an RFID tag according to a first embodiment of the present invention.

10 is an overall configuration diagram of an RFID tag according to a second embodiment of the present invention.

11 is a block diagram illustrating a slot counter controller according to the first and second embodiments of the present invention.

12 is a configuration diagram showing an input / output pad used for testing an RFID tag according to the first and second embodiments of the present invention.

13 is a timing diagram showing an operation timing of a slot counter control unit according to the first and second embodiments of the present invention.

14 is a timing diagram illustrating an operation timing of sequentially activating a plurality of RFID tags according to the first and second embodiments of the present invention.

15 is a flowchart illustrating a method of sequentially testing a plurality of RFID tags according to the first and second embodiments of the present invention.

16 is a circuit diagram illustrating a test input buffer according to the first and second embodiments of the present invention.

17 is a timing diagram illustrating an operation of a test input buffer in a state in which an RFID tag is inactivated according to the first and second embodiments of the present invention.

18 is a timing diagram illustrating an operation of a test input buffer in a state in which an RFID tag is activated according to the first and second embodiments of the present invention.

19 is a circuit diagram illustrating a test output driver according to the present invention.

20 is a timing diagram illustrating the operation of the test output driver according to the first and second embodiments of the present invention.

21 is an overall configuration diagram of an RFID tag according to a third embodiment of the present invention.

22 is an overall configuration diagram of an RFID tag according to a fourth embodiment of the present invention.

23 is a block diagram showing a shift register according to the third and fourth embodiments of the present invention.

24 is a configuration diagram showing the configuration of an input / output pad of an RFID tag according to the third and fourth embodiments of the present invention.

Fig. 25 is a timing chart showing operation timings of the shift registers according to the third and fourth embodiments of the present invention.

26 is a timing diagram illustrating an operation timing of sequentially activating a plurality of RFID tags according to the third and fourth embodiments of the present invention.

FIG. 27 is a flowchart illustrating a method of sequentially testing a plurality of RFID tags included in an RFID tag array according to third and fourth embodiments of the present invention.

28 is a flowchart illustrating a first embodiment of testing each of a plurality of RFID tags included in an RFID tag array according to the present invention.

29 is a flowchart illustrating a second embodiment of testing each of a plurality of RFID tags included in an RFID tag array according to the present invention.

30 is a circuit diagram illustrating a test input buffer according to the third and fourth embodiments of the present invention.

FIG. 31 is a timing diagram illustrating an operation of a test input buffer in a state in which an RFID tag is inactivated according to the third and fourth embodiments of the present invention.

32 is a timing diagram illustrating an operation of a test input buffer in a state in which an RFID tag according to the third and fourth embodiments of the present invention is activated.

33 is a circuit diagram illustrating an input / output circuit unit according to third and fourth embodiments of the present invention.

34 is a circuit diagram illustrating test output drivers according to third and fourth embodiments of the present invention.

35 is a timing diagram illustrating the operation of the test output driver according to the third and fourth embodiments of the present invention.

36 is a circuit diagram showing a control output driver according to the third and fourth embodiments of the present invention.

37 is a timing diagram showing the operation of the control output driver according to the third and fourth embodiments of the present invention.

38 is a circuit diagram showing an address signal input / output unit according to the third and fourth embodiments of the present invention.

39 is a circuit diagram illustrating a control signal input / output unit according to third and fourth embodiments of the present invention.

40 is a circuit diagram illustrating a control signal input / output unit according to third and fourth embodiments of the present invention.

Fig. 41 is a circuit diagram showing a control result signal output unit according to the third and fourth embodiments of the present invention.

42 is a circuit diagram illustrating an antistatic part according to third and fourth embodiments of the present invention.

Claims (26)

In the RFID tag for transmitting and receiving radio signals with the RFID reader, A shift register which receives a test serial input signal and a test clock and generates and outputs a test serial output signal during a test operation; A test circuit unit activated by the test serial output signal during the test operation and providing a test input signal input from the outside during an activation period to test whether the RFID tag internal circuit operates normally; And An input / output pad unit configured to receive a power supply voltage and a ground voltage from an external device, receive the test serial input signal, the test clock, and the test input signal, and output the test serial output signal; And the test is performed by comparing the test input signal with a test output signal output from an RFID tag internal circuit provided with the test input signal. The method according to claim 1, The shift register And storing the value of the test serial input signal and outputting the value of the test serial input signal as a test serial output signal in synchronization with a test clock. The method according to claim 2, And the shift register is reset by a power on reset signal. The method according to claim 1, And the shift register is reset by a test reset signal input from the outside. The method according to claim 1, And a test input buffer configured to receive a demodulated signal demodulating the radio signal received from the RFID reader and the test input signal to generate a command signal. The method according to claim 5, And the test input buffer comprises an ORA logic element. The method according to claim 6, And the demodulation signal is output as the command signal when the test input signal is input at a low level. The method according to claim 6, And when the demodulation signal is input at a low level, output the test input signal as the command signal. The method according to claim 5, The test input buffer And a resistance element connected in parallel between an input terminal to which the test input signal is input and a ground terminal to bias the test input signal to a low level. The method according to claim 1, And a test signal output driver for driving the test result signal output from the test circuit unit as a test output signal when the test is completed. The method according to claim 10, The test signal output driver A driving unit driving the test result signal to generate the test output signal; And And a pull-up driving unit configured to pull up the test result signal inputted to the input terminal of the driving unit. A shift register which receives a test serial input signal and a test clock and generates and outputs a test serial output signal; A test circuit unit activated by the test serial output signal and performing a test according to an address signal and a control signal input from the outside during the activation period; And And an input / output pad unit configured to receive a power supply voltage and a ground voltage from an external source, receive the test serial input signal, the test clock and the address signal, and the control signal, and output the test serial output signal. The method according to claim 12, The shift register And storing the value of the test serial input signal and outputting the value of the test serial input signal as a test serial output signal in synchronization with a test clock. The method according to claim 12, The test circuit unit And performing a test according to the address signal and the control signal and generating and outputting a control result signal. delete delete delete The method according to claim 1 or 12, The RFID tag further includes a voltage limiter for restricting the power supply voltage supplied from the outside from higher than the power supply voltage level. The method according to claim 1 or 12, RFID tag comprising a memory block having a plurality of memory cells for storing data. The method of claim 19, The test circuit unit And selectively testing a memory cell, which is a test target, among the plurality of memory cells according to the test input signal. The method of claim 19, And the plurality of memory cells comprise ferroelectric capacitor elements. The method according to claim 10 The input / output pad unit A power supply voltage applying pad to which the power supply voltage is applied; A ground voltage applying pad to which the ground voltage is applied; A test serial signal input pad to which the test serial input signal is input; A test serial signal output pad to which the test serial output signal is output; A test clock input pad to which the test clock is input; A test signal input pad to which the test input signal is input; And RFID tag including a test signal output pad to which the test output signal is output. delete A shift register which receives a test serial input signal and a test clock and generates and outputs a test serial output signal; A test circuit unit activated by the test serial output signal and performing a test operation based on a test input signal input from the outside during the activation period; An RFID tag comprising an input / output pad unit for receiving a power supply voltage and a ground voltage from an external device, receiving the test serial input signal, the test clock, and the test input signal, and outputting the test serial output signal. The test operation is a method of testing whether an internal circuit of the RFID tag is normally operated based on the test input signal. Activating the test circuitry by the test serial output signal; Inputting the test input signal through the input / output pad unit; Providing, by the activated test circuit unit, the test input signal to an internal circuit of an RFID tag according to the test input signal, and generating a test output signal based on an output signal according to the provided test input signal; Outputting the test output signal to the outside; And And comparing the test input signal with the test output signal to test whether the internal circuit of the RFID tag operates normally. 27. The method of claim 24, Performing the test operation and generating a test output signal, Generating an address signal and a control signal from the test input signal; Performing a test operation according to the address signal and the control signal; And Completing a test and generating the test output signal. A shift register which receives a test serial input signal and a test clock and generates and outputs a test serial output signal; A test circuit unit activated by the test serial output signal and performing a test on whether a memory unit inside the RFID tag is normally operated based on an address signal and a control signal input from the outside during the activation period; An RFID tag including an input / output pad unit configured to receive a power supply voltage and a ground voltage from an external source, receive the test serial input signal, the test clock, the address signal, and the control signal, and output the test serial output signal; As a test method, Activating the test circuitry by the test serial output signal; Inputting the address signal and the control signal through the input / output pad unit; Providing, by the test circuit unit, the test input signal to the memory unit based on the address signal and the control signal to generate a test output signal based on the received output signal; Outputting the test output signal to the outside; And And comparing the test input signal with the test output signal to test whether the memory unit operates normally.

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