KR101150525B1 - RFID device and test method thereof - Google Patents

Abstract

Embodiments of the present invention relate to an RFID device and a test method thereof, and a technology related to an RFID tag chip (Radio Frequency IDentification Tag Chip) for communicating with an RFID reader using a radio signal. The embodiment of the present invention includes a memory unit in which data is read or written, and a test interface unit performing a dummy write operation of the memory unit during a specific period when the test operation signal is activated.

Description

Rfid device and test method thereof

Embodiments of the present invention relate to an RFID device and a test method thereof, and a technology related to an RFID tag chip (Radio Frequency IDentification Tag Chip) for communicating with an RFID reader using a radio signal.

RFID (Radio Frequency IDentification Tag Chip) is a contactless automatic identification method that communicates with an RFID reader by attaching an RFID tag to an object to be identified and automatically transmitting and receiving it by using a wireless signal. To provide technology. As RFID is used, it is possible to compensate for the disadvantages of the conventional automatic identification technology, barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

Meanwhile, a nonvolatile ferroelectric memory may be used as a memory used for an RFID tag.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is an overall configuration diagram of a general RFID device.

The RFID device according to the related art largely includes an antenna unit 1, an analog unit 10, a digital unit 20, and a memory unit 30.

Here, the antenna unit 1 serves to receive a radio signal transmitted from an external RFID reader. The wireless signal received through the antenna unit 1 is input to the analog unit 10 through the antenna pads 11 and 12.

The analog unit 10 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 20. In addition, the analog unit 10 senses the output voltage VDD and outputs a power-on reset signal POR and a clock CLK to the digital unit 20 for controlling the reset operation.

The digital unit 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 10, and outputs a response signal RP to the analog unit 10. The digital unit 20 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 30.

In addition, the memory unit 30 reads / writes data using a memory element and stores the data.

Here, the RFID device uses a frequency of several bands, the characteristics of which vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the RFID device operates in a short distance, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

Embodiments of the present invention have the following features.

First, it is possible to test the performance of an RFID tag chip by directly applying a measurement signal through a test pad without using a wireless signal applied from an antenna at the wafer level.

Second, by adding a dummy write cycle to increase the storage capacity of the cell to stabilize the characteristics of the memory cell.

Third, a dummy write cycle may be added to reduce the size of the memory cell and contribute to shrinking of the cell size.

According to an embodiment of the present invention, an RFID device includes a memory unit configured to read or write data, and including a ferroelectric capacitor element; And a test interface unit configured to perform a dummy write operation of the memory unit during a specific period when the test operation signal is activated.

In addition, the test method of the RFID device according to another embodiment of the present invention, the step of activating the test mode of the RFID chip when the test operation signal is activated; Performing a dummy write operation of the memory unit during a specific period when the test mode is activated; And performing a test of the memory unit and the digital processor through the external common test pad after the dummy write operation.

The present invention has the following effects.

First, the present invention enables the test of the performance of an RFID tag chip by directly applying a measurement signal through a test pad at the wafer level.

Second, by adding a dummy write cycle to increase the storage capacity of the cell to stabilize the characteristics of the memory cell.

Third, the dummy write cycle is added to reduce the size of the memory cell and contribute to shrinking the cell size.

In addition, the preferred embodiment of the present invention is for the purpose of illustration, those skilled in the art will be able to various modifications, changes, replacements and additions through the spirit and scope of the appended claims, such configuration changes, etc. It should be seen as belonging to a range.

1 is a block diagram of a conventional RFID device.
2 is a block diagram of an RFID device according to an embodiment of the present invention.
FIG. 3 is a detailed configuration diagram of the memory unit of FIG. 2. FIG.
FIG. 4 is a detailed circuit diagram of the cell array unit of FIG. 3. FIG.
FIG. 5 is a detailed circuit diagram of the sense amplifier of FIG. 4. FIG.
6 is an operation timing diagram relating to the cell array unit of FIG. 4;
FIG. 7 illustrates a dummy write operation section of the cell array unit of FIG. 4. FIG.
8 is a diagram for describing a method of operating a dummy write operation of the cell array unit of FIG. 4.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of an RFID tag chip in an RFID device according to an embodiment of the present invention.

The embodiment of the present invention does not receive a radio signal applied from the antenna 1 like the above-described conventional RFID device, but receives a measurement signal directly through a common test pad at a wafer level, thereby receiving an RFID tag chip (Radio Frequency Identification). Tag Chip's performance can be tested.

The RFID device according to the embodiment of the present invention largely includes an analog processing unit 100, a digital processing unit 200, a test interface unit 300, a memory unit 400, and a test control unit 500.

First, the analog processor 100 includes a voltage amplifier 110, a modulator 120, a demodulator 130, a power-on reset unit 140, a clock generator 150, and a test input buffer. 160 and a test output driver 170.

Here, the voltage amplifier 110 generates a driving voltage of the RFID according to the power supply voltage VDD applied from the power supply voltage application pad P2.

The modulator 120 modulates the response signal RP input from the digital processor 200. The demodulator 130 generates an operation command signal DEMOD according to the output voltage of the power supply voltage application pad P2, and outputs the generated operation command signal DEMOD to the test input buffer 160.

The power on reset unit 140 detects a voltage applied from the power voltage applying pad P2 and outputs a power on reset signal POR for controlling the reset operation to the digital processing unit 200. The clock generator 150 supplies the clock CLK for controlling the operation of the digital processor 200 according to the output voltage of the power voltage applying pad P2 to the digital processor 200.

Here, the power-on reset signal POR rises together with the power supply voltage while the power supply voltage transitions from the low level to the high level, and then transitions from the high level to the low level at the moment the power supply is supplied to the power supply voltage level VDD, thereby causing a circuit inside the RFID tag. Means a signal to reset.

The test input buffer 160 commands a command according to a test input signal RXI input through the test signal input pad P4, an operation command signal DEMOD input from the demodulator 130, and a test activation signal TSTEN applied from the test control unit 500. The signal CMD is output to the digital processor 200.

That is, when the test activation signal TSTEN is deactivated in the normal operation mode, the test input buffer 160 supplies the command signal CMD to the digital processing unit 200 according to the operation command signal DEMOD applied from the demodulator 130.

On the other hand, when the test activation signal TSTEN is activated in the test operation mode, the test input buffer 160 transmits a command signal CMD for testing RFID according to the test input signal RXI applied from the test signal input pad P4 to the digital processing unit 200. Supply.

In addition, the test output driver 170 drives the test output signal TXO according to the response signal RP input from the digital processor 200 to output the command processing result of the RFID to the outside through the test signal output pad P1.

Here, the voltage amplifier 110, the modulator 120, the demodulator 130, the power-on reset unit 140, the clock generator 150, the test input buffer 160 and the test output driver 170 are In the test operation mode for testing the performance of the RFID, it is driven by the power supply voltage VDD applied from the external power supply voltage application pad P2 and the ground voltage GND applied from the external ground voltage application pad P3.

That is, the power supply voltage applying pad P2 indicates a pad to which the power supply voltage VDD is applied when the RFID tag is activated to test a plurality of RFID tags on the wafer. The ground voltage applying pad P3 represents a pad to which the ground voltage GND is applied when the plurality of RFID tags are tested on the wafer.

When the RFID tag communicates with the RFID reader to receive a wireless signal, the voltage amplifier 110 supplies the power supply voltage VDD. However, in the present invention, since the test is performed on the wafer, a separate power supply voltage pad P2 and ground voltage are performed. The supply voltage VDD and the ground voltage GND are supplied through the application pad P3.

The digital processor 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog processor 100, and interprets the command signal CMD and generates control signals and processing signals. The digital processor 200 outputs a response signal RP corresponding to the control signal and the processing signals to the analog processor 100.

In addition, the digital processor 200 outputs the address DADD, the input data DI, the chip enable signal DCE, the write enable signal DWE, and the output enable signal DOE to the test interface 300. In addition, the digital processing unit 200 is applied with the output data DO from the test interface unit 300.

In addition, the test interface unit 300 is activated according to the test activation signal TSTEN applied from the test control unit 500. When the test interface unit 300 is activated, the memory unit 400 is tested according to a tag selection address, a memory address, input data, and a control signal XCE, XWE, XOE, or TACT input from the outside.

Among the control signals described above, XCE represents a chip enable signal. Among the control signals, XWE represents a write enable signal, XOE represents an output enable signal, and TACT represents a test operation signal.

Here, the test interface 300 may include tag selection addresses, memory addresses, and input data input through the common test pad P5, and control signals XCE and XWE input through the control signal input pads P9 to P11 and the test input pad P12. The memory unit 400 is tested by generating address ADD and control signals I, CE, WE, and OE according to XOE and TACT.

The test interface unit 300 receives the control result signal O and outputs the output data XDO to the outside through the data output pad P8.

Meanwhile, when the test interface 300 is activated, the internal circuits included in the RFID tag, that is, the analog processing unit 100 and the digital, according to the address DADD and the control signals DI, DCE, DWE, and DOE input from the digital processing unit 200. The processor 200 and the memory 400 are tested.

To test the entire operation of the RFID tag, the digital processor 200 generates the address DADD and the control signals DI, DCE, DWE, and DOE by the command signal CMD generated according to the test input signal RXI.

The test interface 300 generates the address ADD and the control signals I, CE, WE, and OE according to the address DADD and the control signals DI, DCE, DWE, and DOE to test the entire operation of the RFID tag. The test interface 300 receives a control result signal O, which is a test result, from the memory unit 400 and generates a control result signal DO.

The digital processor 200 generates a response signal RP according to the control result signal DO. In addition, the test output driver 170 drives the response signal RP and outputs it through the test signal output pad P1.

The memory unit 400 includes a plurality of memory cells, each memory cell writes data to a storage element, and serves to read data stored in the storage element.

Here, the memory unit 400 may be a nonvolatile ferroelectric memory (FeRAM). FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

The test control unit 500 serves to activate the RFID tag in the test mode. The test control unit 500 receives a test operation signal TACT from the test input pad P12 and a test clock TCLK from the test clock input pad P13. The test controller 500 outputs a test activation signal TSTEN for controlling whether the RFID tag is activated to the test input buffer 160 and the test interface unit 300.

As described above, when the test activation signal TSTEN is activated in the test mode, the present invention outputs a test result of the RFID device through the test signal output pad P1 or externally through the data output pad P8.

That is, when testing the entire operation of the RFID device, the test input signal RXI input through the test signal input pad P4 is transmitted to the digital processing unit 200, the test interface unit 300, and the memory unit 400, and the test is performed again. It is output through the test output pad P1 via the interface unit 300, the digital processing unit 200, and the test output driver 170. Then, the external test equipment measures the output of the test signal output pad P1 to test the entire operation of the RFID device.

On the other hand, when only testing the memory unit 400 of the RFID device, the address and data input through the common test pad P5 is transferred to the memory unit 400 via the test interface unit 300, and again the test interface unit ( 300 is output via the data output pad P8. Then, the external test equipment measures the output of the data output pad P8 to test the operation of the memory unit 400.

3 is a detailed block diagram illustrating the memory unit 400 of FIG. 2.

The memory unit 400 includes a word line decoder 410, a control signal processor 420, a cell array unit 430, a sense amplifier, and an input / output buffer 440.

Here, the word line decoder 410 decodes the word line WL according to the address ADD applied from the test interface unit 300 and outputs the word line WL to the cell array unit 430. Here, the address ADD [7: 0] represents an address applied from the test interface unit 300.

The control signal processor 420 is configured to drive the cell array unit 430 according to control signals such as a chip enable signal CE and an output enable signal OE and a write enable signal WE applied from the test interface unit 300. The word line WL and the cell plate line PL are controlled.

The control signal processor 420 may sense the amplifier and the input / output buffer 440 according to control signals such as the chip enable signal CE and the output enable signal OE and the write enable signal WE applied from the test interface unit 300. To control the operation.

That is, the control signal processor 420 may include a sense amplifier enable signal for controlling whether the sense amplifier 440 is activated, an output enable signal for outputting data sensed by the sense amplifier 440 to the data bus M_DATA, and the like. A write enable signal for writing data applied from the data bus M_DATA to the cell array unit 430 is output.

The cell array unit 430 includes a nonvolatile ferroelectric memory (FeRAM). The cell array unit 430 includes a plurality of memory cells, and one of the plurality of memory cells is selected by an address output from the word line decoder 410. The cell array unit 430 includes a plurality of unit cells including a ferroelectric element and a switching element to store data in the ferroelectric element and to read the stored data.

In addition, the operation of the sense amplifier and the input / output buffer 440 is controlled according to the sense amplifier enable signal, the output enable signal OE, and the write enable signal WE applied from the control signal processor 420 based on the reference voltage. .

The sense amplifier and the input / output buffer 440 sense and amplify the data applied from the cell array unit 430, output the data to the data bus M_DATA, and transfer the data applied from the data bus M_DATA to the cell array unit 430.

Looking at the function of each control signal in the memory unit 400 having such a configuration is shown in Table 1 below.

Control signal I / O Description ADD input Address applied from the test interface 300 CE input The chip enable signal applied from the test interface 300 WE input The write enable signal applied from the test interface 300 OE input Output enable signal applied from the test interface unit 300 M_DATA Input / output I / O data bus

4 is a detailed circuit diagram illustrating the cell array unit 430 of FIG. 3.

In FIG. 4, a case in which a unit cell UC of a nonvolatile ferroelectric memory (FeRAM) is formed of cells C1 and C2 having a structure of 2T (Transistor) 2C (Capacitor) will be described. Here, the cell C1 of one 1T1C structure is connected to the bit line BL to store positive data, and the cell C2 of the other 1T1C structure to store negative data.

In an embodiment of the present invention, a plurality of word lines WL0 to WLn and a plurality of plate lines PL0 to PLn are arranged in a row direction. Here, one word line WL is selected by receiving a separate address from the plurality of word lines WL0 through WLn, and one plate line PL is selected by receiving a separate address from the plurality of plate lines PL0 through PLn. A plurality of bit line pairs BL0, / BL0 to BLm, / BLm are arranged in the column direction.

Further, the unit cell UC is formed in an area where a plurality of word lines WL0 to WLn, a plurality of plate lines PL0 to PLn, and a plurality of bit line pairs BL0, / BL0 to BLm, / BLm intersect.

In the unit cell UC, the cell C1 includes the switching element T1 and the ferroelectric element F1. The switching element T1 is connected between the bit line BL0 and the ferroelectric element F1 so that the gate terminal is connected to the word line WL0. Here, it is preferable that the switching element T1 consists of an NMOS transistor. The ferroelectric element F1 is connected between the switching element T1 and the plate line PL.

In the unit cell UC, the cell C2 includes the switching element T2 and the ferroelectric element F2. The switching element T2 is connected between the bit line / BL0 and the ferroelectric element F2 so that the gate terminal is connected to the word line WL0. Here, the switching element T1 consists of an NMOS transistor. The ferroelectric element F2 is connected between the switching element T2 and the plate line PL.

In addition, the sense amplifier 440 is connected to the bit line pair BL0, / BL0 to sense and amplify cell data applied from the unit cell UC. Here, one sense amplifier 440 is shared by bit line pairs BL0 and / BL0.

FIG. 5 is a detailed circuit diagram illustrating the sense amplifier 440 of FIG. 4.

The sense amplifier 440 includes an activation controller and an amplifier. Here, the activation controller includes a PMOS transistor PM1 and an NMOS transistor N3. The amplification unit includes PMOS transistors PM2 and PM3 and NMOS transistors N1 and N2.

The PMOS transistor PM1 is connected between the power supply voltage terminal and the PMOS transistors PM2 and PM3 so that the sense amplifier enable signal / SEN is applied through the gate terminal. The NMOS transistor N3 is connected between the ground voltage terminal and the NMOS transistors N1 and N2 so that the sense amplifier enable signal SEN is applied through the gate terminal.

The PMOS transistors PM2 and PM3 and the NMOS transistors N1 and N2 are connected between the PMOS transistor PM1 and the NMOS transistor N3 so that the gate terminals are cross coupled. The common drain terminal of the PMOS transistors PM2 and NMOS transistor N1 is connected to the bit line BL, and the common drain terminal of the PMOS transistors PM3 and NMOS transistor N3 is connected to the bit line / BL.

6 is an operation timing diagram of the cell array unit 430 of FIG. 4.

First, the bit line equalization signal BLEQ is activated in the t0 section, which is a bit line precharge section, to precharge the bit line pair BL // BL. At this time, the chip enable signal CE applied from the test interface 300 maintains a low level. The word line WL, the plate line PL, and the sense amplifier enable signal SEN are maintained at a low level.

Thereafter, in the period t1, the chip enable signal CE applied from the test interface unit 300 transitions to a high level. As a result, the word line WL and the plate line PL of the cell array unit 430 transition to a high level. Accordingly, charge sharing of the cell data is started in the bit line pair BL // BL to perform a sensing voltage development operation. At this time, the bit line equalization signal BLEQ transitions to a low level.

Subsequently, in the period t2, the sense amplifier enable signal SEN transitions to a high level so that the sense amplifier 440 operates. Accordingly, the voltage difference between the bit line pairs BL and / BL is sensed and amplified by the sense amplifier 440.

Next, in the period t3, the plate line PL transitions to the low level. Accordingly, a rewrite operation of data '0' is performed in a period t2 and a rewrite operation of a data '1' is performed in a period t3.

Thereafter, in the period t4 which is the bit line precharge period, the chip enable signal CE applied from the test interface unit 300 transitions to the low level. The word line WL and the sense amplifier enable signal SEN transition to a low level. At this time, the bit line equalization signal BLEQ transitions to a high level.

FIG. 7 is a diagram for describing a dummy write operation section of the cell array unit 430 of FIG. 4.

In FIG. 7, section (A) indicates a section in which the dummy write operation of the cell array unit 430 is required.

The cell operation characteristics of FeRAM are as follows. In the first wafer processing state, there are some regions in which the ferroelectric domain array of the capacitors is arbitrarily arranged in the cell capacitor characteristics of the memory unit 400.

These regions do not coincide with the applied voltage direction of the capacitor and are arranged in 90 degrees or other directions. As a result, the capacitor does not contribute to the charge storage, so that the storage capacity of the capacitor does not reach the maximum value.

The embodiment of the present invention repeatedly performs a write operation using a dummy cycle to readjust the initial domain arrangement.

Then, the orientation of the domains not aligned by the write voltage is gradually arranged toward the write voltage by the write voltage.

As the cycle increases, the ratio of domains arranged in the same direction as the write voltage increases, which increases the storage capacity of the capacitor.

Therefore, the embodiment of the present invention allows the FeRAM cell to have a high storage capacity by driving a dummy write cycle for a predetermined time period to the FeRAM in the initial wafer.

Here, the constant time interval means the interval (A) of FIG. 7. In the exemplary embodiment of the present invention, the dummy write operation is performed about 10 to 1000 times, 1 to 1000 times, or 100 to 900 times in the section (A) where the dummy write operation of the cell array unit 430 is required.

In addition, an embodiment of the present invention allows the memory cell to be made smaller by adding a dummy write cycle to improve the storage capacity of the cell. When the size of the memory cell is reduced, it is possible to contribute to the shrink of the cell size.

FIG. 8 is a diagram for describing a dummy write operation method of the cell array unit 430 of FIG. 4.

First, when the test operation signal TACT is activated to perform the dummy write operation of the cell array unit 430, the test mode of the RFID chip is activated by the test interface unit 300 (step S1).

When the test mode of the RFID chip is activated, the dummy write operation of the cell array unit 430 is performed under the control of the test interface unit 300 during the section (A) of FIG. 7 (step S2).

In this case, when the test mode is activated, the test interface unit 300 receives data applied from the common test pad P5 and performs a dummy write operation of the memory unit 400.

In the initial wafer state, the capacitor may become unstable. Accordingly, the data storage capacity of the cell is improved by randomly writing data “0” or “1” to the cell array unit 430 at an initial value during the dummy write period.

Here, the dummy write section may be described as a section until the ferroelectric domain array of the capacitors included in the cell array unit 430 is aligned.

Subsequently, the operation of the memory unit 400 and the digital processing unit 200 is tested through the test input buffer 160 and the test output driver 170 (step S3).

Next, an initialization write operation of the memory unit 400 is performed to set an initialization condition of the RFID chip. (Step S4).

Claims (14)

A memory unit configured to read or write data and including a ferroelectric capacitor element; And
When the test operation signal is activated includes a test interface for performing a dummy write operation of the memory unit for a specific period,
And the specific section is a section until the array of ferroelectric domains of the ferroelectric capacitor device is aligned. Claim 2 has been abandoned due to the setting registration fee. The RFID device of claim 1, wherein the dummy write operation is performed at a wafer level of an RFID chip. Claim 3 was abandoned when the setup registration fee was paid. The RFID device of claim 1, wherein data “0” or data “1” is randomly written to the memory unit during the dummy write operation. delete delete Claim 6 was abandoned when the registration fee was paid. The RFID device of claim 1, further comprising a common test pad configured to supply data to the test interface unit during the dummy write operation. Activating a test mode of the RFID chip upon activation of the test operation signal;
Performing a dummy write operation of a memory unit during a specific period when the test mode is activated; And
And testing the memory unit and the digital processor through an external common test pad after the dummy write operation. Claim 8 was abandoned when the registration fee was paid. 8. The method of claim 7, wherein the dummy write operation is performed at the wafer level of the RFID chip. Claim 9 was abandoned upon payment of a set-up fee. The test method according to claim 7, wherein the data "0" or data "1" is randomly written in the memory unit during the dummy write operation. Claim 10 has been abandoned due to the setting registration fee. 8. The method of claim 7, wherein the memory unit comprises a ferroelectric capacitor element. Claim 11 was abandoned upon payment of a setup registration fee. The test method of claim 10, wherein the specific section is a section until the array of ferroelectric domains of the ferroelectric capacitor device is aligned. Claim 12 is abandoned in setting registration fee. The test method of claim 7, further comprising applying dummy write data through the external common test pad during the dummy write operation. delete Claim 14 has been abandoned due to the setting registration fee. The test method of claim 7, further comprising: performing an initialization write operation of the memory unit to set an initialization condition of the RFID chip.

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