KR101218280B1 - RFID device - Google Patents

Abstract

An embodiment of the present invention relates to an RFID device, and a technology related to an RFID tag chip (Radio Frequency IDentification Tag Chip) that communicates with an RFID reader using a radio signal. This embodiment of the present invention, the memory unit to read or write data, the level of the power supply voltage applied to the RFID is detected, and pumping the power supply voltage corresponding to the clock to output a first pumping voltage higher than the power supply voltage The pumping voltage generating unit and a step-pulse pumping unit for supplying a second pumping voltage higher than the first pumping voltage to the memory unit by pumping the first pumping voltage during operation of the memory unit.

Description

RFID device {RFID device}

An embodiment of the present invention relates to an RFID device, and a technology related to an RFID tag chip (Radio Frequency IDentification Tag Chip) that communicates with an RFID reader using a radio signal.

RFID (Radio Frequency IDentification Tag Chip) is a contactless automatic identification method that communicates with an RFID reader by attaching an RFID tag to an object to be identified and automatically transmitting and receiving it by using a wireless signal. To provide technology. As RFID is used, it is possible to compensate for the disadvantages of the conventional automatic identification technology, barcode and optical character recognition technology.

Recently, RFID tags have been used in various cases, such as logistics management systems, user authentication systems, electronic money systems, transportation systems.

For example, in the logistics management system, cargo classification or inventory management is performed using an integrated circuit (IC) tag in which data is recorded instead of a delivery slip or a tag. In the user authentication system, admission management and the like are performed using an IC card that records personal information and the like.

Meanwhile, a nonvolatile ferroelectric memory may be used as a memory used for an RFID tag.

In general, nonvolatile ferroelectric memory, or ferroelectric random access memory (FeRAM), has a data processing speed of about dynamic random access memory (DRAM) and is attracting attention as a next-generation memory device because of its characteristic that data is preserved even when the power is turned off. have.

The FeRAM is a device having a structure almost similar to that of a DRAM, and uses a ferroelectric capacitor as a memory device. Ferroelectrics have a high residual polarization characteristic, and as a result, the data is not erased even when the electric field is removed.

1 is a block diagram of a general RFID device.

The RFID device according to the related art includes an antenna unit 1, an analog unit 10, a digital unit 20, and a memory unit 30.

Here, the antenna unit 1 serves to receive a radio signal transmitted from an external RFID reader. The wireless signal received through the antenna unit 1 is input to the analog unit 10 through the antenna pads 11 and 12.

The analog unit 10 amplifies the input wireless signal to generate a power supply voltage VDD which is a driving voltage of the RFID tag. The operation command signal is detected from the input wireless signal, and the command signal CMD is output to the digital unit 20. In addition, the analog unit 10 senses the output voltage VDD and outputs a power-on reset signal POR and a clock CLK to the digital unit 20 for controlling the reset operation.

The digital unit 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog unit 10, and outputs a response signal RP to the analog unit 10. The digital unit 20 also outputs the address ADD, input / output data I / O, control signal CTR, and clock CLK to the memory unit 30.

In addition, the memory unit 30 reads / writes data using a memory element and stores the data.

Here, the RFID device uses a frequency of several bands, the characteristics of which vary depending on the frequency band. In general, the lower the frequency band, the slower the recognition speed, the RFID device operates in a short distance, and is less affected by the environment. On the contrary, the higher the frequency band, the faster the recognition speed and the longer the distance is affected by the environment.

Such an RFID chip passive element operates by using a power delivered to an antenna. However, in the case of the RFID chip for long-distance operation, the power delivered to the antenna is very weak. Therefore, each block circuit of the RFID chip should be designed to consume the least power, and the low power supply should be used up.

However, the conventional RFID device continues to supply a constant voltage to the memory block even when the memory cell does not perform a read / write operation in the memory block. That is, the memory cell needs to supply the pumping voltage only when reading / writing data to the cell.

However, in the conventional RFID device, a power supply voltage is generated from the voltage multiplier 110 provided in the analog unit 10 to continuously supply the pumping voltage to the memory block regardless of whether the memory cell is activated. That is, the continuous boost operation is performed until the memory unit 30 is boosted to a stable power supply voltage level. As a result, unnecessary current consumption increases with oscillation of the voltage multiplier.

Embodiments of the present invention have the following features.

First, in the memory block of the RFID device, the pumping voltage VPP2 may be supplied only to a circuit required for the read / write operation of the memory cell or to drive the memory cell, thereby reducing current consumption due to the unnecessary pumping voltage. have.

Second, the low power supply voltage is supplied to the analog processing unit and the digital processing unit, and the high pumping voltage is gradually supplied by using a clock to minimize power consumption.

According to an embodiment of the present invention, an RFID device includes a memory unit configured to read or write data; A pumping voltage generation unit configured to detect a level of a power supply voltage applied to the RFID and output a first pumping voltage higher than the power supply voltage by pumping the power supply voltage in response to a clock; And a step-pulse pumping unit configured to supply a second pumping voltage higher than the first pumping voltage to the memory unit by pumping the first pumping voltage during operation of the memory unit, wherein the step-pulse pumping unit is included in the memory unit. do.

An embodiment of the present invention has the following effects.

First, the pumping voltage VPP2 is supplied only to a circuit required for the read / write operation of the memory cell or to drive the memory cell in the memory block of the RFID device, thereby reducing current consumption due to the unnecessary pumping voltage supply.

Second, it provides a low power supply voltage to the analog processing unit and the digital processing unit, and supplies a high pumping voltage step by step using a clock to minimize the power consumption.

It will be apparent to those skilled in the art that various modifications, additions, and substitutions are possible, and that various modifications, additions and substitutions are possible, within the spirit and scope of the appended claims. As shown in Fig.

1 is a block diagram of a conventional RFID device.
2 is a block diagram of an RFID device according to an embodiment of the present invention.
3 is a view for explaining a voltage level according to an embodiment of the present invention.
4 is a circuit diagram of a pumping voltage generator of FIG. 2.
5 is a detailed circuit diagram illustrating a pumping voltage detector of FIG. 4.
6 is an operation waveform diagram illustrating a pumping voltage detector of FIG. 5.
7 is an operation timing diagram relating to the pumping voltage generator of FIG. 4.
FIG. 8 is a detailed circuit diagram of the step-pulse pumping part of FIG. 2. FIG.
9 is an operation timing diagram relating to the step-pulse pumping unit of FIG. 8;

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a radio frequency identification (RFID) device according to an embodiment of the present invention.

An embodiment of the present invention includes an analog processor 100, a digital processor 200, and a memory unit 300.

The analog processor 100 may include a voltage multiplier 110, a modulator 120, a demodulator 130, a power on reset unit 140, a clock generator unit 150 and the pumping voltage generator 160.

The antenna ANT connected to the analog processor 100 is a component for transmitting and receiving data between an external reader or writer and RFID. The voltage multiplier 110 generates a power supply voltage VDD which is a driving voltage of the RFID by the radio signal RF applied from the antenna ANT.

In addition, the modulator 120 modulates the response signal RP applied from the digital processor 200 and transmits the modulated response signal RP to the antenna ANT. The demodulator 130 detects an operation command signal from the radio signal RF applied from the antenna ANT according to the output voltage of the voltage multiplier 110 and outputs the command signal CMD to the digital processor 200.

The power on reset unit 140 detects the output voltage VDD of the voltage multiplier 110 and outputs a power on reset signal POR for controlling the reset operation to the digital processing unit 200.

The clock generator 150 supplies a clock CLK for controlling the operation of the digital processor 200 to the digital processor 200 according to the output voltage VDD of the voltage multiplier 110. The clock generator 150 outputs the generated clock CLK to the pumping voltage generator 160.

The pumping voltage generator 160 is controlled according to the clock CLK applied from the clock generator 150 to detect the level of the power supply voltage VDD applied from the voltage multiplier 110 and to pump the pumping voltage VPP1. Output to the pulse pumping unit 310.

In addition, the digital processor 200 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK, and the command signal CMD from the analog processor 100, interprets the command signal CMD, generates control signals and processing signals, and generates an analog processor. The response signal RP corresponding to 100 is output. The digital processor 200 outputs an address ADD, input / output data I / O, and a control signal CTR to the memory unit 400.

The memory unit 300 includes a plurality of memory cells, each of which writes data to a storage element and reads data stored in the storage element.

The memory unit 300 may use a nonvolatile ferroelectric memory (FeRAM). FeRAM has a data processing speed of about DRAM. In addition, FeRAM has a structure almost similar to DRAM, and has a high residual polarization characteristic of the ferroelectric by using a ferroelectric as the material of the capacitor. Due to this residual polarization characteristic, data is not erased even when the electric field is removed.

The step-pulse pumping unit 310 provided in the memory unit 300 secondly pumps the pumping voltage VPP1 applied from the pumping voltage generation unit 160 according to the pumping enable signal VPP2_EN to output the pumping voltage VPP2. Here, the step-pulse pumping unit 310 boosts the voltage level of the memory cell only when the word line is activated during the read or write operation of the memory cell.

The pumping enable signal VPP2_EN is a memory unit according to the control signal CTR applied from the digital processing unit 200, that is, the chip enable signal CE, the output enable signal OE, and the write enable signal WE. The signal is generated by a peripheral circuit unit (not shown) provided inside the 300.

According to the pumping enable signal VPP2_EN, the step-pulse pumping unit 310 may be driven to supply the pumping voltage VPP2 to the memory cell once per cycle during the read / write operation. That is, during the read / write operation of the memory cell, the pumping enable signal VPP2_EN is activated to activate the word line driver and the plate line driver for driving the memory cell according to the pumping voltage VPP1.

FIG. 3 is a diagram for describing the voltage level in FIG. 2.

Referring to FIG. 3, the power supply voltage VDD has a level higher than the ground voltage VSS. The pumping voltage VPP1 generated by the pumping voltage generator 160 has a level higher than that of the power supply voltage VDD. Here, the pumping voltage VPP1 is a primary boosted voltage generated using the power supply voltage VDD. In addition, the pumping voltage VPP2 generated by the step-pulse pumping unit 310 has a level higher than that of the pumping voltage VPP1. Here, the pumping voltage VPP2 is a secondary boosted voltage generated using the pumping voltage VPP1.

4 is a detailed circuit diagram illustrating the pumping voltage generator 160 of FIG. 2.

The pumping voltage generator 160 may include a driver 161, a ferroelectric capacitor 162, a charger 163, a rectifier 164, a pumping voltage detector 165, and a pumping voltage output unit 166.

Here, the driver 161 includes an AND gate AND1 as an input driver, inverters IV1 and IV2, and a PMOS transistor P1 and an NMOS transistor N1 as driving elements.

The AND gate AND1 performs an AND operation on the clock CLK and the detection voltage VPP1REG. The inverters IV1 and IV2 non-invert the delay of the output of the AND gate AND1 to the ferroelectric capacitor 162. The PMOS transistor P1 and the NMOS transistor N1 are connected in series between the power supply voltage terminal and the ground voltage terminal, and the output of the inverter IV1 is applied through the gate terminal. In addition, the output of the node A is applied to the bulk of the PMOS transistor P1.

The ferroelectric capacitor 162 includes a plurality of ferroelectric capacitors FC1 to FC3 connected in parallel between the node A and the output terminal of the inverter IV2.

The charging unit 163 includes a PMOS transistor P2. Here, the PMOS transistor P2 is connected between the power supply voltage terminal and the node A, the gate terminal is connected to the node B, and the output of the node A is applied to the bulk.

The rectifier 164 includes a PN type diode D connected in the forward direction between the node A and the output terminal of the pumping voltage VPP1. The rectifier 164 rectifies the voltage of the node A and outputs the pumping voltage VPP1.

The pumping voltage detector 165 detects the voltage level of the pumping voltage VPP1 and outputs the detection voltage VPP1REG to the AND gate AND1.

The pumping voltage output unit 166 includes a plurality of ferroelectric capacitors FC4 and FC5 connected in parallel between the output terminal of the pumping voltage VPP1 and the ground voltage terminal.

FIG. 5 is a detailed circuit diagram illustrating the pumping voltage detector 165 of FIG. 4.

The pumping voltage detector 165 includes a voltage detector 170 and a pumping voltage controller 180. Here, the voltage detector 170 includes a reference voltage generator 171, a voltage sensor 172, and an amplifier 173. In addition, the pumping voltage controller 180 includes a buffer unit 181 and a driver 182.

The reference voltage generator 171 outputs a reference voltage ref including the pull-up resistor R1 and the NMOS transistor N2. The resistor R1 is connected between the pumping voltage VPP1 applying stage and the output terminal of the reference voltage ref. The NMOS transistor N2 is connected between the output terminal of the reference voltage ref and the ground voltage terminal, and the gate terminal and the drain terminal are commonly connected to serve as a diode having a threshold voltage (Vt) characteristic.

Here, since the NMOS transistor N2 is turned off at the pumping voltage VPP1 below the threshold voltage Vt, the reference voltage ref becomes equal to the pumping voltage VPP1 level. On the other hand, in the NMOS transistor N2, the current flows through the NMOS transistor N2 at the pumping voltage VPP1 above the threshold voltage Vt, thereby increasing the voltage drop at the resistor R1. Then, the reference voltage ref sets the value of the resistor R1 large so that the reference voltage ref becomes a saturation state with the threshold voltage Vt.

The amplifier 173 has a differential amplifier type including current limiting resistors R4 and R5, PMOS transistors P3 and P4 and NMOS transistors N3 and N4. Here, the current limiting resistors R4 and R5 are current limiting elements for limiting the driving current of the circuit to reduce current consumption.

The current limiting resistor element R4 is connected between the pumping voltage VPP1 applying stage and the common source terminal of the PMOS transistors P3 and P4. The current limiting resistor R5 is connected between the common source terminal of the NMOS transistors N3 and N4 and the ground voltage terminal.

The PMOS transistors P3 and P4 are connected between the current limiting resistor element R4 and the NMOS transistors N3 and N4 so that the common gate terminal is connected to the drain terminal of the PMOS transistor P3. The NMOS transistors N3 and N4 are connected between the PMOS transistors P3 and P4 and the current limiting resistor R5 to apply the differential input reference voltage ref and sensed voltage sense through their respective gate terminals.

In addition, the voltage sensing unit 172 outputs a sensing voltage sense including resistors R2 and R3. Resistor R2 is connected between the pumping voltage VPP1 applied stage and the output terminal of the sensed voltage sense. Resistor R3 is connected between the output terminal of the sense voltage sense and the ground voltage terminal. The level of sensing voltage sense is determined by the resistance ratio of resistors R2 and R3.

Here, assuming that the value of the resistor R3 among the resistors R1 to R3 is X, the resistor R2 has a resistance value of mX which is m times larger than the resistor R3. The resistor R1 has a resistance value of nX that is n times larger than the resistor R3.

In addition, the buffer unit 181 includes resistors R6 and R7, a PMOS transistor P5, and an NMOS transistor N5. The buffer unit 181 buffers the output of the amplifier 173 and outputs a voltage having a CMOS level. Resistor R6, PMOS transistor P5, NMOS transistor N5 and resistor R7 are connected in series between the pumping voltage VPP1 applied stage and ground voltage stage. In the PMOS transistor P5 and the NMOS transistor N5, a common gate terminal is connected to the output terminal of the amplifier 173.

Here, the current limiting resistors R6 and R7 are current limiting elements for reducing the current consumption by limiting the driving current of the buffer unit 181.

In addition, the driving unit 182 includes an inverter IV3. The inverter IV3 inverts the output of the buffer unit 181 to output the detection voltage VPP1REG.

FIG. 6 is an operation waveform diagram illustrating the pumping voltage detector 165 of FIG. 5.

First, the pumping voltage VPP1 gradually increases until the node voltage reaches a predetermined level or more, and the pumping voltage VPP1 level has a constant level when the target level is reached.

Here, the reference voltage ref has a level higher than the sensing voltage sense during the period in which the level of the pumping voltage VPP1 gradually rises, that is, before the pumping voltage VPP1 reaches the target level. In this case, the output of the amplifier 173 becomes high level and the detection voltage VPP1REG becomes high level.

On the other hand, when the level of the pumping voltage VPP1 increases to maintain a constant level, that is, when the pumping voltage VPP1 reaches the target level, the sensing voltage sense is higher than the reference voltage ref. In this case, the amplifier 173 goes low and the detection voltage VPP1REG goes low.

That is, the sensing voltage sense is a signal that is proportionally changed by the resistance ratio (X: mX) of the resistor R3 and the resistor R2. Therefore, when the pumping voltage VPP1 becomes lower than the target pumping voltage VPP1, the detection voltage VPP1REG is at a low level.

In the region where the pumping voltage VPP1 is low, the reference voltage ref is larger than the sensing voltage sense. However, in the pumping voltage VPP1 above the target voltage, the sensing voltage sense becomes larger than the reference voltage ref, and the detection voltage VPP1REG transitions to the low level.

FIG. 7 is an operation timing diagram of the pumping voltage generator 160 of FIG. 4.

First, the t1 section is a section in which the power supply voltage VDD rises. When the power supply voltage VDD is equal to or higher than the operating voltage level of the CMOS in the t1 period, the clock CLK starts to be generated from the clock generator 150.

In addition, the pumping voltage generator 160 operates in response to the clock CLK. The pumping voltage detector 165 generates a detection voltage VPP1REG that gradually rises corresponding to the level of the power supply voltage VDD. The pumping voltage VPP1 gradually rises according to the detection voltage VPP1REG.

Thereafter, in the t2 period, the power supply voltage VDD maintains a constant level, and the detection voltage VPP1REG also maintains a constant level corresponding to the level of the power supply voltage VDD. In addition, the pumping voltage VPP1 gradually rises even in the period t2 according to the clock CLK and the pumping voltage output unit 166.

Subsequently, in the period t3, the pumping voltage VPP1 reaches the target voltage level, thereby maintaining a constant level. Then, the detection voltage VPP1REG transitions to the low level. As a result, the pumping operation of the pumping voltage VPP1 is stopped and the pumping voltage VPP1 level is maintained as it is.

FIG. 8 is a detailed circuit diagram of the step-pulse pumping unit 310 of FIG. 2.

The step-pulse pumping unit 310 includes a driving unit 311, a ferroelectric capacitor 312, and a charging unit 313.

The driver 311 includes inverters IV4 and IV5 as input drivers, PMOS transistors P6 and NMOS transistors N6 as driving elements. Inverters IV4 and IV5 output the non-inverted delay of the pumping enable signal VPP2_EN to the ferroelectric capacitor 312. The PMOS transistor P6 and the NMOS transistor N6 are connected in series between the pumping voltage VPP1 supply terminal and the ground voltage terminal, and the output of the inverter IV4 is applied through the gate terminal. In addition, the output of the node C is applied to the bulk of the PMOS transistor P6.

The ferroelectric capacitor 312 includes a plurality of ferroelectric capacitors FC6 to FC8 connected in parallel between the node C and the output terminal of the inverter IV5.

The charging unit 313 includes a PMOS transistor P7. Here, the PMOS transistor P7 is connected between the pumping voltage VPP1 applying terminal and the node C so that the gate terminal is connected to the node D, and the output of the node C is applied to the bulk.

9 is an operation timing diagram of the step-pulse pumping unit 310 of FIG. 5.

First, in the period t1, the pumping enable signal VPP2_EN maintains a low level. The output of inverter IV4 goes high when the pumping enable signal VPP2_EN is at the low level. Accordingly, the NMOS transistor N6 of the driver 311 is turned on to maintain the node D in the low level.

At this time, when the node D is at the low level, the PMOS transistor P7 is turned on so that the node C maintains the pumping voltage VPP1 level during normal operation. Accordingly, the node C is at the pumping voltage VPP1 level, and the output terminal of the pumping voltage VPP2 is output at the pumping voltage VPP1 level.

Here, when the memory cell does not perform a read or write operation, the word line WL, the plate line PL, and the bit line BL maintain the ground voltage VSS level.

Thereafter, the memory cell performs a sensing operation so that the pumping enable signal VPP2_EN transitions to the pumping voltage VPP1 level when the t2 section in which the word line WL, the bit line BL, and the plate line PL of the memory cell are activated is entered. Accordingly, when the output of the inverter IV4 becomes low, the PMOS transistor P6 is turned on so that the node C becomes the pumping voltage VPP1 level.

When the output of the inverter IV5 becomes high, the pumping voltage VPP1 level rises according to the charging voltages of the plurality of ferroelectric capacitors FC6 to FC8 so that the voltage level of the node C becomes the pumping voltage VPP2 level. Here, the level of the pumping voltage VPP2 represents the level of the pumping voltage VPP1 + threshold voltage (threshold voltage Vt of the PMOS transistor P7).

As a result, the word line WL and the plate line PL rise to the pumping voltage VPP1 + Vt level higher than the target voltage, and the voltage level of the bit line BL rises to increase the pumping voltage VPP1 + Vt level to reinforce the threshold voltage of the memory cell. The pumping voltage VPP2 having is supplied to the memory cell.

Thereafter, the voltage level of the output terminal of the pumping voltage VPP2 is maintained at the pumping voltage VPP1 + Vt level when entering the t3 section for restoring the data '0'. At this time, the word line WL, the bit line BL and the plate line PL of the memory cell maintain the same level as the voltage level of the output terminal.

Subsequently, the voltage level of the plate line PL transitions to the low level when entering the t4 section for restoring the data '1'. Subsequently, when the voltage level of the word line WL transitions low when the t5 period enters, the voltage level of the bit line BL maintains the ground voltage VSS level.

The present invention minimizes power consumption by operating the analog processing unit 100 and the digital processing unit 200 using the smallest power supply voltage VDD, and the pumping voltage for the operation of the memory unit 300 includes two pumping voltages. The generator 160 and the step-pulse pumping unit 310 are supplied.

Here, the pumping voltage VPP1 generated by the pumping voltage generator 160 is generated using the clock CLK and is supplied to a peripheral circuit of the memory unit 300. The pumping voltage VPP2 generated by the step-pulse pumping unit 310 is supplied to a circuit and a memory cell necessary for driving the memory cell. Accordingly, the embodiment of the present invention allows the pumping voltage required for the operation of the memory cell to be generated only when driving is required, thereby minimizing power consumption in the memory unit 300.

Claims (20)

A memory unit for reading or writing data;
A pumping voltage generator for detecting a level of a power supply voltage applied to the RFID and outputting a first pumping voltage higher than the power supply voltage by pumping the power supply voltage in response to a clock; And
And a step-pulse pumping unit configured to supply the second pumping voltage higher than the first pumping voltage to the memory unit by pumping the first pumping voltage during the operation of the memory unit.
And the step-pulse pumping unit is included in the memory unit. Claim 2 has been abandoned due to the setting registration fee. The RFID device of claim 1, further comprising a clock generator configured to generate the clock according to the power supply voltage and output the clock to the pumping voltage generator. Claim 3 has been abandoned due to the setting registration fee. The method of claim 1, wherein the pumping voltage generating unit
A driving unit driving and outputting a detection voltage according to the clock;
A ferroelectric capacitor configured to raise the first node to a level higher than the power supply voltage according to the output of the driver;
A charging unit configured to selectively charge the first node to the power supply voltage level according to the output of the driving unit;
A rectifier for rectifying the voltage applied from the first node;
A pumping voltage detector configured to control the detection voltage by sensing the voltage level of the first node; And
And a pumping voltage output unit configured to charge the output voltage of the rectifying unit to output the first pumping voltage. Claim 4 has been abandoned due to the setting registration fee. The method of claim 3, wherein the driving unit
An input driver driving the detection voltage according to the clock; And
And a driving device for supplying the power supply voltage or the ground voltage to the charging unit according to the output of the input driver. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 3, wherein the ferroelectric capacitor portion
And a plurality of ferroelectric capacitors connected in parallel between the first node and the driver. Claim 6 has been abandoned due to the setting registration fee. The method of claim 3, wherein the charging unit
And a PMOS transistor connected between a power supply voltage terminal and the first node and having a gate terminal connected to an output terminal of the driving unit. Claim 7 has been abandoned due to the setting registration fee. The method of claim 3, wherein the pumping voltage detection unit
And outputting the detection voltage at a high level when the first pumping voltage is less than or equal to a predetermined target level, and outputting the detection voltage at a low level when the first pumping voltage is greater than or equal to the target level. delete delete delete delete Claim 12 is abandoned in setting registration fee. The RFID device of claim 3, wherein the pumping voltage output unit comprises a plurality of ferroelectric capacitors connected in parallel between an output terminal of the rectifying unit and a ground voltage terminal. Claim 13 was abandoned upon payment of a registration fee. The method of claim 1, wherein the step-pulse pumping unit
A driving unit driving a pumping enable signal activated during operation of the memory unit;
A ferroelectric capacitor configured to raise the second node to a level higher than the first pumping voltage according to the output of the driver; And
And a charging unit configured to charge the second node to the second pumping voltage level when the pumping enable signal is inactivated. Claim 14 has been abandoned due to the setting registration fee. The method of claim 13, wherein the driving unit
An input driver to drive the pumping enable signal; And
And a driving device for supplying the first pumping voltage or the ground voltage to the charging unit according to the output of the input driver. Claim 15 is abandoned in the setting registration fee payment. The method of claim 13, wherein the ferroelectric capacitor portion
And a plurality of ferroelectric capacitors connected in parallel between the second node and the driver. Claim 16 has been abandoned due to the setting registration fee. The method of claim 13, wherein the charging unit
And a PMOS transistor connected between an application end of the first pumping voltage and the second node and a gate terminal connected to an output end of the driving unit. delete delete Claim 19 is abandoned in setting registration fee. The method of claim 1,
An analog processor for receiving a wireless signal and outputting an operation command signal; And
And a digital processing unit generating and outputting an address and an operation control signal according to the operation command signal applied from the analog processing unit, and outputting a corresponding response signal to the analog processing unit. Claim 20 has been abandoned due to the setting registration fee. The RFID device of claim 19, wherein the pumping voltage generator is included in the analog processor.

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