KR100874983B1 - Tag chip and its driving method - Google Patents

Abstract

The present invention relates to a tag chip capable of stably supplying driving power to prevent current consumption and malfunction of a circuit. The present invention relates to a power generation unit for generating driving power by receiving a carrier wave through an antenna. The power is supplied through the switch, the rectifying unit rectifies the driving power and supplies it to the driving circuit unit, and compares the magnitude of the driving power from the driving power generating unit with a preset reference voltage, and according to the comparison result, the switch It is configured to include a switch control unit for controlling the on / off of.

Description

Tag chip and method for driving the same

1 is a schematic block diagram of a conventional passive tag chip

2 is a block diagram of a tag chip according to an embodiment of the present invention.

3 is a view showing a power supply of FIG.

4 is a diagram illustrating a specific circuit configuration of the switch controller of FIG. 2.

* Explanation of symbols on the main parts of the drawings

201: driving power generation unit 202: rectifier

203: switch 204: switching control unit

299: power supply unit 241: demodulation unit

242: clock generator 243: reset unit

244 control unit 250 storage unit

260: data transmission unit 233: antenna

221: limiter 222: antistatic circuit

C1: first capacitor C2: second capacitor

279: drive circuit portion 281: carrier wave

CLK: Clock pulse RS: Reset signal

Data: Data Signal VDD: Driving Power

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a passive tag chip used in an RFID system, and more particularly, to a tag chip and a driving method thereof capable of stably supplying driving power to prevent current consumption and malfunction of a circuit.

In recent years, the RFID (Radio Frequency IDentification) system which automatically recognizes an object and even authenticates and pays for the object has been in the spotlight. RFID, that is, wireless recognition refers to a system that can transmit and receive various data in a wireless manner using a predetermined frequency band. In the case of magnetic and barcodes, a specific external display is required and the recognition rate gradually decreases over time due to damage or damage, whereas an RFID system can overcome such disadvantages. RFID systems are emerging as new solutions, such as those used in various automation projects, distribution, livestock management, access control, time and attendance, logistics, and parking management. Specifically, for example, prepaid / postpaid, including credit / debit cards. It can be used on buses, subway cards, parking lot access cards, department store cards, manufacturing processes on conveyor belts, postal delivery systems, identification tags that record animal information, and the like. In an object recognition system, an object containing object recognition information is called a tag, and a device that reads the information recorded on the tag is called an identifier (e.g., a magnetic strip or a barcode display is attached to the tag). Magnetic reader or bar code reader is a reader. In the related art, a magnetic system or a bar code system is mainly used for object recognition. However, magnetic systems (e.g. card reader systems) read through the data recorded on the magnetic strips of the card as frictional contact, which causes damage to the magnetic strips of the card and shortens the life of the card, as well as the card reader. Scanning too late or too fast out of the reference speed when passing the card to the card causes inconvenience that a card data read error occurs, and the magnetic strip has a problem that its magnetization weakens over time. In addition, the bar code system also has a problem that the bar code must exist on the surface of the object, thereby preventing the object recognition when the bar code is damaged. This is because the semiconductor laser emitted from the barcode reader can be recognized by being absorbed / reflected by the black / white band of the barcode.

In addition, the magnetic or barcode system has a problem that the communication speed is also very slow, it is not suitable when a fast recognition speed is required, such as a bus / subway card.

RFID (radio recognition) system has emerged as a system that can solve the problems of the magnetic or barcode system as described above. The RFID system can be viewed as a combination of a tag + identified object having a tag chip embedded therein and an external identifier that can recognize the tag chip externally. The RFID system is an electronic object identification system using radio frequency, and includes an active RFID in which a power source exists inside an identified object and a passive RFID which receives magnetic energy from the outside and uses the same as a power source.

That is, the tag chip used in the passive RFID system generates a driving power by receiving a carrier wave from the reader.

1 is a schematic block diagram of a conventional passive tag chip.

In the conventional passive tag chip, as illustrated in FIG. 1, the driving tag generator 101 generates a driving power by receiving a carrier signal from a reader, and the driving power from the driving power generator 101. It includes a rectifying unit for rectifying.

The size of the carrier signal varies according to the distance between the reader and the tag chip or the power of the reader. That is, as the distance between the reader and the tag chip increases, and the power of the reader decreases, the size of the carrier signal decreases.

When the size of the carrier signal is reduced, the size of the driving power generated inside the tag chip is also reduced. Of course, the driving power generation unit 101 boosts the magnitude of the driving power in a predetermined order, but the smaller the magnitude of the carrier signal, the longer it takes to boost the magnitude of the driving power. Therefore, the rectifier 102 and the circuits connected to the rear end of the rectifier 102 consume a lot of current during the time of raising the driving power to a constant level of voltage.

In addition, since the driving power is supplied to the circuits connected to the rectifier 102 and the rear end of the rectifier 102 in a state where the driving power is not fully boosted, the circuits supplied with the driving power may cause a malfunction.

The present invention has been made to solve the above problems, the switching element is provided between the driving power generation unit and the rectifier, and when the driving power generated from the driving power generation unit is boosted to a predetermined level turn the switching element The object of the present invention is to provide a tag chip and a driving method thereof, which can supply stable driving power by turning on.

The tag chip according to the present invention for achieving the above object, the power generation unit for generating a driving power by receiving a carrier wave through an antenna receives the drive power from the power generation unit through a switch, And a switch controller for rectifying and supplying a driving circuit to the driving circuit unit, and comparing the magnitude of the driving power source from the power generating unit with a preset reference voltage, and controlling on / off of the switch according to the comparison result. It is characterized by.

In addition, the tag chip driving method according to the present invention for achieving the above object, the power generation unit for generating a driving power by receiving a carrier wave through the antenna, and driving the rectified driving power from the power generation unit A method of driving a tag chip including a rectifying unit for supplying a circuit unit, the method comprising: comparing a magnitude of a driving power source from the power generating unit and a predetermined reference voltage; Characterized in that it comprises a step of determining whether or not to supply.

Hereinafter, a tag chip according to an embodiment of the present invention will be described in detail with reference to the accompanying drawings.

2 is a block diagram of a tag chip according to an embodiment of the present invention, Figure 3 is a view showing the power supply of FIG.

As shown in FIG. 2, the tag chip according to an embodiment of the present invention includes a power supply unit 299 for receiving a carrier signal 281 (ultra-high frequency signal of 900 MHz or more) from a reader and generating a driving power source VDD; A driving circuit unit 279 operated by receiving power from the power supply unit 299, a storage unit 250 for storing data, and a data transmission unit 260 for transmitting a data signal to the reader. Include.

The reader carries power and instructions (data signals) necessary for the tag chip to a carrier signal 281, and the power supply unit 299 provided in the tag chip transmits a power signal included in the carrier signal 281. To generate the driving power source VDD required for the driving circuit unit 279.

The power supply unit 299 receives the driving power generation unit 201 generating the driving power Vddp and the driving power supply Vddp from the driving power generation unit 201 through the switch 203. The rectifier 202 regulating the driving power Vddp and supplying it to the driving circuit unit 279 and the magnitude of the driving power Vddp and the reference voltage from the driving power generating unit 201 are determined. And a switch controller 204 for controlling the on / off of the switch 203 according to the determination result.

The rectifier 202 generates a reference voltage using the driving power supply Vddp supplied thereto, in addition to rectifying the driving power supply Vddp. The generated reference voltage is supplied to a demodulator 241 (demodulator) provided in the driving circuit unit 279.

As shown in FIG. 3, the switch 203 preferably uses a P-type metal oxide semiconductor (MOS) switching element.

In addition, the tag chip according to the embodiment of the present invention further includes a limiter 221, an electrostatic protection circuit 222, and a first capacitor C1.

The limiter 221 may set the maximum magnitude of the driving power source Vd such that the driving power source Vddp from the driving power generation unit 201 does not exceed the maximum allowable voltage range of the rectifying unit 202. Restrict.

The static electricity protection circuit 222 blocks static electricity from flowing into the driving power generator 201 from the outside.

The first capacitor C1 stores the driving power Vddp from the driving power generation unit 201.

The driving power generation unit 201 is a DC power supply having a voltage of about 2 [V] or more with an AC level signal having a peak to peak voltage of about 0.5 [V] supplied from the reader. It converts to (Vddp), and supplies the drive power supply Vddp of this DC level to the rectification part 202.

That is, the driving power generation unit 201 generates the driving power Vddp by converting the signal to a DC level and boosting the voltage level of the converted signal.

For this operation, the driving power generation unit 201 includes a voltage pumping circuit configured with a Schottky diode.

In addition, the driving power generation unit 201 generates a data signal by level shifting the signal of the AC level supplied from the reader, and supplies the data signal to the demodulation unit 241 provided in the driving circuit unit 279. do.

The driving circuit unit 279 includes a controller 244, a demodulator 241, a clock generator 242, and a reset unit 243 (Power On Reset).

The driving power source VDD generated from the rectifier 202 is commonly supplied to the controller 244, the demodulator 241, the clock generator 242, the reset unit 243, and the storage unit 250. It is used as a power source for operating the above-listed components.

The reference voltage generated from the rectifier 202 and the data signal generated from the driving power generator 201 are supplied to the demodulator 241. The demodulator 241 demodulates the data signal into a digital data signal. That is, the data signal is demodulated into a digital signal having a high logic voltage and a low logic voltage. The demodulated digital data signal is supplied to the control unit 244.

The demodulator 241 generates the digital data signal by adding a reference voltage from the driving power generator 201 to the data signal to perform such an operation.

The clock generator 242 generates a clock pulse CLK in response to the driving power supply VDD from the rectifier 202, and supplies the clock pulse CLK to the controller 244.

The controller 244 samples the digital data signal using the clock pulse CLK. The controller 244 reads the sampled digital data signal to find out which command the digital signal is to perform, and generates a control signal for performing this command.

The control unit 244 transmits a data signal to the reader according to the command, and controls the transmission timing of the data signal.

In addition, the controller 244 stores the sampled data signal in the storage unit 250 or reads the data signal stored in the storage unit 250 to perform a necessary operation.

The reset unit 243 generates a reset signal RS whenever the driving power supply VDD is supplied from the rectifier 202, and supplies the reset signal RS to the controller 244 to supply the reset signal RS. ) Register is initialized.

The data transmitter 260 is controlled according to a control signal from the controller 244 to transmit a data signal requested by the reader to the reader.

The data transmitter 260 adjusts an impedance (impedance between the antenna 233 and the reader period) according to a control signal from the controller 244, thereby transmitting a data signal to be transmitted by the controller 244 to a carrier signal. (281) to the reader. The reader demodulates the carrier signal 281 and restores the original data signal.

The reader alternately generates and transmits a power signal and a command signal to the tag chip in a first transmission period, and generates and transmits only the power signal to the tag chip in a second transmission period. The first transmission period and the second transmission period alternate.

Accordingly, in the first transmission period, the tag chip receives the required power to generate driving power VDD, and generates driving power VDD for driving each of the above-described components. Also, in the first transmission period, the tag chip receives a data signal from the reader and reads the data signal to perform a command from the reader.

In the second transmission period, the tag chip transmits a necessary data signal to the reader according to a command from the reader. In this period, the reader transmits only a power signal to the tag chip.

The storage unit 250 is an electrically erasable and programmable read only memory (EEPROM), and the storage unit 250 receives a driving power supply VDD from the rectifying unit 202. On the other hand, a voltage of at least 10 [V] is required to perform an operation for writing data to the storage unit 250. This voltage uses the drive power Vddp output from the drive power generation unit 201, that is, not rectified.

In the embodiment of the present invention configured as described above, the switch control unit 204 will be described in more detail as follows.

4 is a diagram illustrating a specific circuit configuration of the switch controller of FIG. 2.

As shown in FIG. 4, the switch controller 204 detects the size of the driving power supply Vddp largely and outputs a turn-on signal only when the driving power supply Vddp maintains a constant size. And a timing controller 402 for controlling the output timing of the turn-on signal output from the level detector 401.

The level detector 401 includes an input switching element nTr_in in a reverse bias state, a first inverter 441 connected to a source terminal of the input switching element nTr_in, and an output terminal of the first inverter 441. And a third inverter 443 connected to an output terminal of the second inverter 442.

Here, the input switching element nTr_in is an NMOS switching element, and its gate terminal and source terminal are connected together to the first node n1, and the drain terminal has a driving power source (20) of the driving power generation unit 201. Vddp) is supplied.

The first inverter 441 includes a first PMOS switching device pTr_1 and a first NMOS switching device nTr_1.

The gate terminal of the first PMOS switching element pTr_1 is connected to the first node n1, and the source terminal is connected to an output line for outputting driving power Vddp from the driving power generator 201. And the drain terminal is connected to the drain terminal of the first NMOS switching element nTr_1.

The gate terminal of the first NMOS switching element nTr_1 is connected to the first node n1, the source terminal is connected to the ground terminal, and the drain terminal is connected to the drain terminal of the first PMOS switching element pTr_1. Connected.

The second inverter 442 includes a second PMOS switching device pTr_2 and a second NMOS switching device nTr_2.

The gate terminal of the second PMOS switching element pTr_2 is connected to the source terminal of the first PMOS, and the source terminal is connected to an output line for outputting driving power Vddp from the driving power generation unit 201. The drain terminal is connected to the drain terminal of the second NMOS switching device nTr_2.

The gate terminal of the second NMOS switching element nTr_2 is connected to the source terminal of the input switching element nTr_in, the source terminal is connected to the ground terminal, and the drain terminal of the second PMOS switching element pTr_2 It is connected to the drain terminal.

The third inverter 443 includes a third PMOS switching element pTr_3 and a third NMOS switching element nTr_3.

A gate terminal of the third PMOS switching element pTr_3 is connected to a source terminal of the second PMOS, and a source terminal of the third PMOS switching device pTr_3 is connected to an output line for outputting driving power Vddp from the driving power generator 201. And the drain terminal is connected to the drain terminal of the third NMOS switching element nTr_3.

The gate terminal of the third NMOS switching element nTr_3 is connected to the source terminal of the input switching element nTr_in, the source terminal is connected to the ground terminal, and the drain terminal of the third PMOS switching element pTr_3. It is connected to the drain terminal.

The drain terminal of the third PMOS is connected to the gate terminal of the switch 203. The switch 203 is a PMOS switching element.

The timing controller 402 is turned on or turned off according to the logic state of the first node n1, and the fourth PMOS switching device supplies the driving power supply Vddp to the second node n2 at turn-on time. fifth to ninth turned on or off according to a logic state of pTr_4 and the second node n2, and supplying the driving power Vddp to the first node n1 at turn-on; PMOS switching elements pTr_5, pTr_6, pTr_7, pTr_8, pTr_9 and the second node n2 are turned on or off according to the logic state of the PMOS switching elements pTr_5, pTr_6, pTr_8, pTr_9, and the second node n2 VSS) is turned on or off according to the logic state of the fourth and fifth NMOS switching elements nTr_5 and the second node n2, and is turned on from the driving power generator 201. A sixth NMOS switching element nTr_6 for supplying a driving power supply Vddp to the second node n2 and a seventh NMOS switching element nTr for supplying its threshold voltage to the second node n2 _7).

A third capacitor C3 is connected between the first node n1 and the ground terminal, and a fourth capacitor C4 is connected between the second node n2 and the terminal supplied with the driving power source Vddp.

The operation of the switch controller 204 according to the embodiment of the present invention configured as described above will be described in detail as follows.

The voltage of the first node n1 corresponds to the difference voltage between the voltage of the driving power source Vddp and the threshold voltage of the input switching element nTr_in. This is expressed as the following equation.

V (n1) = Vddp-Vth (NTr_in)

V (n1) represents the voltage of the first node n1, and Vth (Tr_in) represents the threshold voltage of the input switching element nTr_in.

 At this time, assuming that the voltage of the driving power source Vddp is 0, since the first to third inverters 443 do not operate, there is no output from the third inverter 443.

Thus, the switch 203 remains turned off. Accordingly, the drive power Vddp output from the drive power generator 201 is not supplied to the rectifier 202.

On the other hand, when the voltage of the driving power supply (Vddp) gradually increases to have a constant value, the first to third inverters 441, 442, and 443 operate to output a turn-on signal.

That is, when the voltage of the first node n1 has a value equal to or greater than the threshold voltage of the first NMOS switching element nTr_1 included in the first inverter 441, the final output from the third inverter 443 is 0. Denotes a voltage (a turn-on signal, that is, a ground voltage VSS).

In other words, when the voltage of the first node n1 satisfies the following equation, a turn-on signal is output.

Vddp-Vth (NTr_in) Vth (NTr_1)

Here, Vth (NTr_1) represents the threshold voltage of the first NMOS switching device nTr_1.

As can be seen from the second equation, the voltage of the driving power source Vddp is greater than the sum of the threshold voltages (sum of the threshold voltage of the input switching element nTr_in and the threshold voltage of the first NMOS switching element nTr_1). If greater than or equal to, the switch controller 204 outputs the ground voltage VSS as a turn-on signal.

When the voltage of the driving power source Vddp satisfying the second equation is supplied to the first node n1, the first inverter 441 outputs a low state signal (ground voltage VSS) to generate a first voltage. 2 is supplied to the inverter 442. Then, the second inverter 442 outputs a high state signal (driving power source Vddp) in response to the low state signal and supplies it to the third inverter 443. Then, the third inverter 443 outputs a low state signal in response to the high state signal. The low state signal is the turn-on signal described above.

This turn-on signal is supplied to the gate terminal of the switch 203 to turn on the switch 203. Then, the driving power source Vddp from the driving power generation unit 201 is supplied to the rectifying unit 202 through the turned-on switch 203.

As such, the switch controller 204 turns on the switch 203 when the voltage of the driving power source Vddp is greater than or equal to the sum of the threshold voltages (reference voltage), and the driving power source Vddp is turned on. The switch 203 is turned off when the voltage at is less than the sum of the threshold voltages (reference voltages).

By adjusting the threshold voltage of the input switching device nTr_in and the threshold voltage of the first NNOS switching device, the magnitude of the driving power Vddp to be supplied to the rectifier 202 may be controlled.

On the other hand, the fourth PMOS switching device pTr_4 of the timing controller 402 is turned on when the driving power supply Vddp does not rise above a predetermined value, thereby turning on the driving power supply Vddp to the second node n2. To feed.

At this time, the second node n2 is gradually charged by the fourth capacitor C4. The fourth and fifth NMOS switching elements nTr_5 having gate terminals connected to the charged second node n2 are turned on. The ground voltage VSS is supplied to the second node n2 through the turned-on fourth and fifth NMOS switching elements nTr_5.

At this time, the second node n2 is not discharged to the ground voltage VSS by the seventh NMOS switching element nTr_7, but is maintained at the threshold voltage of the seventh NMOS switching element nTr_7.

In this state, when the driving power supply Vddp gradually increases to reach a predetermined value, the fifth to ninth PMOS switching devices pTr_5, pTr_6, pTr_7, and pTr_8 having gate terminals connected to the second node n2. , pTr_9) are all turned on.

In this case, the turned-on fifth to ninth PMOS switching devices pTr_5, pTr_6, pTr_7, pTr_8, and pTr_9 serve as resistances, and are determined by time constants determined by the switching elements and the third capacitor C3. The time at which the voltage value of the first node n1 is supplied to the first inverter 441 is determined.

The output time can be adjusted by adjusting the number of the switching elements pTr_5, pTr_6, pTr_7, pTr_8, pTr_9 and the capacitance of the capacitor C3.

The present invention described above is not limited to the above-described embodiment and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

The tag chip according to the present invention as described above has the following effects.

The tag chip according to the embodiment of the present invention includes a switch installed between the driving power generation unit and the rectifier and a switch controller for controlling the switch.

The tag chip according to the exemplary embodiment of the present invention may supply stable driving power by turning on a switch when the driving power generated from the driving power generation unit is boosted to a predetermined level.

Claims (22)

A driving power generation unit receiving a carrier through an antenna and including a boosting circuit configured to generate driving power by boosting a power signal included in the carrier; A rectifying unit receiving the driving power from the driving power generating unit through a switch, rectifying the driving power and supplying the driving power to the driving circuit unit; And, And a switch controller for comparing the magnitude of the driving power from the driving power generation unit with a predetermined reference voltage and controlling the on / off of the switch according to the comparison result. Claim 2 was abandoned when the setup registration fee was paid. The method of claim 1, The carrier tag is characterized in that it comprises a power signal and a data signal for the operation of the driving circuit unit. delete Claim 4 was abandoned when the registration fee was paid. The method of claim 1, The boosting circuit is a tag chip, characterized in that the pumping circuit consisting of a Schottky diode. Claim 5 was abandoned upon payment of a set-up fee. The method of claim 1, And a limiter for controlling the driving power from the driving power generator not to exceed a predetermined size. Claim 6 was abandoned when the registration fee was paid. The method of claim 1, The tag chip, characterized in that it further comprises an antistatic circuit for blocking the static electricity flow into the rectifier. Claim 7 was abandoned upon payment of a set-up fee. The method of claim 1, And a capacitor for storing the driving power from the driving power generation unit. The method of claim 1, And a capacitor for storing the driving power rectified from the rectifier. The method of claim 1, The driving circuit unit, A demodulator for restoring a data signal included in the carrier; A clock generator for generating a clock pulse; A controller which receives a data signal from the demodulator and a clock pulse from the clock generator, reads the data signal, and executes a command according to the read result; A data transmitter for transmitting data to a reader under the control of the controller; And a power-on-reset unit for generating a reset signal each time a driving power is supplied from the rectifier unit, and supplying the reset signal to the controller to initialize the register of the controller. The method of claim 9, And a storage unit for storing the data signal. The method of claim 10, The storage chip is characterized in that the EEPROM (electrically erasable and programmable read only memory). The method of claim 1, The switch control unit Turn on the switch when the driving power is greater than or equal to the reference voltage; And, And the switch is turned off when the driving power is lower than the reference voltage. The method of claim 1, The switch control unit, A level detector detecting a magnitude of the driving power and outputting a turn-on signal only when the driving power is maintained at a predetermined size; And, And a timing controller configured to control an output timing of the turn-on signal output from the level detector. The method of claim 13, The level detection unit, An input NMOS switching element having a drain terminal to which driving power from the driving power generation unit is input, a gate terminal and a source terminal connected together to a first node; A first inverter connected to the first node and supplied with the driving power source and a ground voltage; A second inverter connected to an output terminal of the first inverter and receiving the driving power and a ground voltage; A third inverter connected to the output terminal of the second inverter and receiving the driving power and the ground voltage; And, And a capacitor connected between the first node and a ground terminal for supplying the ground voltage. The method of claim 14, The first inverter, A first NMOS switching element that is turned on or turned off according to a logic state of the first node, and outputs a ground voltage to the second inverter when turned on; And, And a first PMOS switching device which is turned on or turned off according to a logic state of the first node, and which outputs the driving power and supplies the driving power to a second inverter when the first node is turned on. The method of claim 15, The reference chip has a magnitude corresponding to the sum of the threshold voltage of the input NMOS switching device and the threshold voltage of the first NMOS switching device. The method of claim 15, The second inverter, A second NMOS switching element which is turned on or turned off according to a logic state of the output from the first inverter and outputs a ground voltage to the third inverter when turned on; And, And a second PMOS switching device which is turned on or turned off according to the logic state of the output from the first inverter, and outputs the driving power to the third inverter when turned on. . The method of claim 17, The third inverter, A third NMOS switching element which is turned on or turned off according to a logic state of the output from the second inverter, and outputs a ground voltage to the switch when turned on; And, And a third PMOS switching device which is turned on or turned off according to a logic state of the output from the first inverter, and outputs the driving power to the switch when turned on. Claim 19 was abandoned upon payment of a registration fee. The method of claim 18, The tag chip, characterized in that the output terminal of the third inverter is connected to the gate terminal of the switch, the switch element is a PMOS switching element. The method of claim 14, The timing controller, A fourth PMOS switching device which is turned on or turned off according to a logic state of the first node and supplies the driving power to a second node when turned on; A fifth to ninth PMOS switching device which is turned on or turned off according to a logic state of the second node and supplies the driving power to the first node when turned on; Fourth and fifth NMOS switching devices that are turned on or turned off according to a logic state of the second node, and discharge the second node to a ground voltage when the second node is turned on; A sixth NMOS switching device which is turned on or turned off according to a logic state of the second node, and supplies driving power from the driving power generation unit to the second node when turned on; A seventh NMOS switching element supplying its own threshold voltage to the second node; And, And a second capacitor connected between the second node and the terminal to which the driving power is supplied. In the driving method of a tag chip comprising a driving power generation unit receiving a carrier through an antenna to generate driving power, and a rectifying unit for rectifying the driving power from the driving power generation unit to supply to the driving circuit, Generating, by the driving power generation unit, the driving power by boosting a power signal included in the carrier; Comparing the magnitude of the driving power from the driving power generation unit with a preset reference voltage; And, And determining whether or not to supply the driving power to the rectifying unit according to the comparison result. The method of claim 21, Supplying the driving power to the rectifying unit when the driving power is greater than or equal to a reference voltage; And, And when the driving power is lower than a reference voltage, supplying the driving power to the rectifier.

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