KR100762257B1 - Device and mothed for reading tari length for tag chip - Google Patents

Abstract

A device and a method for reading a TARI length for a tag chip are provided to restrict clock signal usage of a high frequency and reduce power consumption by performing 1/2 division or 1/3 division or 1/6 division of a main clock signal for reading 1 TARI length and associating the divided clock signal before counting the TARI length, and reduce counter capacity by limiting a counter for counting the clock signals to 3 bit and 2 bit. A variable clock generator(101) generates a clock signal having a constant frequency if being enable, performs 1/2 division or 1/3 division or 1/6 division of the clock signal according to a frequency adjust signal and then outputs the divided frequency. A 3 bit counter(102) counts and outputs the clock signal outputted from the variable clock generator, and outputs a carry signal if the counted number becomes 8. A 2 bit counter(103) counts and outputs the carry signal outputted from the 3 bit counter. A preamble detection controller(104) outputs the frequency adjust signal to the variable clock generator, enables/resets the 3bit counter and the 2 bit counter, and reads a TARI length by receiving a count signal outputted from the 3bit counter and the 2 bit counter.

Description

Device and mothed for reading TARI length for tag chip}

1 is a block diagram of a conventional tag chip block

2 is a symbol for data " 0 " and " 1 " set in an international standard (ISO Type-C) for a tag chip in a general UHF band.

3 is a timing diagram of a preamble signal transmitted from a general reader to a tag chip.

4 is a frequency table that a typical tag chip must satisfy when transmitting data to a reader.

5 is a block diagram of a tag length reading device for a tag chip according to the present invention.

6 is a detailed circuit diagram of a variable clock generator of a tag length reading device for a tag chip according to the present invention.

7 is a timing diagram illustrating a method of varying (dividing) a clock frequency of a clock generator for a tag chip of a UHF band according to the present invention.

* Explanation of symbols on the main parts of drawings *

101: variable clock generator 102: 3-bit counter

103: 2-bit counter 104: preamble detection control unit

111-115: Inverter 116-118: Switch

C1-C3: Capacitor

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a tag (TAG) chip used in an RFID (Radio Frequency IDentification) system, and more particularly, in detecting a delimiter and a tar in a preamble signal transmitted from a reader to a tag chip. The present invention relates to a tag length reading device and a reading method for a tag chip which divides a frequency of a clock signal for detecting a length of a signal.

In recent years, the RFID (Radio Frequency IDentification) system, which automatically recognizes an object and even authenticates and pays an object, has been in the spotlight. The RFID system refers to a system that can transmit and receive various data in a wireless manner using a predetermined frequency band. In the case of magnetic and barcodes, a specific external display is required and the recognition rate gradually decreases with time due to damage or damage, whereas the RFID system can overcome such disadvantages.

The RFID system is rapidly emerging as a new solution, which is used in various automation business, distribution business, livestock management, access control, time and attendance management, logistics management, parking management, etc. Specifically, for example, prepaid / post-payment including credit / debit card It can be used for buses, subway cards, parking cards, department store cards, manufacturing processes on conveyor belts, postal delivery systems, identification tags that record animal information.

In the object recognition system, an object containing object recognition information is called a tag, and a device that reads the information recorded in the tag is called an identifier. For example, a magnetic strip or barcode representation corresponds to a tag and a magnetic reader or barcode reader corresponds to a recognizer.

In the past, a magnetic system or a bar code system was mainly used for object recognition. However, magnetic systems (e.g. card reader systems) read through the data recorded on the magnetic strip of the card as a frictional contact, which not only shortens the life of the card, but also damages the magnetic strip of the card. Scanning too late or too fast out of the reference speed when passing the card causes inconvenience that card data read error occurs, and the magnetic strip has weakened its magnetization over time. In addition, the bar code system also has a problem that the bar code must exist on the surface of the object, thereby preventing the object recognition when the bar code is damaged. This is because the semiconductor laser emitted from the barcode reader can be recognized by being absorbed / reflected by the black / white band of the barcode.

In addition, the magnetic or bar code system has a problem that the communication speed is also very slow, which is not suitable when a fast recognition speed is required, such as a bus / subway card.

RFID (radio recognition) system has emerged as a system that can solve the problems of the magnetic or barcode system as described above. The RFID system can be seen as a combination of a tag + identified object with a built-in tag chip and an external identifier that can recognize the tag chip from the outside. The RFID system is an electronic object identification system using radio frequency, and includes an active RFID in which a power source exists inside an identified object and a passive RFID which receives magnetic energy from the outside and uses the same as a power source.

That is, the tag chip used in the passive RFID system generates a driving power by receiving a carrier wave from the reader.

1 is a block diagram of a conventional tag chip block.

As shown in FIG. 1, a typical tag chip includes a power supply unit 299 that receives a carrier signal 281 (an ultra-high frequency signal of 900 MHz or more) from a reader and generates a driving power supply VDD, and the power supply unit 299. The driving circuit unit 279 operates by receiving power from the power supply, a storage unit 250 for storing data, and a data transmission unit 260 for transmitting a data signal to the reader.

The reader carries power and instructions (data signals) necessary for the tag chip to a carrier signal 281, and the power supply unit 299 provided in the tag chip transmits a power signal included in the carrier signal 281. To generate the driving power source VDD required for the driving circuit unit 279.

The power supply unit 299 rectifies and supplies the driving power generation unit 201 for generating driving power Vddp and the driving power supply Vddp from the driving power generation unit 201 to the driving circuit unit 279. The rectifier 202 includes a rectifier.

The rectifier 202 generates a reference voltage using the driving power supply Vddp supplied thereto, in addition to rectifying the driving power supply Vddp. The generated reference voltage is supplied to a demodulator 241 (demodulator) provided in the driving circuit unit 279.

In addition, the conventional tag chip further includes a limiter 221, an electrostatic protection circuit 222, and a first capacitor C1.

The limiter 221 may set the maximum magnitude of the driving power source Vd such that the driving power source Vddp from the driving power generation unit 201 does not exceed the maximum allowable voltage range of the rectifying unit 202. Restrict.

The static electricity protection circuit 222 blocks static electricity from flowing into the driving power generator 201 from the outside.

The first capacitor C1 stores the driving power Vddp from the driving power generation unit 201.

The driving power generation unit 201 is a DC power supply having a voltage of about 2 [V] or more with an AC level signal having a peak to peak voltage of about 0.5 [V] supplied from the reader. It converts to (Vddp), and supplies the drive power supply Vddp of this DC level to the rectification part 202.

That is, the driving power generation unit 201 generates the driving power Vddp by converting the signal to a DC level and boosting the voltage level of the converted signal.

For this operation, the driving power generation unit 201 includes a voltage pumping circuit configured with a Schottky diode.

In addition, the driving power generation unit 201 generates a data signal by level shifting the signal of the AC level supplied from the reader, and supplies the data signal to the demodulation unit 241 provided in the driving circuit unit 279. do.

The driving circuit unit 279 includes a controller 244, a demodulator 241, a clock generator 242, and a reset unit 243 (Power On Reset).

The driving power source VDD generated from the rectifier 202 is commonly supplied to the controller 244, the demodulator 241, the clock generator 242, the reset unit 243, and the storage unit 250. It is used as a power source for operating the above-listed components.

The reference voltage generated from the rectifier 202 and the data signal generated from the driving power generator 201 are supplied to the demodulator 241. The demodulator 241 demodulates the data signal into a digital data signal. That is, the data signal is demodulated into a digital signal having a high logic voltage and a low logic voltage. The demodulated digital data signal is supplied to the control unit 244.

The demodulator 241 generates the digital data signal by adding a reference voltage from the rectifier 202 to the data signal to perform this operation.

The clock generator 242 generates a clock pulse CLK in response to the driving power supply VDD from the rectifier 202, and supplies the clock pulse CLK to the controller 244.

The controller 244 samples the digital data signal using the clock pulse CLK. The controller 244 reads the sampled digital data signal to find out which command the digital signal is to perform, and generates a control signal for performing this command.

The control unit 244 transmits a data signal to the reader according to the command, and controls the transmission timing of the data signal.

In addition, the controller 244 stores the sampled data signal in the storage unit 250 or reads the data signal stored in the storage unit 250 to perform a necessary operation.

The reset unit 243 generates a reset signal RS whenever the driving power supply VDD is supplied from the rectifier 202, and supplies the reset signal RS to the controller 244 to supply the reset signal RS. ) Register is initialized.

The data transmitter 260 is controlled according to a control signal from the controller 244 to transmit a data signal requested by the reader to the reader.

The data transmitter 260 adjusts an impedance (impedance between the antenna 233 and the reader period) according to a control signal from the controller 244, thereby transmitting a data signal to be transmitted by the controller 244 to a carrier signal. (281) to the reader. The reader demodulates the carrier signal 281 and restores the original data signal.

The reader alternately generates and transmits a power signal and a command signal to the tag chip in a first transmission period, and generates and transmits only the power signal to the tag chip in a second transmission period. The first transmission period and the second transmission period alternate.

Accordingly, in the first transmission period, the tag chip receives the required power to generate driving power VDD, and generates driving power VDD for driving each of the above-described components. In addition, in the first transmission period, the tag chip receives a data signal from the reader and reads the data signal to perform a command from the reader.

In the second transmission period, the tag chip transmits a necessary data signal to the reader according to a command from the reader. In this period, the reader transmits only a power signal to the tag chip.

The storage unit 250 is an electrically erasable and programmable read only memory (EEPROM), and the storage unit 250 receives a driving power supply VDD from the rectifying unit 202. On the other hand, a voltage of at least 10 [V] is required to perform an operation for writing data to the storage unit 250. This voltage uses the drive power Vddp output from the drive power generation unit 201, that is, not rectified.

In order to transmit and receive data between the tag chip and the reader configured as described above, a transmission / reception frequency should be determined. To determine the transmission / reception frequency between the reader and the tag chip, the reader outputs a preamble signal from the reader to the tag chip. The transmission frequency should be changed when reading the preamble signal and transmitting data to the reader.

The format of the preamble signal will be described below.

Figure 2 is a symbol for the data "0" and "1" set in the international standard (ISO Type-C) for the tag chip of the general UHF band, Figure 3 is a timing of the preamble signal transmitted from the general reader to the tag chip to be.

Symbols for data " 0 " and " 1 " set in the international standard (ISO Type-C) for a tag chip in a general UHF band are shown in FIG. At this time, the length of the TARI is varied from 6.25㎲ to 25㎲. Thus, the length of the data "1" has a length of at least 1.5 x 6.25 ms and at most 2 x 25 ms.

The timing of the preamble signal transmitted from the reader to the tag chip is, as shown in FIG. And an interval (RTcal; 2.5tari to 3.0tari) indicating information of data transmitted from the reader to the tag chip, and a period (TRcal; 1.1RTcal to 3RTcal) indicating information required when transmitting from the tag chip to the reader. .

As such, the tag chip must accurately read the variable tag of the preamble signal transmitted from the reader, and when transmitting data from the tag chip to the reader, the tag chip must be accurately matched and transmitted according to the read tag length to prevent malfunction. Can be.

4 is a table showing frequencies that a typical tag chip must satisfy when transmitting data to a reader.

Accordingly, in the conventional tag chip, the one tag section is counted as a clock signal generated by the clock generator 242 to read the variable tag section.

For example, when the preamble signal as shown in FIG. 3 is transmitted from the reader to the tag chip, the tag chip generates a clock of 3.84 MHz in the clock generator 242 and in the controller 244. One tari period is counted using the clock signal of 3.84 MHz from the end of the delimiter period.

That is, if the clock number of 3.84MHz is counted 24 in the tarry period, the length of the tarry is 6.25㎲, if the number of the 3.84MHz clock signal is 48, the length of the tarry is 12.5㎲, and the count of the 3.84MHz clock signal is 96 You can see that the length of the tarry is 25㎲.

As described above, in the conventional tag chip, since the high frequency clock signal of 3.84 MHz is used to read the variable length, there is a problem in that power consumption is high and a large counter is required. In particular, since the tag chip does not have a built-in battery, high power consumption is fatal for the tag chip.

The present invention has been made in order to solve the above problems, the RFID chip for a tag chip that can reduce the power consumption and counter capacity by dividing the clock signal for reading 1 tari length in RFID (wireless recognition) system It is an object of the present invention to provide a tag length reading device and method.

According to the present invention, a tag length reading device for a tag chip according to the present invention, when enabled, generates a clock signal having a constant frequency and divides the clock signal in half by one according to a frequency control signal. Variable clock generator outputs by dividing / 3 division or 1/6 division and outputs the counted clock signal outputted from the variable clock generator and outputs a carry signal when 8 counts are carried. Outputs a frequency control signal to the variable clock generator and enables / resets the 3-bit counter and 2-bit counter, and counts the count signals output from the 3-bit counter and 2-bit counter. It is characterized in that it comprises a preamble detection control unit for receiving and reading the tarry length.

The tag length reading method for a tag chip according to the present invention for achieving the above object may include detecting a threshold of a preamble signal using a main clock signal and recognizing a tag start point. And a step of reading a carry length by combining a signal and a clock signal divided by 1/2, 1/3, or 1/6 of the main clock signal.

Hereinafter, a tag length reading apparatus and method for a tag chip according to the present invention having the above characteristics will be described in more detail with reference to the accompanying drawings.

5 is a block diagram of a tag length reading device for a tag chip according to the present invention, Figure 6 is a detailed circuit diagram of a clock generator of the tag length reading device for a tag chip according to the present invention.

The tag length reading device for the tag chip according to the present invention generates a clock signal having a constant frequency when the power source core VDD is supplied as an enable (EN) signal, as shown in FIG. A variable clock generator 101 for dividing the clock signal by 1/2, 1/3, or 1/6 in accordance with the signal Freq_adjust (3 bits), and an external enable signal EN1 and a reset signal. 3 bit counter 102 which is controlled according to the (RESET1) signal and counts a predetermined number (8) of the clock signals output from the variable clock generator 101 and outputs a carry signal when the corresponding number is counted. And a 2-bit counter 103 that is controlled according to an external enable signal EN2 and a reset signal RESET2 to count and output a carry signal output from the 3-bit counter 102, and the variable clock. The frequency control signal freq_adjust is applied to the generator 101. Outputs enable signals EN1 and EN2 and reset signals RESET1 and RESET2 to the 3-bit counter 102 and 2-bit counter 103, and outputs the 3-bit counter 102 and 2-bit counter 103. And a preamble detection control unit 104 for receiving the count signal outputted from the frame and reading the tar length.

Here, the circuit configuration of the variable clock generator 101 is as shown in FIG.

That is, as shown in Figure 6, the variable clock generator 101 is connected to the serial and at the same time enable signal is applied to the first to fifth inverters 111 is configured so that the final output signal is fed back first , 112, 113, 114, and 115, first to third capacitors C11, C12, and C13 having a predetermined capacitance to divide a clock frequency, and a frequency control signal freq_adjust1 of the preamble detection control unit 104. According to the first switch 116 to connect / disconnect the first capacitor (C11) to the output terminal of the first inverter 111 and according to the frequency control signal (freq_adjust2) of the preamble detection control unit 104 The second switch 117 connects / disconnects the second capacitor C12 to the output terminal of the second inverter 112 and the second control signal according to the frequency control signal freq_adjust3 of the preamble detection control unit 104. 3 The third capacitor C13 is connected to the output terminal of the inverter 113. It is comprised with the 3rd switch 118 which interrupts | blocks.

Referring to the tag length reading method of the tag length reading device for the tag chip according to the present invention configured as described above is as follows.

7 is a timing diagram illustrating a method of varying (dividing) a clock frequency of a tag length reading device for a tag chip according to the present invention.

First, the variable clock generation unit 101 generates a clock signal of 3.84 MHz when enabled.

In addition, when the frequency control signal freq_adjust is output as 001 from the preamble detection controller 104 (only the first frequency control signal freq_adjust1 is enabled), the variable clock generator 101 may include a first switch. Since 116 is turned on to connect the first capacitor C11, the clock signal of 3.84 MHz is divided by 1/2 to output a clock signal of 1.92 MHz.

In addition, when the frequency control signal freq_adjust is output as 011 from the preamble detection controller 104, the variable clock generator 101 enables the first and second frequency control signals freq_adjust1 and freq_adjust2. Since the first and second switches 116 and 117 are turned on to connect the first and second capacitors C11 and C12, the clock signal of 3.84 MHz is divided by 1/3 to output a clock signal of 1.28 MHz.

Finally, when the frequency control signal freq_adjust is output as 111 from the preamble detection controller 104 (first, second, and third frequency control signals freq_adjust1, freq_adjust2, freq_adjust3). Is enabled), and the first, second, and third switches 116, 117, and 118 are turned on to connect the first, second, and third capacitors C11, C12, and C13, so that the clock of 3.84 MHz The signal is divided by 1/6 to output a clock signal of 640KHz.

Therefore, when the preamble signal as shown in FIG. 3 is output from the reader to the tag chip, the tag chip detects a delimiter of the preamble signal with the high frequency clock signal of 3.84 MHz.

In this way, when the delimiter is normally detected, the preamble detection control unit 104 uses the 3-bit counter 102 and the 2-bit counter 103 to detect 6.25 kHz, which is the minimum length (spec) of the tar. Enable to allow the 3-bit counter 102 to count the 3.84 MHz high frequency clock signal initially.

That is, the 3-bit counter 102 counts the 3.84 MHz clock signal and outputs the counted clock signal to the preamble detection control unit 104. When eight clock signals of 3.8484 MHz are counted in the 3-bit count 102, the 3-bit count 102 outputs a carry signal. At this time, the preamble detection control unit 104 outputs 001 as a frequency control signal to output a clock signal of 1.92 MHz divided by half from the variable clock generation unit 101, and the 3-bit counter 102. ).

Thereafter, the 3-bit counter 102 counts a 1.92 MHz clock signal output from the variable clock generator 101 and outputs the counted clock signal to the preamble detection controller 104 in the same manner as described above. When eight counts, a carry signal is output. At this time, the preamble detection control unit 104 outputs 011 as a frequency control signal when eight clock signals of the 1.92 MHz are counted in the 3-bit count 102, and the variable clock generator 101 outputs 1/1. A three-division 1.28 MHz clock signal is output, and the 3-bit counter 102 is initialized.

Subsequently, the 3-bit counter 102 counts a clock signal of 1.28 MHz output from the variable clock generator 101 and outputs the same to the preamble detection controller 104 in the manner described above. When the dog counts, a carry signal is output. At this time, the preamble detection control unit 104 outputs 111 as a frequency control signal when 8 clock signals of 1.28 MHz are counted in the 3-bit count 102, and the variable clock generator 101 outputs 1/1. The clock signal of 640KHz divided by 6 is outputted, and the 3-bit counter 102 is initialized.

In addition, the 3-bit counter 102 counts a 640 KHz clock signal output from the variable clock generator 101 and outputs the counted clock signal to the preamble detection controller 104 in the same manner as described above.

In the above process, the carry signal output from the 3-bit counter 102 is counted by the 2-bit counter 103 and output to the preamble detection control unit 104.

In this way, the clock signal is variable (divided) to read the carry length, and when the reading is completed, the variable clock generator 101, the 3-bit counter 102 and the 2-bit counter 103 are reset.

That is, as shown in Fig. 7, the time when each of the initial 3.84 MHz clock signal and the 1.92 MHz clock signal are counted respectively becomes 6.25 kHz carry length, and eight clock signals of 1.28 MHz are subsequently counted. The time point becomes the length of 12.5 Hz carry, and the time point when eight clock signals of 640 KHz is counted becomes the length of 25 Hz carry.

The present invention described above is not limited to the above-described embodiments and the accompanying drawings, and it is common in the art that various substitutions, modifications, and changes can be made without departing from the technical spirit of the present invention. It will be evident to those who have knowledge of.

In the tag length reading apparatus and method for a tag chip according to the present invention as described above has the following advantages.

The apparatus and method for tag length reading for a tag chip according to the present invention divides the main clock signal for reading 1 tag length into 1/2, 1/3, and 1/6 divisions, and combines them to count the length of the tar. By suppressing the use of the clock signal of the frequency, power consumption can be reduced, and since the counter for counting the clock signal is limited to 3 bits and 2 bits, the counter capacity can be reduced.

Claims (7)

When enabled, a variable clock generator for generating a clock signal having a constant frequency and dividing the clock signal by 1/2, 1/3, or 1/6 according to the frequency control signal. 3-bit counter for counting and outputting clock signals output from the variable clock generator and outputting carry signals when eight counts are counted A 2-bit counter for counting and outputting a carry signal output from the 3-bit counter; Preamble detection for outputting a frequency control signal to the variable clock generator, enabling / resetting the 3-bit counter and 2-bit counter, and receiving a count signal output from the 3-bit counter and 2-bit counter to read the length of the tarry. A tag length reading device for a tag chip, characterized by comprising a control unit. The method of claim 1, The variable clock generator, First to fifth inverters connected in series and simultaneously enabled signals to be configured so that the final output signal is fed back first; First to third capacitors having a predetermined capacitance to divide a clock frequency; Connecting / blocking the first capacitor to an output terminal of the first inverter, connecting / blocking the second capacitor to an output terminal of the second inverter according to a frequency control signal of the preamble detection controller, and the third inverter And a first to third switches respectively connecting / blocking the third capacitors to the output terminals of the tag length reading device for the tag chip. Detecting a start point of the preamble signal by using a main clock signal and recognizing a start point of tarry; and And a read length of the carry by combining the main clock signal and the clock signal divided by 1/2, 1/3, or 1/6 of the main clock signal. Read method. The method of claim 3, wherein And a main clock signal having a frequency of 3.84 MHz. The method of claim 3, wherein A tag length reading method for a tag chip, characterized in that a tag length is read using the main clock signal and the half divided clock signal of the main clock signal of 6.25 ms or less, which is the minimum specification of the tag length. The method of claim 3, wherein The tag length reading method according to claim 1, wherein the tag length is read using a third divided clock signal of the main clock signal in a section having a length of 6.25 ms or more and 12.5 ms or less. The method of claim 3, wherein And a section length of 12.5 ms or more of the tar length using a 1/6 divided clock signal of the main clock signal.

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