KR101939239B1 - Envelop Detector for RF Communication - Google Patents

Abstract

According to an embodiment of the present invention, an envelope detector for RFID communication includes a first node; A second node; A second input connected to the first node, a second input connected to the second node, and a voltage applied to the first input and a voltage applied to the second input, A first asymmetric comparator having an output terminal for supplying a first reference voltage; A first transistor having an output terminal connected to a gate terminal of the first comparator and having a source and a drain terminal connected to the first node and the second node; And comparing the offset voltage with a difference between a voltage applied to a third input connected to the second node, a voltage applied to a fourth input and a third input connected to the first node, and a voltage applied to the fourth input, A second asymmetric comparator having an output terminal for supplying an input signal; A second transistor having an output terminal connected to the gate terminal of the second comparator, and a source and a drain terminal connected to the first node and the second node; And a symmetric comparator having two inputs connected to the first node and the second node and an output terminal for supplying an output signal generated by a voltage difference applied to the first node and the second node, And receives an input signal through the first node to sense a change in the input signal to determine a voltage level of the output signal.

Description

[0001] Envelope Detector for RF Communication [

The technical idea of the present invention relates to an envelope detector, and more particularly to an envelope detector used for RFID communication.

In recent years, RFID tags have been used in various applications such as logistics management systems, user authentication systems, electronic money systems, and traffic systems. For example, in the logistics management system, classification of cargo or inventory management is performed by using IC (Integrated Circuit) tag in which data is recorded instead of a delivery slip or a tag. In addition, in the user authentication system, entrance management and the like are performed by using an IC card recording personal information and the like.

Communication protocols of contactless smart card devices using a carrier frequency of 13.56 MHz are A type and B type. These two types increase the complexity of the circuit to distinguish these types. Therefore, an envelope detector that can be used without distinguishing between A type and B type is required.

In addition, when the RFID device and the RFID tag are relatively far apart, the tag recognition performance deteriorates.

A problem to be solved by the technical idea of the present invention is to provide an envelope detector applicable to an envelope detector for RFID communication using a carrier frequency of 13.56 MHz without any distinction between A type and B type.

SUMMARY OF THE INVENTION An object of the present invention is to provide an envelope detector that improves the performance of remote sensing.

An envelope detector for RFID communication according to an embodiment of the present invention includes: a first node; A second node; A second input connected to the first node, a second input connected to the second node, and a voltage applied to the first input and a voltage applied to the second input, A first asymmetric comparator having an output terminal for supplying a first reference voltage; A first transistor having an output terminal connected to a gate terminal of the first comparator and having a source and a drain terminal connected to the first node and the second node; And comparing the offset voltage with a difference between a voltage applied to a third input connected to the second node, a voltage applied to a fourth input and a third input connected to the first node, and a voltage applied to the fourth input, A second asymmetric comparator having an output terminal for supplying an input signal; A second transistor having an output terminal connected to the gate terminal of the second comparator, and a source and a drain terminal connected to the first node and the second node; And a symmetric comparator having two inputs connected to the first node and the second node and an output terminal for supplying an output signal generated by a voltage difference applied to the first node and the second node, And receives an input signal through the first node to sense a change in the input signal to determine a voltage level of the output signal.

Preferably, the envelope detector for RFID communications comprises: a first capacitor coupled to the first node; And a second capacitor coupled to the second node.

Preferably, the envelope detector for RFID communication includes a current source connected to the first node and supplying a constant current.

Preferably, the first transistor and the second transistor are transistors having the same physical characteristics.

Preferably, the symmetric comparator outputs logic high when the voltage level applied to the first node is higher than the voltage level applied to the second node, and the voltage level applied to the first node is higher than the voltage level applied to the second node. And outputs a logic low when the voltage level is lower than the voltage level applied to the two nodes.

Preferably, when the voltage level of the first input terminal of the first asymmetrical comparator is higher than the voltage level of the second input terminal of the first asymmetric comparator by an offset voltage or more, the first transistor is turned- On).

Preferably, when the voltage level of the third input terminal of the second asymmetric comparator is higher than the voltage level of the fourth input terminal of the second asymmetric comparator by more than an offset voltage, the second transistor is turned- On).

Preferably, an input signal having a carrier frequency of 13.56 MHz is received through the first node.

Preferably, the output signal is toggled when the amplitude of the signal input through the first node is changed by the offset voltage.

According to another aspect of the present invention, there is provided an RFID communication apparatus including a demodulator for receiving a radio signal applied through an antenna, rectifying and amplifying the radio signal to generate an input signal, and demodulating the input signal to generate an output signal; And a modulator for receiving an output signal from the demodulator and outputting a response signal corresponding to the output signal to the antenna, wherein the demodulator comprises: a first node; A second node; A second input connected to the first node, a second input connected to the first node, and an output signal generated according to whether a difference between the voltage applied to the first input and the voltage applied to the second input is greater than an offset, A first asymmetric comparator having an output terminal for supplying a first reference voltage; A first transistor having an output terminal connected to a gate terminal of the first comparator and having a source and a drain terminal connected to the first node and the second node; An output signal generated according to whether a difference value obtained by subtracting a voltage applied to a fourth input terminal from a voltage applied to a third input terminal connected to the second node, a fourth input terminal connected to the first node, and a third input terminal is greater than an offset, A second asymmetric comparator having an output terminal for supplying an input signal; A second transistor having an output terminal connected to the gate terminal of the second comparator, and a source and a drain terminal connected to the first node and the second node; And a symmetric comparator having two inputs connected to the first node and the second node and an output terminal for supplying an output signal generated by a voltage difference applied to the first node and the second node, And an envelope detector for RFID communication that receives an input signal through the first node and detects a change in the input signal to determine a voltage level of the output signal.

The envelope detector according to the present invention as described above can provide an envelope detector which can be applied without discrimination between A type and B type in an envelope detector for RFID communication using a carrier frequency of 13.56 MHz.

In addition, the envelope detector according to the present invention as described above can provide an envelope detector with improved remote recognition performance.

1 is a circuit diagram of an envelope detector for RFID communication according to an embodiment of the present invention.
Fig. 2 is a timing chart for explaining the operation of the envelope detector for RFID communication of Fig. 1. Fig.
3 and 4 are circuit diagrams for explaining a comparator included in an Envelope Detector for RFID Communication of the present invention.
5 and 6 are block diagrams of an RFID device including an envelope detector according to the present invention.

Hereinafter, embodiments of the present invention will be described in detail with reference to the accompanying drawings. Embodiments of the present invention are provided to more fully describe the present invention to those skilled in the art. The present invention is capable of various modifications and various forms, and specific embodiments are illustrated and described in detail in the drawings. It should be understood, however, that the invention is not intended to be limited to the particular forms disclosed, but includes all modifications, equivalents, and alternatives falling within the spirit and scope of the invention. Like reference numerals are used for similar elements in describing each drawing. In the accompanying drawings, the dimensions of the structures are enlarged or reduced from the actual dimensions for the sake of clarity of the present invention.

The terminology used in this application is used only to describe a specific embodiment and is not intended to limit the invention. The singular expressions include plural expressions unless the context clearly dictates otherwise. In this application, the terms "comprises", "having", and the like are used to specify that a feature, a number, a step, an operation, an element, a part or a combination thereof is described in the specification, But do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof.

Also, the terms first, second, etc. may be used to describe various components, but the components should not be limited by the terms. The terms may be used for the purpose of distinguishing one component from another. For example, without departing from the scope of the present invention, the first component may be referred to as a second component, and similarly, the second component may also be referred to as a first component.

RFID (Radio Frequency Identification Tag Chip) is a non-contact automatic identification method that attaches an RFID tag to an object to be identified and communicates with an RFID reader through radio transmission / reception in order to automatically identify an object using a radio signal . The use of such RFID has made it possible to overcome the disadvantages of conventional automatic identification technology, such as bar code and optical character recognition technology.

Here, the RFID device uses frequencies of a plurality of bands, and the characteristics thereof vary depending on the frequency band. Generally, RFID devices are slower in recognition rate, operate at shorter distances, and are less influenced by the environment as the frequency band is lower. On the other hand, the higher the frequency band, the faster the recognition speed, the longer the distance, and the greater the influence of the environment.

Unless otherwise defined, all terms used herein, including technical or scientific terms, have the same meaning as commonly understood by one of ordinary skill in the art to which this invention belongs. Terms such as those defined in commonly used dictionaries are to be interpreted as having a meaning consistent with the contextual meaning of the related art and are to be interpreted as either ideal or overly formal in the sense of the present application Do not.

1 is a circuit diagram of an envelope detector (RFID communication) 100 for RFID communication according to an embodiment of the present invention.

The envelope detector 100 for RFID communication includes a first asymmetric comparator (Com1), a second asymmetric comparator (Com2), a symmetric comparator (Com3) first transistor (TR1 , A second transistor (TR2), and a current source (IS).

The first asymmetric comparator Com1 has a first input IN1, a second input IN2, and an output OUT1. The first asymmetric comparator Com1 has a first input terminal IN1 connected to the first node ND1 and a second input terminal IN2 connected to the second node ND2. The first asymmetrical comparator Com1 outputs the output signal SIG_OUT1 according to whether the difference obtained by subtracting the voltage applied to the second input IN2 from the voltage applied to the first input IN1 is greater than the offset voltage, ) And outputs it.

For example, if the offset voltage is a [V], the magnitude of the voltage applied to the first input IN1 is equal to or greater than VC + a [V] and the magnitude of the voltage applied to the second input IN1 is equal to VC [V], the output signal SIG_OUT1 applied to the output terminal OUT1 becomes logic high. For example, when the magnitude of the voltage applied to the first input IN1 is less than VC + a [V] and the magnitude of the voltage applied to the second input IN1 is VC [V] The output signal SIG_OUT1 applied to the output terminal of the comparator becomes logic low.

The output terminal OUT1 for supplying the generated output signal SIG_OUT1 is connected to the gate terminal of the first transistor TR1. And is connected to the source and drain terminals of the first transistor TR1 to the first node ND1 and the second node ND2.

The second asymmetric comparator Com2 has a third input IN3, a fourth input IN4, and an output OUT2. The second asymmetric comparator Com2 has a third input IN3 connected to the second node ND2 and a fourth input IN4 connected to the first node ND1. The second asymmetric comparator Com2 outputs the output signal SIG_OUT2 according to whether the difference obtained by subtracting the voltage applied to the third input IN3 from the voltage applied to the fourth input IN4 is greater than the offset voltage, ) And outputs it.

For example, if the offset voltage is a [V], the magnitude of the voltage applied to the third input IN3 is VC [V] and the magnitude of the voltage applied to the fourth input IN4 is VC - a [ V], the output signal SIG_OUT1 applied to the output terminal OUT2 becomes logic high. For example, when the magnitude of the voltage applied to the third input IN3 is VC [V] and the magnitude of the voltage applied to the fourth input IN4 is equal to or greater than VC - a [V] The applied output signal SIG_OUT2 becomes logic low.

The output terminal OUT2 for supplying the generated output signal SIG_OUT2 is connected to the gate terminal of the second transistor TR2. And is connected to the source and drain terminals of the second transistor TR2 to the first node ND1 and the second node ND2.

The symmetric comparator Com3 has two input terminals connected to the first node ND1 and the second node ND2 and an output signal generated by the voltage difference applied to the first node ND1 and the second node ND2 And an output terminal for supplying the output signal. For example, when the voltage level of the first node ND1 is higher than the voltage level of the second node ND2, the voltage level of the first node ND1 is higher than the voltage level of the second node ND2 ), ≪ / RTI > a logic low (low) is output.

Hereinafter, the operation of the envelope detector 100 for RFID communication will be described with reference to FIG.

FIG. 2 is a timing chart for explaining the operation of the envelope detector 100 for RFID communication of FIG.

The signal L1L2 is a signal input to the envelope detector 100 for RFID communication. The signal L1L2 is converted into an input signal INPUT through rectification and amplification.

It is assumed that the input signal INPUT is input through the first node ND1 at a magnitude (amplitude) of VC + a [V]. When the voltage applied to the second node ND2 becomes higher than VC [V], the voltage difference between the first node ND1 and the second node ND2 becomes low, so that the first asymmetrical comparator Com1 becomes a logic high the first transistor TR1 will not output a high signal, and thus the first transistor TR1 will be turned off. If the voltage applied to the second node ND2 is lowered below VC [V], the first transistor TR1 will be turned on and receive charge from the first node ND1. Therefore, if the input signal INPUT is input through the first node ND1 at an amplitude of VC + a [V], the voltage applied to the second node ND2 is the magnitude of the voltage VC [V] Amplitude).

In this state, if the input signal INPUT input through the first node ND1 is reduced in size and input as the amplitude of VC [V], for example, the first transistor TR1 is turned- Off state, and charges are discharged from the first node ND1 by the current source IS.

In this case, the voltage of the first node ND1 converges at a level lower by a [V] than the voltage of the second node ND2. For example, it is assumed that the voltage level of the first node ND1 converges to VD a [V]. When the voltage level of the second node ND2 becomes equal to or higher than VD [V], the second transistor TR2 will be turned on, so that the second node ND2 is turned off by the current source IR A descent will occur. If the voltage level of the second node ND2 becomes VD [V] or lower, there will be no further voltage change at the second node ND2 since the second transistor TR2 will be turned off . Therefore, the voltage level of the second node ND2 converges to VD [V].

In this process, when the voltage of the first node ND1 becomes lower than the voltage of the second node ND2, the output signal OUTPUT is output from the symmetric comparator Com3, for example, at a logic low It is toggled to logic high.

Hereinafter, a case where the magnitude of the input signal INPUT input through the first node ND1 is increased will be described. The first transistor TR1 will be turned on and the voltage level of the second node ND2 will be VC [ V]. In this case, the level of the voltage of the first node ND1 becomes higher than the level of the voltage of the second node ND2. Thus, the output signal OUTPUT is toggled, for example, from a logic high to a logic low by the symmetric comparator Com3.

The envelope detector 100 for RFID communication according to an embodiment of the present invention can prevent a ripple occurring when a voltage level is changed by connecting a capacitor to each of the first node and the second node.

The envelope detector 100 for RFID communication according to an embodiment of the present invention connects the current source IR to the first node and outputs the current to the first node ND1 when the voltage amplitude of the signal L1L2 is low, It is possible to further reduce the magnitude of the voltage of the capacitor.

The envelope detector 100 for RFID communication according to an embodiment of the present invention includes a first transistor and a second transistor having the same physical characteristics to detect a voltage level when the input signal INPUT is high and a voltage level when the input signal INPUT is high, And the voltage level when the input signal INPUT is low can be kept constant.

3 and 4 are circuit diagrams for explaining a comparator included in an envelope detector for RFID communication 100 of the present invention.

3 is a circuit diagram illustrating the first asymmetric comparator Com1. The first asymmetric comparator Com1 may include transistors TR31, TR32, TR33, TR34, and TR35. Here, the node A corresponds to the first input IN1 in Fig. The node B corresponds to the second input IN2 in Fig. The transistor TR31 and the transistor TR32 constitute a current mirror circuit (Current Mirror Circuit). Therefore, the same current flows through the node ND31 and the node ND32.

When a logic high is input to the node A and a logic low is input to the node B, a high voltage is applied to the node ND32. Thus, the output OUT1 corresponds to a logic high (high).

When a logic low is input to the node A and a logic high is input to the node B, a low voltage is applied to the node ND32. Thus, the output OUT1 corresponds to a logic low. It is asymmetrical to the node ND32 and the voltage VS so that two transistors are connected in parallel so that one transistor is connected between the node ND31 and the voltage VS, And the signal of the output (OUT1) terminal is toggled when the magnitude of the voltage applied to the node (B) differs by a certain value. On the other hand, the symmetric comparator Com3 of FIG. 4 can be implemented such that the signal of the output terminal is toggled when the voltage applied to the node A and the node B is the same.

In addition, the first asymmetric comparator (Com1) and the second asymmetric comparator (Com2) in Fig. 3 may be the same.

5 is a configuration diagram of an RFID tag apparatus including an envelope detector 100 according to the present invention.

An RFID device according to an embodiment of the present invention includes an analog unit 10, a digital unit 20, a memory unit 30, and an antenna 40. [

The antenna 40 serves to receive a radio signal transmitted from an external RFID reader.

The analog unit 10 amplifies the input radio signal and generates a power supply voltage VDD which is a driving voltage of the RFID tag. Then, an operation command signal is detected from the input radio signal, and the command signal CMD is output to the digital section 20. [ The analog unit 10 outputs the power-on reset signal POR and the clock CLK to the digital unit 20 for sensing the output voltage VDD and controlling the reset operation.

The digital unit 20 receives a power supply voltage VDD, a power-on reset signal POR, a clock CLK and a command signal CMD from the analog unit 10 and outputs a response signal RP ). The digital section 20 outputs the address ADD, the input / output data I / O, the control signal CTR and the clock CLK to the memory section 30.

Further, the memory unit 30 writes / reads data by using a memory element, and stores data.

According to one embodiment of the present invention, the analog portion 10 includes an envelope detector 100 including an asymmetric comparator to toggle the output signal when the input signal varies by an offset voltage difference. In this case, there is an effect of solving the problem that the remote recognition performance of the RFID device is reduced. That is, according to an embodiment of the present invention, the envelope detector 100 for RFID communication maintains the voltage difference between the first node and the second node at an offset voltage, and stably receives the signal without decreasing the remote recognition performance of the RFID device There is an advantage to be able to do.

6 is a configuration diagram of an RFID tag device 1 including an envelope detector 100 according to the present invention.

The RFID tag device 1 of the present invention includes an antenna 40, a modulator 120, a demodulator 110, a power on reset unit 140, a clock generator A clock generator 130, a digital unit 20, and a memory unit 30.

First, the antenna 40 receives a radio signal RF_EXT transmitted from an external RFID reader. And transmits the radio signal RF_EXT received by the RFID tag device 1 to the external RFID reader via the antenna 40. [ The radio signal RF_EXT applied from the modulation unit 120 to the antenna 40 is transmitted to the RFID reader.

The demodulation unit 110 demodulates the input signal INPUT input through the antenna 40 and outputs the generated demodulation signal DEMOD to the digital unit 20. [

The modulator 120 modulates the response signal RP applied from the digital unit 20 and outputs the generated radio signal through the antenna 40. [

The clock generating unit 130 supplies a clock CLK for controlling the operation of the digital unit 20 to the digital unit 20. [

The power-on reset unit 140 outputs a power-on reset signal POR to the digital unit 20 for controlling the reset operation. Here, the power-on reset signal POR rises as the power supply voltage while the power supply voltage transitions from the low level to the high level, and transitions from the high level to the low level as soon as the power supply voltage is supplied to the power supply voltage level VDD, Quot; means a signal for resetting the internal circuit of the device 1.

The digital section 20 receives the power supply voltage VDD, the power-on reset signal POR, the clock CLK and the demodulation signal DEMOD and analyzes the demodulation signal DEMOD and generates control signals and processing signals . The digital unit 20 outputs a response signal RP corresponding to the control signal and the processing signals to the modulation unit 120. [ The digital section 20 outputs the address ADD, the data I / O, the control signal CTR and the clock CLK to the memory section 30.

The memory unit 30 includes a plurality of memory cells, and each memory cell writes data to the storage element and reads data stored in the storage element. Here, the memory unit 30 may be a nonvolatile ferroelectric memory (FeRAM). The nonvolatile ferroelectric memory (FeRAM) has a data processing speed of about a DRAM. In addition, the nonvolatile ferroelectric memory (FeRAM) has a structure almost similar to that of DRAM, and has a high remanent polarization, which is a characteristic of a ferroelectric, by using a ferroelectric as a material of a capacitor. Due to the residual polarization property, even if the electric field is removed, the data can not be erased.

According to an embodiment of the present invention, the demodulation unit 110 includes an envelope detector 100 including an asymmetric comparator, and toggles the output signal when the input signal fluctuates by an offset voltage difference. In this case, there is an effect of solving the problem that the remote recognition performance of the RFID device is reduced.

The envelope detector 100 included in the demodulator 110 according to an exemplary embodiment of the present invention may include a capacitor to prevent ripples generated when the voltage level is changed.

The envelope detector 100 included in the demodulation unit 110 according to an embodiment of the present invention connects a current source IR to easily detect a size change when the magnitude of the signal RF_EXT varies. can do.

While the present invention has been described with reference to exemplary embodiments, it is to be understood that the invention is not limited to the disclosed exemplary embodiments, but, on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims. Accordingly, the true scope of the present invention should be determined by the technical idea of the appended claims.

1: RFID tag device
10: analog part
20: Digital section
30: memory unit
40: Antenna
100: Envelope detector for RFID communication
110: demodulator
120: Modulation section
130: clock generator
140: Power-on reset section

Claims (10)

A first node; A second node;
A second input connected to the first node, a second input connected to the second node, and a voltage applied to the first input and a voltage applied to the second input, A first asymmetric comparator having an output terminal for supplying a first reference voltage;
A first transistor having an output terminal connected to a gate terminal of the first asymmetric comparator and having a source and a drain terminal connected to the first node and the second node;
And comparing the offset voltage with a difference between a voltage applied to a third input connected to the second node, a voltage applied to a fourth input and a third input connected to the first node, and a voltage applied to the fourth input, A second asymmetric comparator having an output terminal for supplying an input signal;
A second transistor having an output terminal of the second asymmetric comparator connected to a gate terminal, and a source and a drain terminal connected to the first node and the second node; And
And a symmetric comparator having two inputs connected to the first node and the second node and having an output terminal for supplying an output signal generated by a voltage difference applied to the first node and the second node,
An envelope detector for receiving an input signal through the first node and sensing a change in the input signal to determine a voltage level of the output signal. 2. The apparatus of claim 1, further comprising: a first capacitor coupled to the first node; And a second capacitor coupled to the second node. The envelope detector of claim 1, further comprising a current source connected to the first node to supply a constant current. The envelope detector for RFID communication according to claim 1, wherein the first transistor and the second transistor are transistors having the same physical characteristics. 2. The method of claim 1, wherein the symmetric comparator outputs a logic high when a voltage level applied to the first node is higher than a voltage level applied to the second node, Is lower than a voltage level applied to the second node, outputs a logic low signal. The method as claimed in claim 1, wherein when the voltage level of the first input terminal of the first asymmetric comparator is higher than the voltage level of the second input terminal of the first asymmetric comparator by an offset voltage or more, The RFID tag is turned on.
The method as claimed in claim 1, wherein when the voltage level of the third input terminal of the second asymmetric comparator is higher than the voltage level of the fourth input terminal of the second asymmetric comparator by an offset voltage or more, The RFID tag is turned on. The envelope detector for RFID communication according to claim 1, wherein an input signal having a carrier frequency of 13.56 MHz is received through the first node. The envelope detector for RFID communication according to claim 1, wherein the output signal is toggled when an amplitude of a signal inputted through the first node is changed by the offset voltage. A demodulator for receiving a radio signal applied through an antenna, rectifying and amplifying the radio signal to generate an input signal, and demodulating the input signal to generate an output signal; And
And a modulator for receiving an output signal from the demodulator and outputting a response signal corresponding to the output signal to an antenna, wherein the demodulator comprises:
A first node; A second node;
A second input connected to the first node, a second input connected to the first node, and an output signal generated according to whether a difference between the voltage applied to the first input and the voltage applied to the second input is greater than an offset, A first asymmetric comparator having an output terminal for supplying a first reference voltage;
A first transistor having an output terminal connected to a gate terminal of the first comparator and having a source and a drain terminal connected to the first node and the second node;
An output signal generated according to whether a difference value obtained by subtracting a voltage applied to a fourth input terminal from a voltage applied to a third input terminal connected to the second node, a fourth input terminal connected to the first node, and a third input terminal is greater than an offset, A second asymmetric comparator having an output terminal for supplying an input signal;
A second transistor having an output terminal connected to the gate terminal of the second comparator, and a source and a drain terminal connected to the first node and the second node; And
And a symmetric comparator having two inputs connected to the first node and the second node and having an output terminal for supplying an output signal generated by a voltage difference applied to the first node and the second node,
And an envelope detector for RFID communication that receives an input signal through the first node and detects a change in an input signal to determine a voltage level of the output signal.

Images