JPS6261973B2 - - Google Patents

Description

[Detailed description of the invention] The present invention relates to large scale logic integrated circuits.

Large scale logic integrated circuits consist of input stage latches, combinational logic circuits and output stage logic circuits. In order to facilitate diagnosis and maintenance, each latch has a scan-in input in addition to the normally used data input and timing input.
Usually, the configuration is such that a value of "1" or "0" can be input from the scan-in input. The test method is to input the value into the latch serially one bit at a time, pass it through the combinational circuit, then apply a timing pulse to the output stage latch, capture the output of the combinational circuit into the output latch,
Give the scanout address to the output latch 1
Diagnosis is performed by reading scanout data bit by bit.

The above-mentioned conventional techniques have the disadvantage that only the direct current characteristics of the combinational circuit can be diagnosed. That is, since values are input to each input stage latch bit by bit, the influence of the output of the latch after the scan-in operation is passed through the combinational circuit as a level signal, and the pulse influence is lost. If you try to investigate this, the problem is that you can only test whether the time it takes for the last 1-bit change in the input latch to pass through the combinational circuit is in time for the latch time of the output latch.

SUMMARY OF THE INVENTION An object of the present invention is to solve the above-mentioned problems and provide an integrated circuit capable of testing delay time.

The present invention provides an exclusive OR circuit at the output of input latches that operate at the same timing, writes a test pattern reversed from the original test pattern to the input latch during diagnosis, and after writing all bit patterns, performs an exclusive OR circuit. By switching the inputs at the same time and inputting a regular test pattern into the combinational circuit, it is possible to determine whether the test pattern has passed through the combinational circuit within the time from the data switch to the capture of the output latch. It is in the point of doing.

FIG. 1 shows a block diagram of a conventional logic integrated circuit. In the figure, 1 and 4 are combinational circuits, and the output of combinational circuit 1 is latched into a group of latches at latch timing inputs 8 and 9, and input to combinational circuit 4. The output of combinational circuit 4 is latched into output latch group 5 at latch timing input 10. The scan address 11 and scan-in data are input to the scan decoder 6. The scan-in data 12 is written to the latch 2 or 3 specified by the scan address 11, the data is taken into the output latch group 5 at the latch timing 10, and the scan-out selector 7
and diagnose the four parts of the combinational circuit.
For this reason, the values of the input latch group are determined bit by bit, and the delay time passing through the combinational circuit 4 cannot be sufficiently inspected.

FIG. 2 shows an embodiment of the present invention, in which a group of 13 exclusive OR circuits is added to the conventional circuit shown in FIG. 1 at the input section of the section 4 to be diagnosed. During normal operation, the signal passing through combinational circuit 1 is held at latch timing 8.
At latch timing 9, the signal is taken into latch group 2, and at latch timing 9, it is taken into latch group 3. Both pass through the combinational circuit 4 and are taken into the latch group 5 at the latch timing 10.

For diagnosis of combinational circuit 4, scan address 1
1 and scan-in data 12, inverted versions of the original test patterns are sequentially written into latch groups 2 and 3. Then, if a pulse is input from the diagnostic terminal 15 instead of the latch timing 8 and the diagnostic terminal 14 instead of the latch timing 9, it passes through the combinational circuit 4, and is taken into the latch group 5 according to the latch timing. Time inspection becomes possible.

In this way, using scan-in diagnostics, the delay time of the combinational circuit portion can be tested in time intervals of timing pulses.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing a conventional example, and FIG. 2 is a block diagram showing an embodiment of the present invention. 2, 3, 5... Latch group, 4... Combinational circuit, 13... Exclusive OR circuit.

Claims (1)

[Claims] 1. In an integrated circuit that includes a combinational circuit and a latch connected to its input, and has a configuration in which any value can be entered into the latch from the outside, the output of the latch is sent to the combinational circuit via an exclusive OR circuit. After inputting an arbitrary value into the latch, the other inputs of the exclusive OR circuit are switched and the value of the latch is applied to the combinational circuit through the exclusive OR circuit. circuit.