JPH07174821A - Inspecting method for boundery scanning cell and testing circuit - Google Patents

Abstract

PURPOSE:To lower the number of elements as much as possible by carrying out shifting work by a D-type single latch and a dynamic gate. CONSTITUTION:A first multiplexer 1 selects either first input data or second input data based on a shift mode signal and sends it out. A D-type single latch 2 sends out the output of the multiplexer 1 based on the first shift clock signal. A dynamic gate 3 dynamically stores the output of the latch 2 based on the second clock signal. A second multiplexer 8 selects either the first input data or the output of a latch 4 for updating and sends it out. That is, the latch 2 is made to have a function as a master latch by a shift clock A and the gate 3 is made to have a function as a slave latch by a shift clock B, so that two-phase operation can be carried out.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a boundary scan cell used as a test circuit for an integrated circuit device, and a test circuit verification method for verifying a test circuit.

[0002]

2. Description of the Related Art The structure of a conventional boundary scan cell is shown in FIG. This boundary scan cell includes multiplexers 1 and 8 and D type flip-flops 6 and 7. Next, the structure and operation of this boundary scan cell will be described.

When operating in the normal mode, by controlling the test mode signal to "0", the data can be directly output from the input terminal IN to the output terminal OUT through the multiplexer 8. When such a boundary scan cell is placed on the external terminals of the integrated circuit chip, it is possible to prevent the state of the external terminals from being affected. When outputting other boundary scan cell data to the output terminal OUT, by controlling the test mode signal to “1”, the data is input from the D type flip-flop 7 to the output terminal OUT through the multiplexer 8. It can be applied instead of the data from IN. Furthermore, when observing the state of the input terminal IN, the shift mode signal is controlled to "0" so that the input terminal I is passed through the multiplexer 1.
By applying the data from N to the D terminal of the D type flip-flop 6 and further applying a clock pulse to the shift clock signal, the data can be taken in the D type flip-flop 6. The data setting to the boundary scan cell and the observation can be performed by the shift register operation by connecting the shift register stage composed of the multiplexer 1 and the D-type flip-flop 6 to another boundary scan cell.

The conventional boundary scan cell shown in FIG. 9 is composed of two multiplexers 1 and 8 and D type master-slave flip-flops (double latches) 6 and 7. And the D-type flip-flop 6,
If 7 is composed of a CMOS transfer gate and an inverter, at least 18 transistors are required for each and there is a problem that the number of elements is large. In addition, D
The type flip-flop 7 is an update flip-flop and can be replaced with a D-type single latch, but this D-type single latch requires at least 10 transistors, and the number of elements is still large. There is.

Next, a conventional verification method of the test circuit will be described. In a large-scale and complicated logic circuit, a design method called scan design is a very effective method for automatically generating a test pattern having a high fault coverage. FIG. 10 is a block diagram of the scan design circuit. The scan design is a circuit for freely setting or observing the states of the flip-flops forming the sequential circuit from the external terminal (in FIG. 10, a circuit in which flip-flops 75 ₁ , 75 ₂ , ... 75 _n are connected in series). )
In addition to the normal operation mode, the scan flip-flop operates as a shift register to set and read test data, and the test data set in the scan flip-flop and external terminals are set. In this method, the combinational circuit is operated by the test data and the output is observed at the scan flip-flop and the external terminal. Various methods have been conventionally considered for verification of a test circuit of a scan-designed logic circuit. These verification methods include connection check, loop check by path trace, synchronous / asynchronous check, and scan path. It is to check whether the connection is normal. These verification methods are intended for logic circuits that are easily testable by scan design, and conventionally there has been no method for verifying a test circuit for a logic circuit that is easily testable by a split test.

For this reason, conventionally, the verification work is performed manually, and there is a problem that the time required for the verification becomes very long and a circuit error cannot be completely prevented.

The present invention has been made in consideration of the above circumstances, and an object thereof is to provide a boundary scan cell capable of reducing the number of elements as much as possible.

The present invention also provides a test circuit verification method capable of verifying a test circuit capable of performing an operation test for each of a plurality of divided circuit blocks in the shortest possible time. With the goal.

[0009]

The boundary scan cell according to the present invention is a first multiplexer for selecting and outputting either the first input data or the second input data based on a shift mode signal. A D-type single latch that latches the output of the first multiplexer based on the first shift clock signal; a dynamic gate that dynamically holds the output of the D-type single latch based on the second clock signal; A second update latch that latches the output of the D-type single latch based on the clock signal, and a second latch that selects and outputs either the first input data or the output of the update latch based on the test mode signal And a multiplexer of.

The test circuit verifying method according to the present invention is for switching between a normal operation and an operation for performing a division test in a logic circuit to which a test circuit is added so that a test can be performed by dividing each circuit block. A first step of setting a test signal value and a signal value for selecting a circuit block to an external terminal or an internal terminal of a logic circuit, and a terminal of a circuit block to be tested when the set signal value propagates the logic value To the external terminal of the logic circuit, the second step of determining the activation condition, and backward propagation for the input terminal and forward, bidirectional for the output terminal by propagating the set signal value by the logical value. For the terminal, the circuit under test is tested from the external terminal of the logic circuit by performing path trace in forward and backward. It is possible to control whether the input signal value can be controlled with respect to the lock input terminal and whether the output signal value can be observed with respect to the output terminal of the circuit block under test. Steps,
It is characterized by having.

[0011]

According to the boundary scan cell of the present invention constructed as described above, the shift operation can be performed by the D type single latch and the dynamic gate. The total number of elements forming the D-type single latch and the dynamic gate is smaller than the number of elements of the conventional D-type flip-flop (double latch).

According to the test circuit verification method of the present invention configured as described above, the test signal value and the signal value for selecting the circuit block are the external terminal or the internal terminal of the logic circuit in the first step. Is set to the input terminal of the circuit block by propagating the logical value of the set signal value to the activation terminal of the path when the logical value of the set signal value is propagated. On the other hand, it is verified by the third step whether it is possible to control the input signal value and whether the output signal value can be observed at the output terminal.
As a result, it is possible to easily detect a mistake in the test circuit, and it is possible to significantly reduce the design period.

[0013]

FIG. 1 shows the configuration of an embodiment of the boundary scan cell according to the present invention. The boundary scan cell of this embodiment is different from the conventional boundary scan cell shown in FIG. 9 in that it has a D-type flip-flop (double latch).
6 and 7 are each replaced with a D-type single latch, and a dynamic gate 3 is newly provided.
Then, the shift clock A causes the D-type single latch 2 to operate as a master latch, and the shift clock B causes the dynamic gate 3 to operate as a slave latch, thereby performing a shift operation (two-phase operation).
Can be done.

The dynamic gate 3 operates to retain data dynamically, but there is a problem that after a certain time or more, charges are discharged and data cannot be retained. However, the shift register operation usually has a cycle of 1000 nanoseconds or less (1 MHz or more).
Since it is performed in step 3, there is no influence on the data holding operation within this time, and thus the shift register operation can be performed. Although the data of the dynamic gate 3 is lost after a lapse of a certain time after the shift register operation is completed, since the data is held in the D type single latch 2 of the master, the data is held in the D type single latch 4 for update in the subsequent stage. There is no problem to add data.

As described above, the boundary scan cell of the embodiment shown in FIG. 1 realizes the function required for the boundary scan cell.

As is well known, a D-type single latch can be composed of 10 transistors, and if a dynamic gate is realized by one transfer gate, that is, two transistors, it is shown in FIG. In the embodiment, a total of twelve transistors are required to perform the shift operation, and when eighteen transistors are required to realize the conventional D-type flip-flop 6 for performing the shift operation. The number of elements can be reduced compared to the above.

The dynamic gate 3 is not limited to the transfer gate as long as it can hold data dynamically like a transfer gate.

In the above embodiment, the D-type single latch is used as the update flip-flop, but a D-type master slave flip-flop may be used.

Next, an embodiment of the test circuit verification method according to the present invention will be described with reference to FIGS. The specific processing procedure of this embodiment is shown in the flowchart of FIG.

In FIG. 2, 11a is circuit connection information indicating the connection relationship between a plurality of circuit blocks, and 11b is a terminal indicating the attributes (input terminal, output terminal, bidirectional terminal) of the terminals of each circuit block. Attribute information, 11c is test mode setting information necessary for testing by dividing each circuit block. Here, the terminal attribute information 11b and the test mode setting information 11c will be described in detail. An example of the terminal attribute information 11b is shown in FIG. 3 (a), and an example of the test mode setting information 11c is shown in FIG. 3 (b). Each information shows the case where there are three circuit blocks A, B, and C. In FIG. 3A, for each circuit block (circuit block A, B, C), whether the attribute of the terminal is an input terminal, an output terminal, or a bidirectional terminal,
They are indicated by INPUT, OUTPUT, and IN / OUT, respectively. In the case of the circuit block A, the input terminal is AI1,
AI2, output terminals are AO1 and AO2, and bidirectional terminals are AIO1 and AIO2. In addition, FIG. 3B shows information for setting each circuit block in the test mode for each of the circuit blocks A, B, and C. For example, when testing circuit block A,
Signal value information for switching from normal operation to test operation (TEST = 1), signal value information for selecting a circuit block to be tested (AIN = 0, BIN = 0), input of bidirectional terminals of the circuit block This shows setting of control signal value information (CIN = 0, 1) for switching the output. Although only the external terminal is used for the test mode setting in FIG. 3B, the internal terminal may be used for the test mode setting information 11c. The control signal for switching the input / output of the bidirectional terminal of the circuit block will be further described with reference to FIG. In FIG. 4, the A terminal of the circuit block 21 is a bidirectional terminal, and it is necessary to switch the input and the output in order to perform both the input control of the signal and the output observation at the bidirectional external terminal B during the division test. The external terminal for switching is CIN. Input / output of the bidirectional terminal A of the circuit block 21 can be switched depending on the signal value set to the external terminal CIN. When the signal value “0” is set to the external terminal CIN (see FIG. 4A), it becomes possible to input a signal from the external terminal B to the bidirectional terminal A of the circuit block 21 (from the external terminal B). The path to the bidirectional terminal A of the circuit block 21 is activated), and the signal value "1" is applied to the external terminal CIN.
When set to (see FIG. 4B), the circuit block 2
A signal can be output from the bidirectional terminal A of No. 1 to the external terminal B (the path from the bidirectional terminal A of the circuit block 21 to the external terminal B is activated). This external terminal CI
The information set to N is the information of the control signal value for switching the input / output of the bidirectional terminal of the circuit block, and is shown as CIN = 0, 1 in FIG. 3B. Incidentally, reference numeral 25 in FIG. 4 is an input buffer.

Returning again to the flowchart of FIG. In the process 12 of reading the setting information, the circuit connection information 1 described above
1a, terminal attribute information 11b and test mode setting information 11
Read c.

After the setting information reading process 12, the test circuit verification process 13 is performed. The process executed in the test circuit verification process will be described in detail for the logic circuits of FIGS. 5 and 6. . FIG. 5 is a logic circuit diagram in which a test circuit is added so that a test can be performed by dividing each circuit block. The logic circuit in FIG. 5 is a logic circuit using a multiplexer and is an example of a logic circuit targeted by the test circuit verification method of the present embodiment. Although a division test using a multiplexer is general, detailed description thereof will be omitted, but in the circuit block A in FIG. 5, the multiplexer 36 controls the signal input to the input terminal of the circuit block A by the external terminal 39 ₂ . Therefore, the multiplexers 32, 34 and 37 are added to observe the signals output from the output terminals of the circuit block A at the external terminals 40 ₁ and 40 ₂ . The multiplexer 32 selects two input signals by the control terminal TSTB, the multiplexers 34 and 36 by the control terminal TSTA, and the multiplexer 37 by the control terminal TST.
Select by C. Therefore, in order to perform the division test, it is necessary to determine the logical value of this control terminal. The determined logical value of the control terminal becomes a condition value for activating a path from the circuit block terminal to the external terminal in the division test. Figure 6
Is a decoder circuit for selecting a circuit block, is a test circuit for determining the logical value of the control terminals (TSTA, TSTB, TSTC) of the multiplexer in FIG. 5, and uses the decoder circuit 45. In FIG. 6, TEST, AIN and BIN are external terminals for setting the test mode setting information,
Through the decoder circuit 45, control terminals (TSTA, TSTB, TSTC) of a plurality of multiplexers are controlled.

The test circuit verification process 13 will be described below in order. In the test circuit verification process 13, first, a circuit block to be tested is selected, and the test mode setting information of the selected circuit block is set to a specified external terminal or internal terminal. This process is the test mode setting process 14 in FIG. The circuit block to be tested may be selected in any manner as long as all circuit blocks can be sequentially selected, but in the present embodiment, the circuit blocks are selected according to the order described in the test mode setting information 11c. If FIG. 3B shows the test mode setting information 11c, the circuit block selected first as the test target is the circuit block A in FIG. 5, the circuit block B is next, and the circuit block C is next. Is. When the test mode setting information of the circuit block A in FIG. 3B is designated to the external terminals TEST, AIN, and BIN of FIG. 6, 1 is given to the external terminal TEST, “0” is given to AIN, and “0” is given to BIN. Will be set. Further, the test mode setting information 11c includes signal value information for switching the input and output with respect to the bidirectional terminals of the circuit block, and the setting of this signal value information is also performed by the test mode setting processing 14. Run. However, since there is a signal value setting for switching to input and a signal value setting for switching to output, the test mode setting process 14 is executed twice. Hereinafter, these two settings will be referred to as an input mode setting and an output mode setting, respectively.

Next, a logic value propagation process 15 for propagating the test mode setting information 11c set in the external terminal or the internal terminal in the test mode setting process 14 to the inside of the circuit is executed. In the test mode setting process 14, when the circuit block A is the test target, TEST = 1, AIN = 0, and BIN = 0 are set in FIG. In the logical value propagation processing 15, the external terminals TEST, AI
Processing for sequentially propagating the logical values set in N and BIN is performed.

The logical value set in the external terminal TEST is sent to the AND circuits 48 ₁ , 48 ₂ and 48 ₃ in the decoder circuit 45 via the input buffer 43 ₁ . Further, the logical value set to the external terminal AIN is sent to the inverter circuit 46 ₁ in the decoder circuit 45 via the input buffer 43 ₂ and further to the AND circuits 48 ₁ and 48 ₃ and the inverter circuit 47 of the decoder circuit 45. _It is sent to the AND circuit 48 ₂ via ₁ . The logical value set in the external terminal BIN is sent to the inverter circuit 46 ₂ of the decoder circuit 45 via the input buffer 43 ₃ and further to the AND circuits 48 ₁ and 48 ₂ and the inverter circuit 47 _{2 of the} decoder circuit 45. Through the AND circuit 48
Sent to ₃ . The output of the AND circuit 48 ₁ is sent to the control terminal TSTA, the output of the AND circuit 48 ₂ is sent to the control terminal TSTB, and the output of the AND circuit 48 ₃ is sent to the control terminal TSTC. When the set logical value is propagated, TSTA = 1, TSTB = 0, TSTC = 0 when the circuit block A is tested.

After performing the logic value propagation processing 15, both the path from the input terminal of the circuit block to the external terminal, the path from the output terminal of the circuit block to the external terminal, and the circuit block for the circuit block to be tested. A path search (also referred to as path trace) processing 16 is performed to check whether all the paths from the facing terminal to the external terminal are activated and the input signal or the output signal can be controlled or observed. In FIG. 5, the control terminal (TS
If all the logical values (TA, TSTB, TSTC) propagate correctly and all the paths from the terminals of the circuit block to be tested to the external terminals are activated, the test circuit can be determined to be normal. To check whether or not the correct logic value has propagated to the control terminal of the multiplexer and the path between the circuit block terminal and the external terminal is active, all terminals in the circuit block under test are path traced and checked one by one. I will do it. In the logic circuit shown in FIG. 5, the path trace processing 16 will be described for the case where the circuit block A is the test target. In the circuit block A, there are 6 terminals in total, and
2 is an input terminal, AO1, AO2 are output terminals, AIO1,
AIO2 is a bidirectional terminal. Path trace processing 16
Since the processing method differs depending on the attributes of the input terminal, the output terminal, and the bidirectional terminal, the processing method will be described below for each attribute.

First, the path trace processing of the input terminal will be described. A path trace will be made using the terminal name AI1 as an example. AI
The logic circuit without the connection circuit for the terminal 1 is shown in FIG.
Is. FIG. 7A shows a logical value propagation situation when the logical value of the control terminal (TSTA) of the multiplexer is “1”. The signal value of X represents indefinite. Further, FIG. 7B shows a logical value propagation situation when the logical value of the control terminal (TSTA) of the multiplexer is “0”. First, the path trace process will be described in the case of FIG. Terminal A of circuit block A
Since the path from I1 is TSTA = 1, the NAND circuit 36d of the multiplexer circuit 36 → the NAND circuit 36a.
→ The path of the external terminal 39 ₂ is activated and the external terminal 39 ₂ is activated.
It is possible to control the input signal from the circuit block to the circuit block. However, as shown in FIG. 7B, when the logical value of the control terminal of the multiplexer circuit 36 is TSTA = 0, which is the reverse of that in FIG. 7A, the multiplexer circuit 36
The NAND circuit 36d → the NAND circuit 36c → the circuit block C passes, and control from the external terminal cannot be performed. Therefore, in this case, the test circuit is missed. In the path trace processing at the input terminal, the paths are sequentially searched in the order opposite to the signal flow from the input terminal of the circuit block.
Like the AI1 terminal of the circuit block A in (a),
This is a backward path trace processing because it is a processing to check whether the path is activated to the external terminal. In FIG. 7, reference numeral 50 is an input buffer.

Next, the path trace processing of the output terminal of the circuit block will be described. The path trace is made by taking the AO1 terminal of the circuit block A in FIG. 5 as an example. FIG. 8 shows a logic circuit in which a connection circuit related to the terminal of AO1 is extracted.
FIG. 8A shows a control terminal (T
FIG. 8B shows a logical value propagation situation when the logical value of STC) is “0”, and FIG. 8B shows a case where the logical value of the control terminal (TSTC) of the multiplexer is “1”. It shows a logical value propagation situation. First, the path trace process will be described in the case of FIG. Since the path from the terminal AO1 of the circuit block A is TSTC = 0, the path of the NAND circuit 37c of the multiplexer circuit 37 → the NAND circuit 37d → the external terminal 40 ₂ is activated,
The output signal from the circuit block can be observed at the external terminal 40 ₂ . However, as shown in FIG. 8B, the logical value of the control terminal of the multiplexer is
When TSTC = 1, which is the opposite of the above, since the NAND circuit 37c of the multiplexer circuit 37 cannot proceed further, the path trace processing is stopped here and observation at the external terminal cannot be performed. Therefore, in this case, the test circuit is missed. In the path trace processing at the output terminal, the paths are sequentially searched from the output terminal of the circuit block along the signal flow, and the AO of the circuit block A in FIG.
Since this is a process for checking whether a path is activated up to an external terminal like one terminal, it is a forward path trace process. In FIG. 8, reference numeral 51 is an output buffer.

Finally, the path trace processing of the bidirectional terminals of the circuit block will be described. The bidirectional terminal performs both backward path trace processing performed at the input terminal and forward path trace processing performed at the output terminal (the bidirectional terminal functions as an input terminal and as an output terminal). Because it is a terminal with a function). However, the input mode setting process is performed before the backward path trace process, and the output mode setting process is performed before the forward path trace process. The method of backward path trace processing and the method of forward path trace processing are the same as the processing methods described above.

The path trace processing 16 explained above
Are sequentially executed for all terminals of the circuit block, and the test circuit is verified for any errors.

When the test circuit verification process is completed for one test target circuit block, the next test target circuit block is selected and the test circuit verification process is repeatedly executed for all the circuit blocks.

When the test circuit verification process is completed for all the circuit blocks, the result output process 18 for outputting the test circuit verification result as information is finally executed (see FIG. 2). The result output processing 18 outputs verification result information 19 indicating which terminal of which circuit block has a test circuit error, where the test circuit error has occurred, and the like.

By executing the processing according to the processing flow shown in FIG. 2, the test circuit verification can be performed on the logic circuit to which the test circuit is added so that the test can be performed by dividing the circuit block.

[0034]

According to the boundary scan cell of the present invention, the number of elements can be reduced as compared with the conventional case.

Further, according to the test circuit verification method of the present invention, it is possible to easily detect a mistake in the inserted test circuit, so that the design period can be greatly shortened.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of a boundary scan cell according to the present invention.

FIG. 2 is a flowchart showing a specific procedure of a test circuit verification method according to the present invention.

FIG. 3 is an explanatory diagram illustrating a specific example of terminal attribute information and test mode setting information according to the present invention.

FIG. 4 is a logic circuit diagram illustrating that input / output of a circuit block bidirectional terminal is switched by a control signal.

FIG. 5 is a block diagram illustrating an example of a logic circuit tested according to the present invention.

FIG. 6 is a circuit diagram of a decoder for selecting a circuit block to be tested.

FIG. 7 is a logic circuit diagram for explaining backward path trace processing.

FIG. 8 is a logic circuit diagram for explaining forward path trace processing.

FIG. 9 is a block diagram showing a configuration of a conventional boundary scan cell.

FIG. 10 is a schematic diagram showing a configuration of a conventional scan design circuit.

[Explanation of symbols]

 1 Multiplexer 2 D type single latch 3 Dynamic gate 4 D type single latch 8 Multiplexer

Claims (2)

[Claims] 1. A first multiplexer for selecting and outputting either one of the first input data or the second input data based on a shift mode signal, and the first multiplexer based on a first shift clock signal. A D-type single latch that latches the output of the first multiplexer, a dynamic gate that dynamically holds the output of the D-type single latch based on a second clock signal, and the D-type single latch based on an update clock signal Update latch for latching an output of the update latch, and a second multiplexer for selecting and outputting either the first input data or the output of the update latch based on a test mode signal. Boundary scan cancellation characterized by being present. 2. In a logic circuit to which a test circuit is added so that a test can be performed by dividing each circuit block, a test signal value for switching between a normal operation and an operation for performing a division test and the circuit block are selected. A first step of setting a signal value to the external terminal or the internal terminal of the logic circuit, and from the terminal of the circuit block to be tested to the external terminal of the logic circuit when the set signal value propagates the logic value. A second step of determining a condition for activating the path up to, and a backward value for an input terminal, a forward value for an output terminal, a forward value for a bidirectional terminal, and a forward value by propagating a logical value of the set signal value. By performing path trace in backward, from the external terminal of the logic circuit to the input terminal of the circuit block under test. A third step of verifying that it is possible to control the input signal value, and whether the output signal value can be observed at the output terminal of the circuit block under test. A method of verifying a test circuit, which is characterized in that