JPH05209935A - Lsi device and lsi test method - Google Patents

Abstract

PURPOSE:To provide an LSI device and a LSI test method which can be tested with a loss clock number so as to shorten the test time. CONSTITUTION:In an LSI device, a plurality of flip-flops FF1 to FFn,..., FF1 to FFn are divided so as to be allocated to respective units U1 to Um of LSI. In each of the units U1 to Um, a scan-out terminal Sout of a certain flip-flop FFj is connected to a scan-in terminal Sin of a next stage flip-flop FF(j+1). Further, the scan-in terminal Sin and scan-out terminal Sout of the uppermost stage flip-flop FFn are connected respectively to an external scan-in terminal Si and an external scan-out terminal So so that scan paths Spath1 to Spathm are individually constituted for the units U1 to Um, respectively, and further, control circuits 18, 20 for selecting any one of the units U1 to Um are included.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION The present invention relates to an LSI device and an LSI.
Regarding the test method of. As a method for facilitating the LSI test, there is a method in which a flip-flop (hereinafter referred to as FF) inside the LSI is of a scan type and a plurality of FFs are connected in series to form a sequential circuit. This kind of LS
In I, the contents of the FF in the middle of execution are read out to the LS.
The I test can be performed, or the LSI can be tested by directly writing data in the FF.

When performing an LSI test as described above, it is necessary to supply a clock signal having a number of clocks equal to the number of FFs to the LSI, and the number of FFs increases as the size of the LSI increases. , The number of clocks has increased,
Therefore, the time required to test the LSI becomes long. Therefore, it is desired to shorten the test time of the LSI.

[0003]

2. Description of the Related Art FIG. 2 shows an example of a scan type D-FF. D-FF is a selector 10 and D
-It is composed of the FF main body 12, and the test signal T is in the non-asserted state during normal operation (non-test).
The selector 10 selects the signal D and supplies it to the D terminal of the D-FF main body 12. The D-FF main body 12 takes in the signal D at the timing of the clock CK and outputs it from the terminal Q. On the other hand, since the test signal T is asserted during the test, the selector 10 selects the scan-in signal S _in and supplies it to the D terminal of the D-FF main body 12. The D-FF main body 12 takes in the scan-in signal S _in at the timing of the clock CK and outputs it from the terminal Q. In addition, terminal Q
The output from is the normal output Q and the scanout signal S
It is used as _out.

Next, FIG. 3 shows a conventional LSI using the scan type FF shown in FIG.
The LSI includes a first combinational circuit 12, a second combinational circuit 16, and n flip-flops FF1 to FFn arranged between the circuits 14 and 16 and connected in series. The input IN is supplied to the circuit 14, and the circuit 1
From 6, the output OUT is output. Below, FF1-F
Fn will be described.

Each of FF1 to FFn is composed of a selector and a D-FF main body, as shown in FIG.
The scan-in terminal S _in of the uppermost FF1 is connected to the external scan-in terminal S _i , the scan-out terminal S _out of the FF1 is connected to the scan-in terminal S _in of the next FF2, and so on. The scan-out terminal S _out of the FF (n−1) is connected to the scan-in terminal S _in of the bottom FFn, and the scan-out terminal S _out of the FFn is connected to the external scan-out terminal S _o. It The path of S _in → S _out → S _in → S _out → ... Is referred to as a _{scan path} S _path .

A test signal T and a clock CK are supplied to the FF1 to FFn. Further, the output terminals O ₁ , O ₂ , -O _n-1 , and O _n of the first combinational circuit 14 are connected to the D terminals of FF1 to FFn, respectively.
The Q terminals of FFn are respectively connected to the second combination circuit 16
Are connected to the input terminals I ₁ , I ₂ , to I _n-1 , I _n .

In the above LSI, during normal operation (non-test), the first combinational circuit 14 operates according to the input IN from the outside, and the result is output terminal O ₁ ,
Output from O ₂ , -O _n-1 , and O _n . Here, FF1
Since the test signal T is in the non-asserted state in FF2,
Output terminals O _1, O ₂ of circuit 14, ~ O output from the _n-1, O _n (latched) incorporation at the timing of the clock CK, respectively, the input terminal I of the second combinational circuit 16
_1, I _2, and supplies the ~I _n-1, I _n. As a result, the second combination circuit 16 operates and outputs the result to the output OUT.
When the output OUT from the second combinational circuit 16 that is output as the above is different from the expected value, which one of the circuit 14 and the circuit 16 has failed, or the circuit 14 or the circuit 1 is defective.
It is necessary to judge whether both 6 are out of order. Therefore, the scan type FF1 to FFn are used to determine which circuit has a failure. Hereinafter, a procedure for determining a failure will be described.

First, the determination of the failure of the first combination circuit 14 will be described. The circuit 14 is operated according to the normal input IN from the outside, and the clock CK is supplied to FF1 to FFn.
Now that one cycle supply, asserting a test signal T, the output of the output terminal O ₁ ~ O _n circuit 14, respectively, are set to FF1 to FFn. After that, when the clock CK is supplied to FF1 to FFn,
The contents of FFn to FF1 are sequentially output to the external scan-out terminal S _o along the scan _path S _path . Then, by looking at the output of the external scan-out terminal S _o , it is possible to determine whether or not the first combinational circuit 14 is out of order.

Next, the determination of the failure of the second combination circuit 16 will be described. While asserting a test signal T, and supplies a clock CK to FF1 to FFn, and at the same time, the input terminal I _n ~I 1 cycle normal input ₁ from the external scan-in terminal S _i of the second combinational circuit 16 Supply each. As a result, the input terminals I _n to
The normal input of I ₁ is sequentially set in FFn to FF1 along the scan _path S _path . The second combination circuit 16 operates according to the normal inputs set in the FFn to FF1 in this way, and outputs the result to the external output OUT.
Output as. Then, by looking at this external output OUT, it is possible to determine whether or not the second combination circuit 16 is out of order.

As described above, in the LSI of FIG.
By by operating the circuit 14 in accordance with the normal input IN from the outside see the output of the external scan-out terminal S _o, it is possible to determine the failure of the circuit 4, also, the external scan-in terminal S _i the normal input It is possible to judge the failure of the circuit 16 by supplying the external output OUT to the circuit 16 and observing the external output OUT.

[0011]

Usually, an LSI can be functionally divided into a plurality of units, and a scan test for whether or not a certain unit has a failure is performed by relating to that unit. All you have to do is focus on the FF. However, as shown in FIG. 3, when all the FFs are connected in a line, when it is desired to test the scan located in the vicinity of the external scan-in terminal S _i (for example, the unit to which FF1 belongs) by scan reading, Before the content of FF1 is output to the external scan-out terminal S _o , the number of clocks is required by the number of FF2 to FFn (n−1) of other units. When a unit located near the external scan-out terminal S _o (for example, a unit to which FFn belongs) is to be tested by scan writing, by the time the write content reaches from the external scan-in terminal S _i to FFn, Other units FF1 to FF (n-1)
The number of clocks is required by the number (n-1) of

Here, if the LSI is small,
Since the number of FFs is small, the number of clocks required for scan reading and scan writing is small, but the number of FFs used increases as the LSI becomes large, so the number of clocks required for scan reading and scan writing of all FFs. Will increase. Therefore, there is a problem that the time required for testing the LSI becomes long.

An object of the present invention is to carry out a test with a small number of clocks and shorten the test time.
It is to provide a test method for an apparatus and an LSI.

[0014]

An LSI device according to the present invention includes a plurality of scan type flip-flops (FF1).
To FFn, ..., FF1 to FFn), the plurality of flip-flops (FF1 to FFn,
..., FF1 to FFn) are divided and LSI units (U
1 to Um), and each of the units (U1 to Um)
m), the scan-out terminal (S _out ) of a certain flip-flop (FFj) is connected to the next flip-flop (F _out ).
F _{(j + 1)} ) scan-in terminal (S _in ), and the scan-in terminal (S _in ) of the uppermost flip-flop (FF1) and the lowermost flip-flop (F _in )
The scan-out terminals (S _out ) of Fn) are
It is connected to the external scan-in terminal (S _i ) and the external scan-out terminal (S _o ), and the scan paths (S _path 1 to S _path m) are separately configured for each unit (U 1 to Um). And the plurality of units (U1 to
Um) control circuit (18, 2)
0) is included.

Further, according to the LSI test method of the present invention, a plurality of scan type flip-flops (FF1) are used.
To FFn, ..., FF1 to FFn) and scan L
In the method of performing SI test, the plurality of flip-flops (FF1 to FFn, ..., FF1 to FFn) are divided and assigned to each unit (U1 to Um) of the LSI, and each unit (U1 to Um) external scan-in terminal (S _o) from through the unit (U) a flip-flop in the (FF1 to FFn) leading to the external scan-out terminal (S _o) scan path (S _path 1~S _path
m) separately prepared, and the plurality of scan paths (S _path)
1 to S _path m) are separately used for LSI
Is tested for each unit (U1 to Um).

[0016]

In the present invention, when the LSI is tested, the target unit (Uj) is selected from the plurality of units (U1 to Um), and the scan _path (S _path ) belonging to the target unit (Uj) is selected. j) using the unit (U
Perform the test of j). That is, the target unit (U
By scanning the unit (Uj) using the scan _path (S _path j) belonging to j), the scan reading and the scan writing are performed by the unit (U) alone. Since the number of FFs in one unit (U) is smaller than the number of FFs in all units (U1 to Um) of the LSI, the target unit (Uj) can be tested with a small number of clocks. it can.

[0017]

Embodiments of the present invention will be described below with reference to the drawings. FIG. 1 shows an LSI according to an embodiment of the present invention using a scan type FF.

The LSI is composed of a plurality of units U for each function.
1, U2-Um, for example, the first unit U1
Is an adder, the second unit U2 is a multiplier, ... The m-th unit Um is an arithmetic unit. The first unit U1 includes n flip-flops FF1 to FFn connected in series,
Each of FF1 to FFn is composed of a selector and a D-FF main body as shown in FIG. The scan-in terminal S _in of the uppermost FF1 is connected to the external scan-in terminal S _i and the scan-out terminal S in of the FF1 is connected.
_out is connected to the scan-in terminal S _in of the FF2 at the next stage, and so on, and the scan-out terminal S _out of FF (n−1) is connected to the scan-in terminal S _in of the FFn at the bottom stage. The scan-out terminal S of the FFn
_out is connected to the external scan-out terminal S _o . Then, the route of S _in → S _out → S _in → _{Sou t} → ...
This is called the first _{scan path} S _path 1. The second unit U2 to the m-th unit Um are the same as the first unit U1.
And the second scan path S.
_path 2 to mth _{scan path} S _path m.

As described above, the scan paths S _path 1 to S _path m are separately arranged for each of the units U1 to Um, and one end of each of the scan paths S _path 1 to S _path m is a common external scan-in. The other end is connected to the common external scan-out terminal S _o .

In the first unit U1, FF1 to FF1
The D terminal of FFn is connected to the input side circuit (not shown but corresponds to the circuit 14 of FIG. 3), and the Q terminals of FF1 to FFn are output side circuits (not shown but corresponding to the circuit 16 of FIG. 3). The second unit U2 to the m-th unit Um include an input-side circuit and an output-side circuit, like the first unit U1. In addition, in the units U1 to Um,
The clock CK is supplied, the LSI is supplied with a normal input IN, and the LSI outputs a normal output OUT.

The LSI includes a test control circuit 18 and a selector 20. The test control circuit 18 uses the test input T
_{According to est} , the test signal T and the scan path select signal S are generated, the test signal T is supplied to the units U1 to Um, and the scan path select signal S is supplied to the selector 20. In the units U1 to Um, FF1 to FFn, ..., FF1 to FFn according to the test signal T.
Mode is selected, that is, FF1 to FFn, ...,
It is selected whether FF1 to FFn are in the normal operation mode or the test mode. Also, the selector 20
Are units U1 to Um and external scan-out terminal S _o
And the scan path select signal S
According to the above, any one of the units U1 to Um is selected, and the scan _path S _path j of the selected unit Uj is selected.
Scan out output from the external scan out terminal S
supply to _o .

The operation of the LSI shown in FIG. 1 will be described below. First, during normal operation (non-test), the test control circuit 1
Since the test signal T from 8 is in the non-asserted state, FF1 to FFn, ..., FF1 to F in the units U1 to Um.
Fn is the normal operation mode. As a result, the unit U1
~ Un performs a normal operation, that is, the LSI receives a normal input IN and outputs a normal output OUT.

Next, at the time of testing, the test control circuit 18
, The FF1 to FFn, ..., FF1 to FFn in the units U1 to Um.
Is a test mode. Further, according to the scan path select signal S from the test control circuit 18, the unit U1
Among Um to Um, one of the units to be tested is selected, for example, the first unit U1.

In the above state, the scan read test
In the strike, the unit is input according to the normal input IN from the outside.
U1 to Um operate and scan units of the units U1 to Um
Space S _path1-S_pathThe scan-out output from m is
It is supplied to the rector 20. Here, for example, the first unit
If U1 is selected, the selected first unit
Scan path S of Ut1_pathScan out from 1
Output is external scan-out terminal S_oIs supplied to
The failure of the first unit U1 is tested.
Becomes

In the scan write test, the normal input is the scan path S from the external scan-in terminal S _in.
It is supplied to the units U1 to Um through the paths 1 to S _path m, and the units U1 to Um operate. Then, the output OUT from the target unit, for example, the first unit U1
By looking at, the failure test of the first unit U1 is performed. The external scan-in terminal S _in
The normal input from the unit is supplied to all the units U1 to Um, but the unit U2 other than the unit under test U1.
-Um may be ignored (Don't care).

As described above, in the LSI of FIG.
It is possible to perform scan reading and scan writing for each one unit Uj of the units U1 to Um, and perform a failure test for each unit Uj.

[0027]

As described above, according to the present invention,
Since a scan path is provided separately for each unit,
It is possible to perform a failure test for each unit by focusing on only the target unit. Therefore, the number of clocks required for the test is smaller than that in the case of testing the entire LSI, so that the test time can be shortened. This is particularly effective when testing a large-scale LSI that uses a large number of FFs.

[Brief description of drawings]

FIG. 1 is a configuration explanatory diagram of an LSI according to an embodiment of the present invention using a scan type FF.

FIG. 2 is an explanatory diagram of a configuration of a scan type D-FF.

FIG. 3 is a configuration diagram of a conventional LSI using a scan type FF.

[Explanation of symbols]

18 ... Test control circuit 20 ... Selector U1-Um ... Unit FF1-FFn ... Flip-flop S _path 1-S _path m ... Scan _path

 ─────────────────────────────────────────────────── ─── Continued Front Page (72) Inventor Tatsuya Nagasawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa Fujitsu Limited

Claims (2)

[Claims] 1. An LS including a plurality of scan-type flip-flops (FF1 to FFn, ..., FF1 to FFn).
In the I device, the plurality of flip-flops (FF1 to FFn, ..., F
F1 to FFn are divided into LSI units (U1 to U)
m), and in each of the units (U1 to Um), the scan-out terminal (S _out ) of a certain flip-flop (FFj) is the scan-in terminal (S _out ) of the next-stage flip-flop (FF _{(j + 1)} ). S _in ), and the scan-in terminal (S _in ) of the uppermost flip-flop (FF1) and the scan-out terminal (S _out ) of the lowermost flip-flop (FFn) are respectively external scan-in terminals. (S _i ) and the external scan-out terminal (S _o ), and the scan path (S 1) is connected to each unit (U1 to Um).
_path 1 to S _path m) are separately configured, and the control circuit (18, 20) for selecting any one of the plurality of units (U1 to Um) is included. apparatus. 2. A method for testing an LSI by scanning a plurality of scan-type flip-flops (FF1 to FFn, ..., FF1 to FFn), wherein the plurality of flip-flops (FF1 to FFn ,.
F1 to FFn are divided into LSI units (U1 to U)
m) assigned to each, the in each unit (U1 to UM), the external scan-in terminal (S _o) from through the flip-flops (FF1 to FFn) in the unit (U) external scan out terminal (S _o) Connected scan paths (S _path 1-S
_path m) is separately prepared, and one of the plurality of scan paths (S _path 1 to S _path m) is separately used to test the LSI for each unit (U 1 to Um). LSI test method.