JPH05334116A - Debugging control system - Google Patents

Abstract

PURPOSE:To remove influence from a circuit other than a diagnostic object and to facilitate debugging by protecting diagnostic data in a debugging control system of an information processor. CONSTITUTION:When a flag 5 is set up to a diagnostic data protection mode by a control instruction applied from a diagnostic device 1 and '1' is set up in the 0th bit e.g. of a mask register 36, an input C00 from a logic circuit 20 for an AND gate 60 corresponding to the 0th bit is inhibited and data setting from the circuit 20 to the register 30 is inhibited. When '1' is similarly set up in the 1st bit of the register 36, data setting from a logic circuit 21 to a register 31 is inhibited. Thus, data set from the logic circuit to the register can be selectively inhibited.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a debug control system for an information processing device.

[0002]

2. Description of the Related Art Conventional debugging of an information processing apparatus writes diagnostic data from a diagnostic apparatus to a register used in normal data processing, advances a clock, and then registers the value of a register of a circuit to be debugged. Is read. Therefore, in the conventional debug control method, for multiple registers used in normal data processing,
Having a data writing means by a control instruction of the diagnostic device,
Utilizing this, the execution of the information processing device is debugged.

FIG. 3 shows a conventional debug control system.
As a means for writing to the register, a method of using a scan path of a flip-flop chain configured in the information processing device (hereinafter referred to as a scan path method) and a method of writing data from a common data path by designating an address (hereinafter The case of using the addressing method) is also shown. In FIG. 3, the information processing device to be diagnosed is the part excluding the diagnostic device 1, and the logic circuits 20 to 3
0, registers 30 to 35, and a decoder 4.
However, although the logic circuits 20 to 23 are shown independently for convenience of illustration, they are originally indivisible circuits. During normal processing, the data paths D01 to D02, D05 to D06, D11 to D1 are transferred from the logic circuits 20 to 23 to the registers 30 to 35.
Data is written via 2 via a write instruction of the data set signals C00 to C05. Registers 30-35
The value of is the data path D03-D04, D07-D10, D
It is read to the logic circuits 20 to 23 via 13 to D14.

When data is written in accordance with a control instruction from the diagnostic device 1 by the scan path method, all the target registers in the information processing device are configured as one flip-flop chain, and a scan-dedicated clock is applied. By performing the shift operation, scan-in data from the diagnostic device is sequentially written. However, the normal clock must be stopped during the scan operation. In FIG. 3, S0 is scan-in data from the diagnostic device 1, and S1 to S6 are registers 30 to.
A scan path connecting 35. S7 is the diagnostic device 1
Is scan-out data for and is used for reading data.

In FIG. 3, D00 is a common data path from the diagnostic device 1, and A0 is an address for designating a register for writing diagnostic data and a write instruction. C06
.About.C09 are diagnostic data set signals for the registers 30, 31, 34, and 35, and an address from the diagnostic device is decoded by the decoder 4, and designated by a write instruction via C06 to C09 which are output signals of the decoder 4. A write instruction to the registered register is issued. Of the registers 30, 31, 34, and 35, data on the common data path is written to the register that receives the write instruction. In the case of the addressing method, it is not necessary to stop the normal clock when writing the diagnostic data.

When debugging is performed by using the scan path method for writing the diagnostic data, the diagnostic data is written in advance and the normal clock is freely run to check the operation of the information processing apparatus, or the information processing apparatus is clocked. If you set the step state and write data,
Check the operation of the target circuit by repeating the advance of several clocks. How to investigate is not directly described because it is not directly related to the present invention, but normally, the diagnostic device is provided with a means for reading out the register or the like of the target device, so that means can be used or a logic analyzer or the like can be used. To use.

The case of using the addressing method for writing the diagnostic data is almost the same as the case of the scan path, but it is not necessary to stop the normal clock at the time of writing the diagnostic data, so that the debugging can be flexibly performed.

[0008]

In the conventional debug control method described above, the register in which the diagnostic data is written may be overwritten from the data path of the normal process. Therefore, the conventional debug control system has a drawback in that it is not easy to set and fix diagnostic data in a target register at a necessary timing.

[0009]

According to a first aspect of the invention, an initial value is set from a diagnostic device to a plurality of registers used in normal data processing of an information processing device by using a data writing means such as a scan path. In the debug control method for debugging the information processing device, a diagnostic data protection mode that can be set by a control instruction of the diagnostic device is provided, and when the diagnostic data protection mode is set, a predetermined register is set to the register. It is characterized by further comprising register write prohibiting means for prohibiting data setting from the information processing device.

The second aspect of the invention is to set the diagnostic data protection mode from the diagnostic device only when there is no logical connection between the information processing device to be diagnosed and another information processing device. The feature is that it is possible.

A third aspect of the invention comprises a mask register having bits corresponding to the register, in which data is set by the data writing means, and the content of the mask register is set to "1". It is characterized in that it has the register write prohibition means for enabling the diagnostic data protection mode only for the register corresponding to a bit.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings. FIG. 1 is a block diagram of an embodiment of the present invention.
The present invention is applied to the information processing apparatus of FIG. Therefore, regarding each part in FIG. 1, only differences from FIG. 3 will be described.

In FIG. 1, a flag 5 is a flag register indicating a diagnostic data protection mode and is set by a control instruction C10 from the diagnostic device 1. AND gate 60
Is the data set signal C00 of the register 30 and the output signal C of the flag register 5 during the normal processing from the logic circuit 20.
11 is input and the logical product of the negation of C11 and C00 is output. Similarly, the AND gate 61 outputs the data set signal C01 of the register 31 from the logic circuit 20 during the normal processing.
And the output signal C11 of the flag register 5 as input, and C1
The logical product of the negation of 1 and C01 is output. Register 30,
31 is the output signals C12, C1 of the AND gates 60, 61
The values on the data paths D01 and D02 are written with 3 as a set signal.

Although the register 30 and the register 31 are selected as the registers to be controlled by the flag register 5 in the present embodiment, the description will proceed, but other registers may be used.

Therefore, when the value of the flag register 5 is "1", that is, when the diagnostic data protection mode is set, the outputs of the AND gates 60 and 61 are always "0", and therefore on the data paths D01 and D02. The value of is never written.

In the present embodiment, even when the diagnostic data protection mode is set, the writing of diagnostic data by a control instruction from the diagnostic device is effective in both the scan path system and the addressing system.

When a plurality of information processing devices are connected to each other,
When configuring one system, it is desirable that the information processing device to be diagnosed is logically separated from other information processing devices when diagnosing a specific information processing device therein. Therefore, the diagnostic device usually has an interface valid flag indicating that the interface between the device to be diagnosed and another device is valid (not shown). It is possible to prevent erroneous operation by controlling the diagnostic data protection mode to be effective under the condition that this flag is “0” and logically separated from other information processing devices.

FIG. 2 shows a diagnostic device 1 in the embodiment of FIG.
Mask register 3 writable by control instruction from
It is the block diagram shown about the case where it equipped with 6. Therefore, regarding the respective parts on FIG. 2, only the differences from FIG. 1 will be described.

In FIG. 2, C16 is a mask register 36.
When the address on A0 from the diagnostic device 1 is decoded by the decoder 4 and the address specifies the mask register 36, the decoder 4 is instructed by the write instruction on A0. A write instruction to the mask register 36 is issued via the output signal C16. Mask register 36
Is a 2-bit register, and the data set signal C16
The data on the common data path D00 is written. The AND gate 62 outputs the output signal M0 of bit 0 of the mask register 36 and the output signal C11 of the flag register 5.
Is input and the logical product of M0 and C11 is output. Similarly, the AND gate 63 receives the bit 1 output signal M1 of the mask register 36 and the output signal C11 of the flag register 5, and outputs a logical product of M1 and C11. The AND gate 60 is used for register 3 from the logic circuit 20 during normal processing.
The data set signal C00 of 0 and the output signal C12 of the AND gate 62 are input, and the logical product of the negation of C12 and C00 is output. Similarly, the AND gate 61 is connected to the logic circuit 2
The data set signal C01 of the register 31 under normal processing from 1 and the output signal C13 of the AND gate 63 are input, and the logical product of the negation of C13 and C01 is output. The registers 30 and 31 are output signals C1 of the AND gates 60 and 61.
4, C15 as a set signal and data paths D01, G0
The value above 2 is written.

Therefore, even when the value of the flag register 5 is "1", that is, even when the diagnostic data protection mode is set, the diagnostic data protection mode for the register 30 has the bit of the corresponding mask register 36, that is, bit 0. It is not valid unless it is "1". Similarly, register 31
Also, the diagnostic data protection mode for is not effective unless the bit of the corresponding mask register 36, that is, bit 1 is "1". When the diagnostic data protection mode is set and the value of bit 0 of the mask register 36 is "1", the output of the AND gate 62 is "1" and the output of the AND gate 60 is "0". The value on the data path D01 is not written in 30. Similarly, when the diagnostic data protection mode is set and the value of bit 1 of the mask register 36 is "1", the AND gate 6
The output of 3 is "1" and the output of the AND gate 61 is "0"
Therefore, the value on the data path D02 is not written to the register 31.

Thus, the mask registers 36 and A
By providing the ND gates 62 and 63, the register 3
The diagnostic data protection mode for 0, 31 can be selectively enabled.

[0022]

As described above, according to the present invention, in the debug control system of the information processing apparatus, by providing the diagnostic data protection mode, it becomes possible to protect the preset diagnostic data, and the circuit which is not the object of diagnosis. There is an effect that the circuit to be diagnosed can be easily debugged without being affected by.

Further, it is possible to prevent an erroneous operation by validating the control instruction for setting the diagnostic data protection mode depending on the operating state of the information processing apparatus.

Further, by providing the mask register, it is possible to select the register to be the target of the diagnostic data protection mode, so that it is possible to set the circuit to be debugged in a sufficiently fine manner and to facilitate the debugging. ..

[Brief description of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention.

FIG. 2 is a block diagram of a second embodiment including a mask register in addition to the first embodiment.

FIG. 3 is a block diagram showing a conventional technique.

[Explanation of symbols]

 1 Diagnostic Device 20-23 Logic Circuit 30-35 Register 36 Mask Register 4 Decoder 5 Flag 60-63 AND Gate S0-S7 Scan Path C00-C16 Signal Line D00-D14 Data Path A0 Address and Write Instruction

Claims (3)

[Claims] 1. A debug for debugging an information processing apparatus by setting an initial value for a plurality of registers used in normal data processing of the information processing apparatus from a diagnostic device by using a data writing means such as a scan path. In the control method, a diagnostic data protection mode that can be set by a control instruction of the diagnostic device is provided, and when the diagnostic data protection mode is set, the data setting from the information processing device to the predetermined register is prohibited. A debug control method characterized by having a register write prohibiting means for controlling. 2. The diagnostic data protection mode can be set from the diagnostic device only when there is no logical connection between the information processing device to be diagnosed and another information processing device. The debug control method according to claim 1. 3. A mask register having a bit corresponding to the register, in which data is set by the data writing means, wherein the content of the mask register is "1".
2. The debug control system according to claim 1, further comprising: the register write prohibition unit that enables the diagnostic data protection mode only for the register corresponding to the bit set to.